Pub Date : 2024-03-01DOI: 10.1109/OJPEL.2024.3394529
Gaël Pillonnet;Patrick P. Mercier
Hybrid switched-capacitor converters (HSCCs) have gained attention due to their promising efficiency and power density compared to traditional inductor- or capacitor-based converters. However, with the recent development of various HSCC topologies, it has become increasingly challenging to choose the most suitable one for a particular application. To address this challenge, this paper proposes a benchmarking framework that enables direct comparison of direct HSCC topologies based on various performance metrics such as passives volume and bandwidth. The proposed approach, which compares all topologies at the same efficiency and output voltage ripple, provides guidelines for topology selection and optimization, ultimately contributing to wider industrial adoption and exploration of new topologies. Downloadable open-access code is also provided to recreate presented results and expand to other topologies not discussed in the paper.
{"title":"Analytical Benchmarking of Direct Hybrid Switched-Capacitor DC-DC Converters","authors":"Gaël Pillonnet;Patrick P. Mercier","doi":"10.1109/OJPEL.2024.3394529","DOIUrl":"10.1109/OJPEL.2024.3394529","url":null,"abstract":"Hybrid switched-capacitor converters (HSCCs) have gained attention due to their promising efficiency and power density compared to traditional inductor- or capacitor-based converters. However, with the recent development of various HSCC topologies, it has become increasingly challenging to choose the most suitable one for a particular application. To address this challenge, this paper proposes a benchmarking framework that enables direct comparison of direct HSCC topologies based on various performance metrics such as passives volume and bandwidth. The proposed approach, which compares all topologies at the same efficiency and output voltage ripple, provides guidelines for topology selection and optimization, ultimately contributing to wider industrial adoption and exploration of new topologies. Downloadable open-access code is also provided to recreate presented results and expand to other topologies not discussed in the paper.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10517471","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140827444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-27DOI: 10.1109/OJPEL.2024.3370712
Qiusheng Zhang;Hangzhi Liu;Yuming Zhou
The Si/SiC Cascode device has been widely accepted in various applications, however, its reliability issue still remains a major concern and needs to be extensively investigated. In this paper, the degradation of a 750 V Si/SiC Cascode device under repetitive short-circuit (SC) tests is investigated at 400 V DC-link voltage. Static and dynamic characteristics are measured before and after the repetitive SC cycles. As the SC cycle increases, the degradation of the device becomes gradually significant. By linking changes in electrical properties to metallization degradation, the physical mechanism of device degradation has been uncovered in depth. Experimental results show that the continuous stress under repetitive SC cycle leads to an increase in the on-state resistance of Si/SiC Cascode device. Finite-element-model (FEM) simulations show that due to the pad current crowding in the source region, the source Al metallization temperature of the SiC JFET rapidly increases to the melting point and undergoes reconstruction, resulting in a significant increase in the source Al metallization resistance. In addition, it is found by scanning electron microscopy (SEM) that the gate metal aluminum of SiC JFET chip also undergoes reconstruction, which is the reason for the degradation of the dynamic characteristics. The research in this paper will provide useful evidences for device manufactures to design Si/SiC Cascode device with high reliability.
硅/碳化硅级联器件在各种应用中已被广泛接受，但其可靠性问题仍是一个主要问题，需要进行广泛研究。本文研究了在 400 V 直流链路电压下，750 V Si/SiC 级联器件在重复短路（SC）测试中的劣化情况。在重复短路周期前后测量了静态和动态特性。随着 SC 周期的增加，器件的劣化逐渐显著。通过将电特性变化与金属化退化联系起来，深入揭示了器件退化的物理机制。实验结果表明，重复 SC 循环下的持续应力会导致 Si/SiC 级联器件的导通电阻增加。有限元模型（FEM）仿真显示，由于源极区域的焊盘电流拥挤，SiC JFET 的源极铝金属化温度迅速升高至熔点并发生重构，导致源极铝金属化电阻显著增加。此外，通过扫描电子显微镜（SEM）发现，SiC JFET 芯片的栅极金属铝也发生了重构，这是动态特性下降的原因。本文的研究将为器件制造商设计具有高可靠性的 Si/SiC 级联器件提供有用的证据。
{"title":"Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests","authors":"Qiusheng Zhang;Hangzhi Liu;Yuming Zhou","doi":"10.1109/OJPEL.2024.3370712","DOIUrl":"10.1109/OJPEL.2024.3370712","url":null,"abstract":"The Si/SiC Cascode device has been widely accepted in various applications, however, its reliability issue still remains a major concern and needs to be extensively investigated. In this paper, the degradation of a 750 V Si/SiC Cascode device under repetitive short-circuit (SC) tests is investigated at 400 V DC-link voltage. Static and dynamic characteristics are measured before and after the repetitive SC cycles. As the SC cycle increases, the degradation of the device becomes gradually significant. By linking changes in electrical properties to metallization degradation, the physical mechanism of device degradation has been uncovered in depth. Experimental results show that the continuous stress under repetitive SC cycle leads to an increase in the on-state resistance of Si/SiC Cascode device. Finite-element-model (FEM) simulations show that due to the pad current crowding in the source region, the source Al metallization temperature of the SiC JFET rapidly increases to the melting point and undergoes reconstruction, resulting in a significant increase in the source Al metallization resistance. In addition, it is found by scanning electron microscopy (SEM) that the gate metal aluminum of SiC JFET chip also undergoes reconstruction, which is the reason for the degradation of the dynamic characteristics. The research in this paper will provide useful evidences for device manufactures to design Si/SiC Cascode device with high reliability.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10449481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140010696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Switched capacitor multilevel inverter topologies are attractive among industrial power electronics researchers due to their applicability in sustainable energy systems such as renewable energy source (RES) applications. In this paper, a new switched capacitor (SC)-based grid-tied seven-level inverter is proposed for renewable energy sources (RES) applications. The proposed inverter can generate a seven-level output voltage waveform with voltage boosting ability and a gain factor of 3. Also, the proposed topology can provide the self voltage balancing for capacitors. The most important challenge of the SC-based topologies, i.e., the capacitor charging spike current, is solved by applying a soft charging circuit in the charging loop of the capacitors. The soft charging circuit consists of an inductor and a power diode in the capacitor charging path. Using a small size inductor in the soft charging circuit, the proposed inverter can limit the input current spikes. Comprehensive experiment results and comparisons are presented to verify the accurate performance of the proposed inverter.
{"title":"A New High Step-Up SC-Based Grid-Tied Inverter With Limited Charging Spike for RES Applications","authors":"Milad Ghavipanjeh Marangalu;Naser Vosoughi Kurdkandi;Kourosh Khalaj Monfared;Iman Talebian;Yousef Neyshabouri;Hani Vahedi","doi":"10.1109/OJPEL.2024.3366165","DOIUrl":"10.1109/OJPEL.2024.3366165","url":null,"abstract":"Switched capacitor multilevel inverter topologies are attractive among industrial power electronics researchers due to their applicability in sustainable energy systems such as renewable energy source (RES) applications. In this paper, a new switched capacitor (SC)-based grid-tied seven-level inverter is proposed for renewable energy sources (RES) applications. The proposed inverter can generate a seven-level output voltage waveform with voltage boosting ability and a gain factor of 3. Also, the proposed topology can provide the self voltage balancing for capacitors. The most important challenge of the SC-based topologies, i.e., the capacitor charging spike current, is solved by applying a soft charging circuit in the charging loop of the capacitors. The soft charging circuit consists of an inductor and a power diode in the capacitor charging path. Using a small size inductor in the soft charging circuit, the proposed inverter can limit the input current spikes. Comprehensive experiment results and comparisons are presented to verify the accurate performance of the proposed inverter.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10443380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The traditional six-step commutation control method in brushless DC motors (BLDCM) often results in significant torque ripple, which limits its application in high-precision fields. This paper proposes a scheme that combines finite control set model predictive control (FCS-MPC) to suppress commutation torque ripple. The scheme utilizes an optimal duty cycle and optimal switch compensation state. By analyzing the mathematical model of BLDC motors, the causes of commutation torque ripple were identified. To maintain the slope of the non-commutation current unchanged, a discrete model was used to predict the non-commutation current at the next moment. The predicted current was then used to calculate the optimal duty cycle. To address the shortcomings of PWM regulation performance at high speeds, a switch insertion compensation strategy was proposed. The strategy selects the optimal switch insertion compensation state based on a cost function to offset the changes in non-commutation current. Furthermore, feedback compensation was incorporated to enhance robustness in the event of parameter mismatch. The effectiveness of this method was demonstrated through experimental and simulation results.
{"title":"Torque Ripple Suppression of BLDCM With Optimal Duty Cycle and Switch State by FCS-MPC","authors":"Zicheng Li;Xiuwei Fan;Qingyao Kong;Jiang Liu;Sai Zhang","doi":"10.1109/OJPEL.2024.3368221","DOIUrl":"10.1109/OJPEL.2024.3368221","url":null,"abstract":"The traditional six-step commutation control method in brushless DC motors (BLDCM) often results in significant torque ripple, which limits its application in high-precision fields. This paper proposes a scheme that combines finite control set model predictive control (FCS-MPC) to suppress commutation torque ripple. The scheme utilizes an optimal duty cycle and optimal switch compensation state. By analyzing the mathematical model of BLDC motors, the causes of commutation torque ripple were identified. To maintain the slope of the non-commutation current unchanged, a discrete model was used to predict the non-commutation current at the next moment. The predicted current was then used to calculate the optimal duty cycle. To address the shortcomings of PWM regulation performance at high speeds, a switch insertion compensation strategy was proposed. The strategy selects the optimal switch insertion compensation state based on a cost function to offset the changes in non-commutation current. Furthermore, feedback compensation was incorporated to enhance robustness in the event of parameter mismatch. The effectiveness of this method was demonstrated through experimental and simulation results.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10443064","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.
本文基于雪崩电压箝位原理，提出了一种由碳化硅 (SiC) MOSFET 和 SiC 二极管组成的固态断路器。实现固态断路器的关键挑战在于降低传导损耗。功率半导体器件的并联是能够满足这些要求的合适配置。然而，在这种配置中，截止操作期间的电流平衡可能会受到功率半导体器件击穿电压特性变化的影响。为解决这一问题，所提出的断路器采用了碳化硅合并引脚肖特基（MPS）二极管箝位，该二极管具有较高的雪崩容限和在重复雪崩事件下的稳健特性。通过在使用 400 V、50 A 直流配电系统的非箝位感应开关（UIS）测试电路中进行实验，验证了所提出的固态断路器的有效性。最终，演示结果表明，SiC 二极管箝位方法有助于固态断路器更紧凑的实现。
{"title":"Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping","authors":"Taro Takamori;Keiji Wada;Wataru Saito;Shin-ichi Nishizawa","doi":"10.1109/OJPEL.2024.3365830","DOIUrl":"10.1109/OJPEL.2024.3365830","url":null,"abstract":"This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10436368","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-12DOI: 10.1109/OJPEL.2024.3365029
Weston D. Braun;Eric A. Stolt;Kristi Nguyen;Jeronimo Segovia-Fernandez;Sombuddha Chakraborty;Ruochen Lu;Juan M. Rivas-Davila
Piezoelectric resonators promise to increase dc-dc converter power density by replacing inductive components. However, piezoelectric resonators are not direct circuit level replacements for inductors, requiring new topologies. In this paper, we present a stacked converter using two piezoelectric resonators, providing improved efficiency at low conversion ratios. This converter is realized with a lithium niobate thickness-shear mode resonator with interdigitated electrodes that allow the two resonators required for the topology to be realized as tightly matched sub-resonators on the same substrate. The 180 V to 60 V converter operates between 6.15 MHz and 6.35 MHz and achieves a resonator-level power density of $text{1.34};text{kW}/text{cm}^{3}$ .
压电谐振器有望取代电感元件，从而提高直流-直流转换器的功率密度。然而，压电谐振器不能在电路层面直接替代电感器，需要采用新的拓扑结构。在本文中，我们介绍了一种使用两个压电谐振器的堆叠式转换器，可在低转换率下提高效率。该转换器采用铌酸锂厚度剪切模式谐振器，电极相互咬合，使拓扑结构所需的两个谐振器能够在同一基板上实现紧密匹配的子谐振器。180 V 至 60 V 转换器的工作频率为 6.15 MHz 至 6.35 MHz，谐振器级功率密度为 $text{1.34};text{kW}/text{cm}^{3}$。
{"title":"A Stacked Piezoelectric Converter Using a Segmented IDT Lithium Niobate Resonator","authors":"Weston D. Braun;Eric A. Stolt;Kristi Nguyen;Jeronimo Segovia-Fernandez;Sombuddha Chakraborty;Ruochen Lu;Juan M. Rivas-Davila","doi":"10.1109/OJPEL.2024.3365029","DOIUrl":"10.1109/OJPEL.2024.3365029","url":null,"abstract":"Piezoelectric resonators promise to increase dc-dc converter power density by replacing inductive components. However, piezoelectric resonators are not direct circuit level replacements for inductors, requiring new topologies. In this paper, we present a stacked converter using two piezoelectric resonators, providing improved efficiency at low conversion ratios. This converter is realized with a lithium niobate thickness-shear mode resonator with interdigitated electrodes that allow the two resonators required for the topology to be realized as tightly matched sub-resonators on the same substrate. The 180 V to 60 V converter operates between 6.15 MHz and 6.35 MHz and achieves a resonator-level power density of \u0000<inline-formula><tex-math>$text{1.34};text{kW}/text{cm}^{3}$</tex-math></inline-formula>\u0000.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10432952","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To safely integrate large numbers of wind turbines into the electric power grid, turbines must demonstrate compliance with grid codes and technical guidelines through rigorous testing. Such tests are traditionally performed using prototype turbines on designated measurement sites. So-called field tests offer little flexibility and repeatability, as factors such as wind and grid conditions cannot be adjusted at will. Recently, specialized laboratory test facilities were established to augment or completely replace conventional field tests. These facilities need to constantly grow in size, power, and functionality to keep up with wind turbine trends, while new and increasingly complex grid requirements necessitate more advanced testing methodologies. This paper presents four testing concepts and how they can be further integrated into the development and certification process of wind turbines using the laboratories of Fraunhofer IWES as an example. In particular, turbine, nacelle, subsystem, and component testing are reviewed and their advantages and anticipated challenges for evaluating grid code compliance are highlighted. Experiences gained over the past decade from testing wind turbines and constructing experimental testing facilities are shared, including key data and capabilities of the developed test benches. The authors expect the presented approach to be used for validating simulation models that can be embedded into larger interaction and stability studies of wind farms at a later stage. Such an integrated testing approach may lead to quicker and more flexible design and optimization of new generations of wind turbines, effectively increasing the speed of grid integration and ensuring safe and reliable grid operation.
{"title":"Opportunities and Challenges of Advanced Testing Approaches for Multi-Megawatt Wind Turbines","authors":"Florian Hans;Philipp Borowski;Jan Wendt;Gesa Quistorf;Torben Jersch","doi":"10.1109/OJPEL.2024.3364973","DOIUrl":"10.1109/OJPEL.2024.3364973","url":null,"abstract":"To safely integrate large numbers of wind turbines into the electric power grid, turbines must demonstrate compliance with grid codes and technical guidelines through rigorous testing. Such tests are traditionally performed using prototype turbines on designated measurement sites. So-called field tests offer little flexibility and repeatability, as factors such as wind and grid conditions cannot be adjusted at will. Recently, specialized laboratory test facilities were established to augment or completely replace conventional field tests. These facilities need to constantly grow in size, power, and functionality to keep up with wind turbine trends, while new and increasingly complex grid requirements necessitate more advanced testing methodologies. This paper presents four testing concepts and how they can be further integrated into the development and certification process of wind turbines using the laboratories of Fraunhofer IWES as an example. In particular, turbine, nacelle, subsystem, and component testing are reviewed and their advantages and anticipated challenges for evaluating grid code compliance are highlighted. Experiences gained over the past decade from testing wind turbines and constructing experimental testing facilities are shared, including key data and capabilities of the developed test benches. The authors expect the presented approach to be used for validating simulation models that can be embedded into larger interaction and stability studies of wind farms at a later stage. Such an integrated testing approach may lead to quicker and more flexible design and optimization of new generations of wind turbines, effectively increasing the speed of grid integration and ensuring safe and reliable grid operation.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10432956","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Virtual Impedance Shaping for the Bus Conversion System in the Hybrid AC/DC Grid","authors":"Sicong Jin, Huanyue Liao, Xin Zhang, Hao Ma, Changjiang Sun, Bin Guo","doi":"10.1109/ojpel.2024.3358787","DOIUrl":"https://doi.org/10.1109/ojpel.2024.3358787","url":null,"abstract":"","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-31DOI: 10.1109/OJPEL.2024.3360878
Xipei Yu;Junjie Feng;Liyan Zhu;Qiang Li
Recently, omnidirectional wireless power transfer (WPT) has gained increasing popularity due to its capability to charge in arbitrary positions and directions. However, existing solutions still face several challenges, including coupled coils, non-optimized structure, non-uniform magnetic field, and poor misalignment tolerance. This work proposes an omnidirectional WPT system with three fully decoupled coils consisting of one square coil and two perpendicular DD coils. Comprehensive modeling and Pareto optimization for the transmitter coil structure are conducted for improved tolerance to both lateral and angular misalignment. Experimental results are provided to validate the system performance in terms of the output voltage and efficiency under different lateral and angular misalignments. With a 12 V input, the efficiency of the system exhibits a <10% variation, ranging from 69% to 78%, with 50 mm misalignment in the x and y axes and a 90-degree angular misalignment. At the same time, the output voltage remains within the range of 11.5 V to 14.5 V.
最近，全向无线电力传输（WPT）因其能够在任意位置和方向充电而越来越受欢迎。然而，现有的解决方案仍然面临着一些挑战，包括耦合线圈、非优化结构、不均匀磁场和较差的错位容差。这项研究提出了一种全向 WPT 系统，该系统由三个完全解耦的线圈组成，其中包括一个方形线圈和两个垂直的 DD 线圈。对发射器线圈结构进行了全面建模和帕累托优化，以提高对横向和角度偏差的耐受性。实验结果验证了系统在不同横向和角度偏差下的输出电压和效率性能。在 12 V 输入电压下，系统的效率变化小于 10%，在 x 轴和 y 轴错位 50 mm 和角度错位 90 度的情况下，效率在 69% 至 78% 之间。同时，输出电压保持在 11.5 V 至 14.5 V 的范围内。
{"title":"Design and Optimization of a Planar Omnidirectional Wireless Power Transfer System for Consumer Electronics","authors":"Xipei Yu;Junjie Feng;Liyan Zhu;Qiang Li","doi":"10.1109/OJPEL.2024.3360878","DOIUrl":"10.1109/OJPEL.2024.3360878","url":null,"abstract":"Recently, omnidirectional wireless power transfer (WPT) has gained increasing popularity due to its capability to charge in arbitrary positions and directions. However, existing solutions still face several challenges, including coupled coils, non-optimized structure, non-uniform magnetic field, and poor misalignment tolerance. This work proposes an omnidirectional WPT system with three fully decoupled coils consisting of one square coil and two perpendicular DD coils. Comprehensive modeling and Pareto optimization for the transmitter coil structure are conducted for improved tolerance to both lateral and angular misalignment. Experimental results are provided to validate the system performance in terms of the output voltage and efficiency under different lateral and angular misalignments. With a 12 V input, the efficiency of the system exhibits a <10% variation, ranging from 69% to 78%, with 50 mm misalignment in the x and y axes and a 90-degree angular misalignment. At the same time, the output voltage remains within the range of 11.5 V to 14.5 V.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10417109","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-29DOI: 10.1109/OJPEL.2024.3359971
Sajjad Goudarzitaemeh;Majid Pahlevani
This paper presents a novel bidirectional DC–DC converter for several applications such as energy storage systems. The proposed power circuit topology not only has inherent soft switching but also offers reduced conduction losses. The reduction in conduction losses is achieved through a direct power transfer (DPT) path, which can effectively bypass the transformer as well as power semiconductors at the primary side, and transfer power directly to the secondary side. In addition, The power circuit offers flexibility to shape the input current waveform to have lower peak values, resulting in further reduction in conduction losses. Thus, the proposed circuit can potentially provide high efficiency by reducing both the conduction losses and switching losses simultaneously. Theoretical analysis, simulation results, and experimental results demonstrate the feasibility of the proposed circuit and its superior performance.
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