Pub Date : 2025-10-13DOI: 10.1109/OJPEL.2025.3621063
Mana Hosseinzadehlish;Saeed Jahdi;Xibo Yuan;Martin Kuball
In energy-dense power electronic applications such as electric vehicles, avalanche-induced failures represent a significant reliability risk that can impact system availability. This paper provides comprehensive measurements and modelings to investigate the robustness of high-voltage-rated Silicon and 4H-SiC bipolar junction transistors (BJTs) under unclamped inductive switching (UIS) conditions. The study employs a combination of experimental measurements and Technology Computer-Aided Design (TCAD) models to provide a comprehensive analysis of the failure mechanism of these devices under the intense electrothermal stress of avalanche mechanism. Measurements have been performed at 25 °C and 175 °C to assess the impact of elevated temperatures on the avalanche dynamics in Silicon and 4H-SiC NPN power BJTs. The UIS tests have been carried out by incrementally increase of either the DC-link voltage or the base pulse length till the device failure. It is seen that the Silicon device can tolerate higher UIS energy, due to its significantly larger die area. However, for the same UIS energy density per die area, the 4H-SiC NPN BJT clearly outperforms its Silicon counterpart.
{"title":"Analysis of Avalanche UIS Ruggedness of Vertical Power Silicon and SiC NPN BJTs","authors":"Mana Hosseinzadehlish;Saeed Jahdi;Xibo Yuan;Martin Kuball","doi":"10.1109/OJPEL.2025.3621063","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3621063","url":null,"abstract":"In energy-dense power electronic applications such as electric vehicles, avalanche-induced failures represent a significant reliability risk that can impact system availability. This paper provides comprehensive measurements and modelings to investigate the robustness of high-voltage-rated Silicon and 4H-SiC bipolar junction transistors (BJTs) under unclamped inductive switching (UIS) conditions. The study employs a combination of experimental measurements and Technology Computer-Aided Design (TCAD) models to provide a comprehensive analysis of the failure mechanism of these devices under the intense electrothermal stress of avalanche mechanism. Measurements have been performed at 25 °C and 175 °C to assess the impact of elevated temperatures on the avalanche dynamics in Silicon and 4H-SiC NPN power BJTs. The UIS tests have been carried out by incrementally increase of either the DC-link voltage or the base pulse length till the device failure. It is seen that the Silicon device can tolerate higher UIS energy, due to its significantly larger die area. However, for the same UIS energy density per die area, the 4H-SiC NPN BJT clearly outperforms its Silicon counterpart.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1828-1840"},"PeriodicalIF":3.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1109/OJPEL.2025.3620488
Quanxue Guan;Jiabei Hu;Xue Hu;Yuqian Fan;Qingling Cai;Xiaojun Tan
Deep learning methods have been widely employed to diagnose faults in power converters. However, it is challenging to diagnose multiple faults in two-stage charging power modules. Besides, diagnostic models often excel only under the exact operating conditions on which they were trained. To enable rapid and accurate open-circuit fault (OCF) diagnosis for charging pile power converters operating under varying conditions, this paper proposes an improved Light Gradient Boosting Machine (LightGBM) framework based on transfer learning. Measured waveforms are first segmented via a sliding window, from which eleven concise time-domain features are extracted and fed to the computationally efficient LightGBM for fault classification. To address the prevalent class-imbalance problem encountered in real-world fault data acquisition, this paper proposes a channel-attention-based Wasserstein generative adversarial network with a gradient penalty for data augmentation. Domain adaptation from one working condition with sufficient labelled data to other few-labelled conditions is realized through a novel dynamic re-weighting scheme from the perspectives of instance weights and feature mapping. Furthermore, a new loss function is established to integrate Maximum Mean Discrepancy for aligning the feature spaces of source and target domains, with cross-entropy for reducing the source-domain classification error. Experiments on a fast-charging power module demonstrate that the proposed lightweight method achieves an average diagnosis accuracy of 99.16% for both single- and multi-switch OCFs, and a diagnosis speed of about 13 ms across diverse load and grid conditions. It also achieves an accuracy of over 98.68% in the target condition with merely ten labeled samples, outperforming state-of-the-art alternatives. Moreover, the proposed algorithm maintains robustness under abrupt load transients and severe external noises. Compared to existing deep learning methods and state-of-the-art transfer networks, the proposed method cuts training time by one order of magnitude while maintaining the highest accuracy.
{"title":"Open-Circuit Fault Diagnosis for Charging Modules Based on Transfer Light Gradient Boosting Machine","authors":"Quanxue Guan;Jiabei Hu;Xue Hu;Yuqian Fan;Qingling Cai;Xiaojun Tan","doi":"10.1109/OJPEL.2025.3620488","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3620488","url":null,"abstract":"Deep learning methods have been widely employed to diagnose faults in power converters. However, it is challenging to diagnose multiple faults in two-stage charging power modules. Besides, diagnostic models often excel only under the exact operating conditions on which they were trained. To enable rapid and accurate open-circuit fault (OCF) diagnosis for charging pile power converters operating under varying conditions, this paper proposes an improved Light Gradient Boosting Machine (LightGBM) framework based on transfer learning. Measured waveforms are first segmented via a sliding window, from which eleven concise time-domain features are extracted and fed to the computationally efficient LightGBM for fault classification. To address the prevalent class-imbalance problem encountered in real-world fault data acquisition, this paper proposes a channel-attention-based Wasserstein generative adversarial network with a gradient penalty for data augmentation. Domain adaptation from one working condition with sufficient labelled data to other few-labelled conditions is realized through a novel dynamic re-weighting scheme from the perspectives of instance weights and feature mapping. Furthermore, a new loss function is established to integrate Maximum Mean Discrepancy for aligning the feature spaces of source and target domains, with cross-entropy for reducing the source-domain classification error. Experiments on a fast-charging power module demonstrate that the proposed lightweight method achieves an average diagnosis accuracy of 99.16% for both single- and multi-switch OCFs, and a diagnosis speed of about 13 ms across diverse load and grid conditions. It also achieves an accuracy of over 98.68% in the target condition with merely ten labeled samples, outperforming state-of-the-art alternatives. Moreover, the proposed algorithm maintains robustness under abrupt load transients and severe external noises. Compared to existing deep learning methods and state-of-the-art transfer networks, the proposed method cuts training time by one order of magnitude while maintaining the highest accuracy.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1759-1768"},"PeriodicalIF":3.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202317","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-09DOI: 10.1109/OJPEL.2025.3619673
Anugula Rajamallaiah;S.V.K. Naresh;Y. Raghuvamsi;Singamasetty Manmadharao;Kishore Bingi;Anand R;Josep M. Guerrero
Deep reinforcement learning (DRL) has emerged as a promising paradigm for the intelligent control of power electronic converters. It offers adaptability, model-free operation, and real-time decision making in complex, nonlinear, and dynamic environments. This review provides a comprehensive analysis of the state-of-the-art in DRL-based control strategies for various power converter applications. It includes voltage regulation in DC-DC converters connected to DC microgrids, speed control of permanent magnet synchronous motors (PMSM), voltage regulation and frequency modulation in dual active bridge (DAB) converters, maximum power point tracking (MPPT) in solar pv systems, and grid-connected inverter control in both grid-following and grid-forming modes. The paper systematically categorizes the recent literature based on converter topology, control objectives, DRL algorithms used, and implementation frameworks, highlighting the strengths and limitations of each approach. Special attention is given to the design of reward functions and action-state representations. Furthermore, the review identifies key challenges including stability assurance, sample inefficiency, hardware deployment constraints, and lack of standardized benchmarking environments. Finally, research gaps and future directions are outlined, emphasizing the need for physics-informed learning, safe exploration strategies, and hybrid model-based approaches to bridge the gap between academic advances and real-world deployment in power electronic systems.
{"title":"Deep Reinforcement Learning for Power Converter Control: A Comprehensive Review of Applications and Challenges","authors":"Anugula Rajamallaiah;S.V.K. Naresh;Y. Raghuvamsi;Singamasetty Manmadharao;Kishore Bingi;Anand R;Josep M. Guerrero","doi":"10.1109/OJPEL.2025.3619673","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3619673","url":null,"abstract":"Deep reinforcement learning (DRL) has emerged as a promising paradigm for the intelligent control of power electronic converters. It offers adaptability, model-free operation, and real-time decision making in complex, nonlinear, and dynamic environments. This review provides a comprehensive analysis of the state-of-the-art in DRL-based control strategies for various power converter applications. It includes voltage regulation in DC-DC converters connected to DC microgrids, speed control of permanent magnet synchronous motors (PMSM), voltage regulation and frequency modulation in dual active bridge (DAB) converters, maximum power point tracking (MPPT) in solar pv systems, and grid-connected inverter control in both grid-following and grid-forming modes. The paper systematically categorizes the recent literature based on converter topology, control objectives, DRL algorithms used, and implementation frameworks, highlighting the strengths and limitations of each approach. Special attention is given to the design of reward functions and action-state representations. Furthermore, the review identifies key challenges including stability assurance, sample inefficiency, hardware deployment constraints, and lack of standardized benchmarking environments. Finally, research gaps and future directions are outlined, emphasizing the need for physics-informed learning, safe exploration strategies, and hybrid model-based approaches to bridge the gap between academic advances and real-world deployment in power electronic systems.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1769-1802"},"PeriodicalIF":3.9,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11197642","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-08DOI: 10.1109/OJPEL.2025.3619489
Kaizhe Nie;Feng Gao;Yu Jiang
Inverter’s controller directly determines the grid-integration quality of power conversion systems. To address complex operating conditions, e.g., grid voltage distortion, parameter variations and weak grid scenarios, this paper proposes a lightweight artificial neural network (ANN) controller with strong adaptability. In implementation, the ANN controller generates control signals while simultaneously optimizing its weights in real time using the gradient descent algorithm. Distinctively, the weight gradients are directly calculated using the loss function and weights, which compared to the error backpropagation method, significantly reduces computational complexity, and therefore achieves the computational lightweight feature. In addition, the ANN phase-locked loop (ANN-PLL) is constructed to provide phase alignment for current reference while enabling fully ANN-based inverter control architecture. In principle, the proposed ANN controller relies neither on an offline training dataset nor on the system model, and achieves adaptive weights adjustment in real time with minimal computational effort. Through physical experiments, the proposed lightweight ANN controller was compared with the sliding mode controller and the model-based ANN controller, verifying its superior performance under complex operating conditions, such as grid voltage distortion, input voltage variation, current reference variation, filter parameter variation, and extremely weak grid (short circuit ratio = 1.09).
{"title":"A Lightweight ANN Controller for Grid-Tied Inverters With Strong Adaptability","authors":"Kaizhe Nie;Feng Gao;Yu Jiang","doi":"10.1109/OJPEL.2025.3619489","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3619489","url":null,"abstract":"Inverter’s controller directly determines the grid-integration quality of power conversion systems. To address complex operating conditions, e.g., grid voltage distortion, parameter variations and weak grid scenarios, this paper proposes a lightweight artificial neural network (ANN) controller with strong adaptability. In implementation, the ANN controller generates control signals while simultaneously optimizing its weights in real time using the gradient descent algorithm. Distinctively, the weight gradients are directly calculated using the loss function and weights, which compared to the error backpropagation method, significantly reduces computational complexity, and therefore achieves the computational lightweight feature. In addition, the ANN phase-locked loop (ANN-PLL) is constructed to provide phase alignment for current reference while enabling fully ANN-based inverter control architecture. In principle, the proposed ANN controller relies neither on an offline training dataset nor on the system model, and achieves adaptive weights adjustment in real time with minimal computational effort. Through physical experiments, the proposed lightweight ANN controller was compared with the sliding mode controller and the model-based ANN controller, verifying its superior performance under complex operating conditions, such as grid voltage distortion, input voltage variation, current reference variation, filter parameter variation, and extremely weak grid (short circuit ratio = 1.09).","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1803-1814"},"PeriodicalIF":3.9,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11197260","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/OJPEL.2025.3616798
Song Hu;Lei Han;Rui Wang;Chuan Sun;Yiwang Wang;Ming Lu;Xiaodong Li;Wu Chen
In this paper, an isolated bidirectional three-level neutral-point-clamped dual-bridge series resonant converter (3L-NPC-DBSRC) is proposed for the wide-voltage range dc-dc applications in energy storage systems, which consists of a neutral-point-clamped (NPC) three-level bridge on the primary side, a LC-type series-resonant tank, and a full bridge on the secondary side. The proposed 3L-NPC-DBSRC is able to realize increased voltage gain and reduced harmonic components in the primary-side high-frequency-link voltages and currents. By using fundamental harmonic analysis (FHA), the steady-state operation principles of 3L-NPC-DBSRC are thoroughly analyzed in both forward and backward power-flow directions. Furthermore, a control algorithm based on globally optimal condition (GOC) is proposed for achieving zero-voltage switching (ZVS) in all switches and minimum root-mean-square (RMS) ac-link current, thus simultaneously reducing the switching and conduction power losses, and eventually resulting in high overall efficiency. Finally, to verify the effectiveness of the proposed 3L-NPC-DBSRC and its control method, both simulations and experiments are carried out on a designed example.
{"title":"Analysis, Design, and Performance Optimization of a Bidirectional Three-Level Neutral-Point-Clamped Dual-Bridge Series Resonant DC–DC Converter for Energy Storage Systems","authors":"Song Hu;Lei Han;Rui Wang;Chuan Sun;Yiwang Wang;Ming Lu;Xiaodong Li;Wu Chen","doi":"10.1109/OJPEL.2025.3616798","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3616798","url":null,"abstract":"In this paper, an isolated bidirectional three-level neutral-point-clamped dual-bridge series resonant converter (3L-NPC-DBSRC) is proposed for the wide-voltage range dc-dc applications in energy storage systems, which consists of a neutral-point-clamped (NPC) three-level bridge on the primary side, a LC-type series-resonant tank, and a full bridge on the secondary side. The proposed 3L-NPC-DBSRC is able to realize increased voltage gain and reduced harmonic components in the primary-side high-frequency-link voltages and currents. By using fundamental harmonic analysis (FHA), the steady-state operation principles of 3L-NPC-DBSRC are thoroughly analyzed in both forward and backward power-flow directions. Furthermore, a control algorithm based on globally optimal condition (GOC) is proposed for achieving zero-voltage switching (ZVS) in all switches and minimum root-mean-square (RMS) ac-link current, thus simultaneously reducing the switching and conduction power losses, and eventually resulting in high overall efficiency. Finally, to verify the effectiveness of the proposed 3L-NPC-DBSRC and its control method, both simulations and experiments are carried out on a designed example.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1641-1655"},"PeriodicalIF":3.9,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11186209","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/OJPEL.2025.3617847
Muhammad Usman Tahir;Sajib Chakraborty;Erdem Akboy;Ariya Sangwongwanich;Daniel Ioan Stroe;Omar Hegazy;Frede Blaabjerg
Charging strategies play a key role in battery energy storage systems, specifically in applications like electric vehicles. Inefficient charging methods can increase safety risks, performance, and battery life degradation, highlighting the need to develop more advanced charging protocols. Different charging techniques have distinct effects on the LIB and DC–DC converter’s electrical and thermal performance. Therefore, this paper investigates different charging techniques in order to determine the LIB and DC–DC converter’s electrical and thermal performance parameters. The charging techniques that have been investigated are constant current (CC), multi-stage constant current (MSCC), boost current (BC) charging, and constant power (CP) charging. Results indicate notable variations in charging time, charge input capacity, converter efficiency, and thermal performance across the different strategies. For instance, CC charging exhibits higher efficiency than other charging methods despite differing temperature rise profiles in the DC–DC converter and LIB. Additionally, the CP charging strategy performs well in charged input capacity compared to other methods, with a moderate temperature rise. These results highlight the trade-offs between various performance parameters under different charging strategies. The findings highlight the importance of selecting an appropriate charging strategy based on specific performance targets.
{"title":"System-Level Performance Analysis of Li-Ion Batteries and DC–DC Converters Under Various Charging Strategies","authors":"Muhammad Usman Tahir;Sajib Chakraborty;Erdem Akboy;Ariya Sangwongwanich;Daniel Ioan Stroe;Omar Hegazy;Frede Blaabjerg","doi":"10.1109/OJPEL.2025.3617847","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3617847","url":null,"abstract":"Charging strategies play a key role in battery energy storage systems, specifically in applications like electric vehicles. Inefficient charging methods can increase safety risks, performance, and battery life degradation, highlighting the need to develop more advanced charging protocols. Different charging techniques have distinct effects on the LIB and DC–DC converter’s electrical and thermal performance. Therefore, this paper investigates different charging techniques in order to determine the LIB and DC–DC converter’s electrical and thermal performance parameters. The charging techniques that have been investigated are constant current (CC), multi-stage constant current (MSCC), boost current (BC) charging, and constant power (CP) charging. Results indicate notable variations in charging time, charge input capacity, converter efficiency, and thermal performance across the different strategies. For instance, CC charging exhibits higher efficiency than other charging methods despite differing temperature rise profiles in the DC–DC converter and LIB. Additionally, the CP charging strategy performs well in charged input capacity compared to other methods, with a moderate temperature rise. These results highlight the trade-offs between various performance parameters under different charging strategies. The findings highlight the importance of selecting an appropriate charging strategy based on specific performance targets.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1674-1684"},"PeriodicalIF":3.9,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11192747","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/OJPEL.2025.3616902
Yu-En Wu;Che-Ming Chang
This paper proposes an ultrahigh-step-down converter with a high voltage conversion ratio. The primary side of the proposed converter contains a half-bridge converter with a conventional buck converter. This design effectively reduces the voltage stress on the input-side diode and main switch while also recovering leakage inductance energy. The secondary side has a current-doubling rectification architecture, which enables zero-voltage switching and zero-current switching, thereby minimizing switching losses on the secondary-side switches and consequently improving overall efficiency. A 150-W prototype was implemented under an input voltage range of 140 to 170 V and an output voltage of 3.3 V. The efficiency and feasibility of the proposed converter were confirmed through steady-state analyses and a hardware implementation. In experiments, the peak efficiency of the prototype was 93.4% at an input of 140 V and 92.5% at an input of 170 V.
{"title":"Wide-Range Input-Isolated DC–DC Ultrahigh-Step-Down Converter Containing Buck and Half-Bridge Topologies for Low-Power Applications","authors":"Yu-En Wu;Che-Ming Chang","doi":"10.1109/OJPEL.2025.3616902","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3616902","url":null,"abstract":"This paper proposes an ultrahigh-step-down converter with a high voltage conversion ratio. The primary side of the proposed converter contains a half-bridge converter with a conventional buck converter. This design effectively reduces the voltage stress on the input-side diode and main switch while also recovering leakage inductance energy. The secondary side has a current-doubling rectification architecture, which enables zero-voltage switching and zero-current switching, thereby minimizing switching losses on the secondary-side switches and consequently improving overall efficiency. A 150-W prototype was implemented under an input voltage range of 140 to 170 V and an output voltage of 3.3 V. The efficiency and feasibility of the proposed converter were confirmed through steady-state analyses and a hardware implementation. In experiments, the peak efficiency of the prototype was 93.4% at an input of 140 V and 92.5% at an input of 170 V.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1724-1736"},"PeriodicalIF":3.9,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11189051","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-30DOI: 10.1109/OJPEL.2025.3616196
Riadh Al-Haidari;Dylan Richmond;Mohammed Alhendi;El Mehdi Abbara;Abdullah Obeidat;Firas Alshatnawi;Mark Schadt;Mark Poliks;Arun V. Gowda;Jeff Erlbaum;Han Xiong;Collin Hitchcock
The demand for compact, customized power devices is growing, driven by advancements in electric transportation and renewable energy. Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC), offer superior performance over traditional silicon (Si) due to their higher switching frequencies, improved efficiency, and greater voltage capabilities. However, conventional packaging methods often limit WBG adoption due to high costs and complexity. Additive manufacturing (AM) presents a promising alternative, enabling streamlined production, design flexibility, and reduced material waste. Leveraging AM processes and materials, significant improvements in size, weight, power density, and functionality can be realized. In this study, we demonstrated the first 1.7 kV low-profile, low-inductance multichip SiC module using direct ink writing. Finite element analysis of electrical stress defined the material requirements and design geometry, which facilitates the selection of candidate materials and processing techniques. Comprehensive testing of printed insulator and conductor materials validated their compatibility with SiC packaging requirements. Key SiC MOSFET parameters, such as on-resistance, leakage current, and threshold voltage, remained consistent with those of conventionally packaged modules and bare die performance, indicating minimal impact from AM processes. The printed modules passed a 4 kV AC isolation test, exhibited discharge-free operation up to 1.7 kV, withstood a double pulse test at 800 V / 105 A with inductance of 23.83 nH, and completed 50,000 power cycling cycles at 50 A without failure. Despite these achievements, high stress power cycling, thermal cycling and humidity bias tests revealed limitations in the current AM materials and processes, highlighting important areas for future improvement toward long-term reliability.
{"title":"Multichip SiC Power Module Packaging Using Direct Ink Writing","authors":"Riadh Al-Haidari;Dylan Richmond;Mohammed Alhendi;El Mehdi Abbara;Abdullah Obeidat;Firas Alshatnawi;Mark Schadt;Mark Poliks;Arun V. Gowda;Jeff Erlbaum;Han Xiong;Collin Hitchcock","doi":"10.1109/OJPEL.2025.3616196","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3616196","url":null,"abstract":"The demand for compact, customized power devices is growing, driven by advancements in electric transportation and renewable energy. Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC), offer superior performance over traditional silicon (Si) due to their higher switching frequencies, improved efficiency, and greater voltage capabilities. However, conventional packaging methods often limit WBG adoption due to high costs and complexity. Additive manufacturing (AM) presents a promising alternative, enabling streamlined production, design flexibility, and reduced material waste. Leveraging AM processes and materials, significant improvements in size, weight, power density, and functionality can be realized. In this study, we demonstrated the first 1.7 kV low-profile, low-inductance multichip SiC module using direct ink writing. Finite element analysis of electrical stress defined the material requirements and design geometry, which facilitates the selection of candidate materials and processing techniques. Comprehensive testing of printed insulator and conductor materials validated their compatibility with SiC packaging requirements. Key SiC MOSFET parameters, such as on-resistance, leakage current, and threshold voltage, remained consistent with those of conventionally packaged modules and bare die performance, indicating minimal impact from AM processes. The printed modules passed a 4 kV AC isolation test, exhibited discharge-free operation up to 1.7 kV, withstood a double pulse test at 800 V / 105 A with inductance of 23.83 nH, and completed 50,000 power cycling cycles at 50 A without failure. Despite these achievements, high stress power cycling, thermal cycling and humidity bias tests revealed limitations in the current AM materials and processes, highlighting important areas for future improvement toward long-term reliability.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1656-1673"},"PeriodicalIF":3.9,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11185071","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-30DOI: 10.1109/OJPEL.2025.3615672
F. M. Ibanez;Fernando Martin Porres;Mikhail Koksharov;Ainhoa Galarza
Multiple port DC/DC converters have applications in many fields: hybrid energy storage systems where batteries are combined with supercapacitors, multi-level and multi-modular inverters that need multiple DC sources, and DC microgrids. Among these converters, the multiple active bridge (MAB) is particularly attractive due to its high-power transfer and galvanic isolation capabilities. This paper introduces a predictive observer for the converter inner AC currents in order to reduce the number of required current sensors and to use only output DC current sensors. Using this observer, the control of the converter exploits the real-imaginary techniques (dq-frame) without those AC current sensors, thus reducing the cost and complexity of the sensing system and the associated required hardware. This method is verified through simulations using MATLAB/Simulink and Plexim PLECS platforms, and implemented in a 1000 W triple-port prototype. The results show that the observer does not significantly alter the response of the converter in terms of power control, reaching the steady state in around 8 ms for a step in the power reference, even considering a 50% mismatch between the observer and the real transformer windings time constants.
{"title":"DQ-Current Observer for Aiding the Control of Multiple Active Bridge Converters","authors":"F. M. Ibanez;Fernando Martin Porres;Mikhail Koksharov;Ainhoa Galarza","doi":"10.1109/OJPEL.2025.3615672","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3615672","url":null,"abstract":"Multiple port DC/DC converters have applications in many fields: hybrid energy storage systems where batteries are combined with supercapacitors, multi-level and multi-modular inverters that need multiple DC sources, and DC microgrids. Among these converters, the multiple active bridge (MAB) is particularly attractive due to its high-power transfer and galvanic isolation capabilities. This paper introduces a predictive observer for the converter inner AC currents in order to reduce the number of required current sensors and to use only output DC current sensors. Using this observer, the control of the converter exploits the real-imaginary techniques (dq-frame) without those AC current sensors, thus reducing the cost and complexity of the sensing system and the associated required hardware. This method is verified through simulations using MATLAB/Simulink and Plexim PLECS platforms, and implemented in a 1000 W triple-port prototype. The results show that the observer does not significantly alter the response of the converter in terms of power control, reaching the steady state in around 8 ms for a step in the power reference, even considering a 50% mismatch between the observer and the real transformer windings time constants.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1685-1702"},"PeriodicalIF":3.9,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11184746","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital Twin (DT) is a rapidly emerging research area, offering solutions for seamless integration between digital and physical systems, driven by advancements in Internet of Things (IoT), Machine Learning (ML), data-rich environments, and 5G networks. Simultaneously, Power Electronics Converter (PEC)s have become indispensable in modern engineering, with industries such as renewable energy, electric vehicles, transportation, home appliances, industrial automation, energy transmission, and lighting systems relying heavily on them as central components. DT for power electronics represents an ongoing research topic, yet the literature inadequately provides a comprehensive overview of DT for PECs. This paper aims to provide an overview of critical subtopics in developing DT for PECs. It offers a detailed rationale for DT research, supported by an extensive literature analysis of over 180 publications identifying key research areas. The paper also outlines existing DT standards and introduces a five-dimensional architecture for DT based on state-of-the-art literature. Additionally, it provides an in-depth review of recent advancements in power electronics essential for practical DT implementation, particularly in sensor development, PEC modelling, and DT services. The authors also highlight their contributions to DT components in modelling and Condition Monitoring (CM) for PECs, presenting results, insights, and example datasets to foster further research. A key finding of the paper is the identification of research gaps through the literature review, particularly in data acquisition techniques, integrated condition monitoring, and PEC reliability. Overall, this work provides an overview of recent progress and outlines future research needed for the real-world implementation of DT for PECs.
{"title":"Overview of Digital Twin Development in Power Electronics","authors":"Sachin Kumar Bhoi;Sajib Chakraborty;Farzad Hosseinabadi;Mohamed Amine Frikha;Gamze Egin Martin;Aldo Sorniotti;Omar Hegazy","doi":"10.1109/OJPEL.2025.3615238","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3615238","url":null,"abstract":"Digital Twin (DT) is a rapidly emerging research area, offering solutions for seamless integration between digital and physical systems, driven by advancements in Internet of Things (IoT), Machine Learning (ML), data-rich environments, and 5G networks. Simultaneously, Power Electronics Converter (PEC)s have become indispensable in modern engineering, with industries such as renewable energy, electric vehicles, transportation, home appliances, industrial automation, energy transmission, and lighting systems relying heavily on them as central components. DT for power electronics represents an ongoing research topic, yet the literature inadequately provides a comprehensive overview of DT for PECs. This paper aims to provide an overview of critical subtopics in developing DT for PECs. It offers a detailed rationale for DT research, supported by an extensive literature analysis of over 180 publications identifying key research areas. The paper also outlines existing DT standards and introduces a five-dimensional architecture for DT based on state-of-the-art literature. Additionally, it provides an in-depth review of recent advancements in power electronics essential for practical DT implementation, particularly in sensor development, PEC modelling, and DT services. The authors also highlight their contributions to DT components in modelling and Condition Monitoring (CM) for PECs, presenting results, insights, and example datasets to foster further research. A key finding of the paper is the identification of research gaps through the literature review, particularly in data acquisition techniques, integrated condition monitoring, and PEC reliability. Overall, this work provides an overview of recent progress and outlines future research needed for the real-world implementation of DT for PECs.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1737-1758"},"PeriodicalIF":3.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11184148","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：