Pub Date : 2024-01-29DOI: 10.1109/OJPEL.2024.3359479
Naveed Ishraq;Ayan Mallik
In this article, a high-efficiency and high-density 2.5 kW four-level interleaved flying capacitor multilevel (FCML) totem-pole bridgeless power-factor-correction (PFC) rectifier with 200 V GaN devices is analyzed, designed, and tested. This 2.5 kW four-level continuous conduction mode (CCM) GaN totem pole PFC operates with three times inductor current ripple frequency than that of the switching frequency which significantly reduces the size of the inductors while also supporting switching loss reduction. This article compares the loss of the two-level CCM GaN totem-pole PFC, four-level non-interleaved FCML PFC and interleaved four-level FCML PFC with the same ripple frequency (300 kHz) and shows that the interleaved four-level CCM GaN PFC has much less device loss. In addition, this article discusses the detailed EMI spectrum analysis and derivation of the mathematical model for determining the attenuation requirement of the four-level interleaved FCML PFC converter followed by volumetric co-optimization of AC-side passives i.e., the boost inductor and differential mode (DM) EMI filter. A 2.5 kW four-level interleaved FCML GaN totem-pole PFC prototype with an optimized 94 kHz switching frequency is developed and tested in this article. The converter exhibits a peak efficiency of 99.14% with system power density reaching 89.47 W/inch 3 .
本文分析、设计并测试了采用 200 V GaN 器件的高效率、高密度 2.5 kW 四电平交错飞行电容多电平（FCML）图腾极无桥功率因数校正（PFC）整流器。这种 2.5 kW 四电平连续导通模式 (CCM) GaN 图腾柱 PFC 的工作电感电流纹波频率是开关频率的三倍，从而显著减小了电感器的尺寸，同时还支持降低开关损耗。本文比较了相同纹波频率（300 kHz）下两级 CCM GaN 图腾柱 PFC、四级非交错 FCML PFC 和交错四级 FCML PFC 的损耗，结果表明交错四级 CCM GaN PFC 的器件损耗要小得多。此外，本文还讨论了详细的 EMI 频谱分析和数学模型的推导，以确定四电平交错 FCML PFC 转换器的衰减要求，然后对交流侧无源元件（即升压电感器和差模 (DM) EMI 滤波器）进行体积协同优化。本文开发并测试了一款 2.5 kW 四电平交错式 FCML GaN 图腾柱 PFC 原型，其开关频率优化为 94 kHz。该转换器的峰值效率为 99.14%，系统功率密度达到 89.47 W/inch3。
{"title":"Design of a 2.5 kW Four-Level Interleaved Flying Capacitor Multilevel Totem-Pole PFC Converter With AC-Side Passive Volume Optimization","authors":"Naveed Ishraq;Ayan Mallik","doi":"10.1109/OJPEL.2024.3359479","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3359479","url":null,"abstract":"In this article, a high-efficiency and high-density 2.5 kW four-level interleaved flying capacitor multilevel (FCML) totem-pole bridgeless power-factor-correction (PFC) rectifier with 200 V GaN devices is analyzed, designed, and tested. This 2.5 kW four-level continuous conduction mode (CCM) GaN totem pole PFC operates with three times inductor current ripple frequency than that of the switching frequency which significantly reduces the size of the inductors while also supporting switching loss reduction. This article compares the loss of the two-level CCM GaN totem-pole PFC, four-level non-interleaved FCML PFC and interleaved four-level FCML PFC with the same ripple frequency (300 kHz) and shows that the interleaved four-level CCM GaN PFC has much less device loss. In addition, this article discusses the detailed EMI spectrum analysis and derivation of the mathematical model for determining the attenuation requirement of the four-level interleaved FCML PFC converter followed by volumetric co-optimization of AC-side passives i.e., the boost inductor and differential mode (DM) EMI filter. A 2.5 kW four-level interleaved FCML GaN totem-pole PFC prototype with an optimized 94 kHz switching frequency is developed and tested in this article. The converter exhibits a peak efficiency of 99.14% with system power density reaching 89.47 W/inch\u0000<sup>3</sup>\u0000.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10415496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139715218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-29DOI: 10.1109/OJPEL.2024.3359271
Hector Sarnago;Oscar Lucía
Power electronics plays a key role in electric vehicle technology in areas such as the battery charging and managing, dc distribution and motor drive systems, among others. There are, however, significant challenges to be addressed in terms of cost, performance, reliability and power density. This paper aims at proposing an improved on-board charger architecture taking advantage of a power pulsating buffer topology. The proposed architecture will enable to significantly reduce the dc-link capacitor size, enabling a change in its technology, and leading to a higher power density and higher reliability implementation. The proposed architecture is analyzed, its main design considerations are discussed and, finally, a 3.6-kW experimental prototype is designed and implemented to prove the feasibility of this proposal. As a conclusion, the proposed topology is recommended as a high-performance high-power-density OBC implementation for future EVs.
{"title":"High Power Density On-Board Charger Featuring Power Pulsating Buffer","authors":"Hector Sarnago;Oscar Lucía","doi":"10.1109/OJPEL.2024.3359271","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3359271","url":null,"abstract":"Power electronics plays a key role in electric vehicle technology in areas such as the battery charging and managing, dc distribution and motor drive systems, among others. There are, however, significant challenges to be addressed in terms of cost, performance, reliability and power density. This paper aims at proposing an improved on-board charger architecture taking advantage of a power pulsating buffer topology. The proposed architecture will enable to significantly reduce the dc-link capacitor size, enabling a change in its technology, and leading to a higher power density and higher reliability implementation. The proposed architecture is analyzed, its main design considerations are discussed and, finally, a 3.6-kW experimental prototype is designed and implemented to prove the feasibility of this proposal. As a conclusion, the proposed topology is recommended as a high-performance high-power-density OBC implementation for future EVs.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10415508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139749897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-29DOI: 10.1109/OJPEL.2024.3359848
BART F. J. BOKMANS;Bas J. D. Vermulst;Jan M. Schellekens;Henk Huisman
In this paper an advanced modulation strategy is proposed that generates the switch control signals of a power converter while inherently guaranteeing zero-voltage switching (ZVS) operation. The proposed modulator is based on a first-order $Delta Sigma$ -modulator combined with a hold-off circuit. This hold-off circuit consists of a D-latch and maintains the converter's switching state until ZVS commutation can be achieved while an integrator ensures the correct average output. Furthermore, features are implemented to improve start-up and transient behavior. The operating principle and stability of the proposed modulator is discussed and simulation results are presented. Finally, the proposed modulator is validated on a $2 ,mathrm{k}mathrm{W}$ GaN-based synchronous buck converter. Results show that the converter naturally operates under ZVS conditions by continuously varying its switching frequency without having to compute switching times or frequencies. The proposed method is an interesting alternative to pulse-width modulation especially when operating at high switching frequencies or when the switching loss in the power converter is significant.
{"title":"A Delta-Sigma Modulated Power Converter With Inherent Zero-Voltage Switching","authors":"BART F. J. BOKMANS;Bas J. D. Vermulst;Jan M. Schellekens;Henk Huisman","doi":"10.1109/OJPEL.2024.3359848","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3359848","url":null,"abstract":"In this paper an advanced modulation strategy is proposed that generates the switch control signals of a power converter while inherently guaranteeing zero-voltage switching (ZVS) operation. The proposed modulator is based on a first-order \u0000<inline-formula><tex-math>$Delta Sigma$</tex-math></inline-formula>\u0000-modulator combined with a hold-off circuit. This hold-off circuit consists of a D-latch and maintains the converter's switching state until ZVS commutation can be achieved while an integrator ensures the correct average output. Furthermore, features are implemented to improve start-up and transient behavior. The operating principle and stability of the proposed modulator is discussed and simulation results are presented. Finally, the proposed modulator is validated on a \u0000<inline-formula><tex-math>$2 ,mathrm{k}mathrm{W}$</tex-math></inline-formula>\u0000 GaN-based synchronous buck converter. Results show that the converter naturally operates under ZVS conditions by continuously varying its switching frequency without having to compute switching times or frequencies. The proposed method is an interesting alternative to pulse-width modulation especially when operating at high switching frequencies or when the switching loss in the power converter is significant.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416366","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139727373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-26DOI: 10.1109/OJPEL.2024.3358818
Hassanien Ramadan A. Mohamed;Yasser Abdel-Rady I. Mohamed
Back-to-Back (B2B) HVDC systems can enhance cross-regional transmission capacity and overall power system stability. However, their use in interconnecting two extremely weak grids can compromise system stability. This paper presents a comprehensive stability analysis of a B2B HVDC system to distinguish the root causes of instability mechanisms and identify the critical short circuit ratio (CSCR) of each converter station under inverter and rectifier operations considering the impact of power feedforward compensation of the dc-bus voltage controller. The study also investigates the stability implications and CSCR changes when a dc transmission line connects the converter stations, creating a point-to-point (P2P) HVDC system. Eigenvalue analysis, based on detailed small-signal modeling, showed that three distinct instability mechanisms, high-, low-, and medium-frequency instabilities, can compromise the operation of VSC stations under extremely weak grid conditions. Notably, the medium-frequency instability observed in the P2P HVDC system during inverter operation is predominantly caused by the power feedforward compensation of the dc-bus voltage controller. Furthermore, the analysis reveals that the CSCRs for dc-bus voltage-controlled VSC stations are higher in comparison to power-controlled ones. This suggests that a dc-bus voltage-controlled VSC is more susceptible to instability in weak grid scenarios than its power-controlled counterpart. Active compensators are designed based on participation factor analysis to mitigate the identified instabilities. The findings are validated with extensive simulations and real-time hardware-in-the-loop tests, demonstrating the analysis's accuracy and the proposed compensators' efficacy.
{"title":"Comprehensive Analysis and Stabilization of a B2B HVDC System Connecting Two Extremely Weak Grids Considering the Impact of Power Feedforward Compensation","authors":"Hassanien Ramadan A. Mohamed;Yasser Abdel-Rady I. Mohamed","doi":"10.1109/OJPEL.2024.3358818","DOIUrl":"10.1109/OJPEL.2024.3358818","url":null,"abstract":"Back-to-Back (B2B) HVDC systems can enhance cross-regional transmission capacity and overall power system stability. However, their use in interconnecting two extremely weak grids can compromise system stability. This paper presents a comprehensive stability analysis of a B2B HVDC system to distinguish the root causes of instability mechanisms and identify the critical short circuit ratio (CSCR) of each converter station under inverter and rectifier operations considering the impact of power feedforward compensation of the dc-bus voltage controller. The study also investigates the stability implications and CSCR changes when a dc transmission line connects the converter stations, creating a point-to-point (P2P) HVDC system. Eigenvalue analysis, based on detailed small-signal modeling, showed that three distinct instability mechanisms, high-, low-, and medium-frequency instabilities, can compromise the operation of VSC stations under extremely weak grid conditions. Notably, the medium-frequency instability observed in the P2P HVDC system during inverter operation is predominantly caused by the power feedforward compensation of the dc-bus voltage controller. Furthermore, the analysis reveals that the CSCRs for dc-bus voltage-controlled VSC stations are higher in comparison to power-controlled ones. This suggests that a dc-bus voltage-controlled VSC is more susceptible to instability in weak grid scenarios than its power-controlled counterpart. Active compensators are designed based on participation factor analysis to mitigate the identified instabilities. The findings are validated with extensive simulations and real-time hardware-in-the-loop tests, demonstrating the analysis's accuracy and the proposed compensators' efficacy.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10415340","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-24DOI: 10.1109/OJPEL.2024.3357832
Niu Jia;Lingxiao Xue;Han Cui
The wide applications of wide-bandgap (WBG) devices in power electronics systems bring benefits in higher switching speed, frequency, and power density, but also cause severe electromagnetic interference (EMI) issues. While many EMI mitigation methods are available to reduce the noise generated from the source (i.e., switching WBG devices), it is equally important to analyze and control the EMI propagation paths. In WBG systems, the parasitic and coupling effects become dominant due to the high switching frequency and the compact system size, which creates uncontrolled propagation paths that degrade the systems’ EMI performance significantly. Therefore, it is crucial to investigate the parasitic and coupling effects and develop corresponding mitigation techniques. This review focuses on analyzing the EMI propagation paths to provide a comprehensive guideline to identify possible parasitics and couplings in the power module package level, EMI filter level, and the power electronics system level. The corresponding mitigation techniques for common-mode and differential-mode conducted EMI as well as radiated EMI are summarized, and the remaining challenges and future research topics are also discussed for all three levels in the conclusion.
{"title":"Mitigating EMI Noise in Propagation Paths: Review of Parasitic and Coupling Effects in Power Electronic Packages, Filters, and Systems","authors":"Niu Jia;Lingxiao Xue;Han Cui","doi":"10.1109/OJPEL.2024.3357832","DOIUrl":"10.1109/OJPEL.2024.3357832","url":null,"abstract":"The wide applications of wide-bandgap (WBG) devices in power electronics systems bring benefits in higher switching speed, frequency, and power density, but also cause severe electromagnetic interference (EMI) issues. While many EMI mitigation methods are available to reduce the noise generated from the source (i.e., switching WBG devices), it is equally important to analyze and control the EMI propagation paths. In WBG systems, the parasitic and coupling effects become dominant due to the high switching frequency and the compact system size, which creates uncontrolled propagation paths that degrade the systems’ EMI performance significantly. Therefore, it is crucial to investigate the parasitic and coupling effects and develop corresponding mitigation techniques. This review focuses on analyzing the EMI propagation paths to provide a comprehensive guideline to identify possible parasitics and couplings in the power module package level, EMI filter level, and the power electronics system level. The corresponding mitigation techniques for common-mode and differential-mode conducted EMI as well as radiated EMI are summarized, and the remaining challenges and future research topics are also discussed for all three levels in the conclusion.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10413541","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-23DOI: 10.1109/OJPEL.2024.3357128
Fangzhou Zhao;Tianhua Zhu;Lennart Harnefors;Bo Fan;Heng Wu;Zichao Zhou;Yin Sun;Xiongfei Wang
This paper derives closed-form solutions for grid-forming converters with power synchronization control (PSC) by subtly simplifying and factorizing the complex closed-loop models. The solutions can offer clear analytical insights into control-loop interactions, enabling guidelines for robust controller design. It is proved that 1) the proportional gains of PSC and alternating voltage control (AVC) can introduce negative resistance, which aggravates synchronous resonance (SR) of power control, 2) the integral gain of AVC is the cause of sub-synchronous resonance (SSR) in stiff-grid interconnections, albeit the proportional gain of AVC can help dampen the SSR, and 3) surprisingly, the current controller that dampens SR actually exacerbates SSR. Controller design guidelines are given based on analytical insights. The findings are verified by simulations and experimental results.
本文通过对复杂的闭环模型进行巧妙的简化和因式分解，得出了具有功率同步控制（PSC）功能的并网变流器的闭式解。这些解法可为控制回路的相互作用提供清晰的分析见解，从而为稳健的控制器设计提供指导。研究证明：1）PSC 和交流电压控制（AVC）的比例增益会引入负电阻，从而加剧功率控制的同步谐振（SR）；2）尽管 AVC 的比例增益有助于抑制 SSR，但 AVC 的积分增益是僵化电网互联中次同步谐振（SSR）的原因；3）令人惊讶的是，抑制 SR 的电流控制器实际上加剧了 SSR。根据分析结果给出了控制器设计指南。模拟和实验结果验证了上述结论。
{"title":"Closed-Form Solutions for Grid-Forming Converters: A Design-Oriented Study","authors":"Fangzhou Zhao;Tianhua Zhu;Lennart Harnefors;Bo Fan;Heng Wu;Zichao Zhou;Yin Sun;Xiongfei Wang","doi":"10.1109/OJPEL.2024.3357128","DOIUrl":"10.1109/OJPEL.2024.3357128","url":null,"abstract":"This paper derives closed-form solutions for grid-forming converters with power synchronization control (PSC) by subtly simplifying and factorizing the complex closed-loop models. The solutions can offer clear analytical insights into control-loop interactions, enabling guidelines for robust controller design. It is proved that 1) the proportional gains of PSC and alternating voltage control (AVC) can introduce negative resistance, which aggravates synchronous resonance (SR) of power control, 2) the integral gain of AVC is the cause of sub-synchronous resonance (SSR) in stiff-grid interconnections, albeit the proportional gain of AVC can help dampen the SSR, and 3) surprisingly, the current controller that dampens SR actually exacerbates SSR. Controller design guidelines are given based on analytical insights. The findings are verified by simulations and experimental results.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10412174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-23DOI: 10.1109/OJPEL.2024.3357073
Brandon M. Grainger;Daniel J. Carnovale
Hands-on, testing laboratories are fundamental to technical learning environments in universities. The need for modern equipment in these labs to support industry research and testing is often cost prohibitive and students and professors rely on a random collection of donated and often outdated equipment. This article focuses on the creation of a state-of-the-art medium voltage electrical power technologies lab highlighting the design, implementation and lessons learned for a modern 5 MVA system.
{"title":"13.8 kV, 5 MVA Medium Voltage Test Facility: Design, Implementation and Lessons Learned","authors":"Brandon M. Grainger;Daniel J. Carnovale","doi":"10.1109/OJPEL.2024.3357073","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3357073","url":null,"abstract":"Hands-on, testing laboratories are fundamental to technical learning environments in universities. The need for modern equipment in these labs to support industry research and testing is often cost prohibitive and students and professors rely on a random collection of donated and often outdated equipment. This article focuses on the creation of a state-of-the-art medium voltage electrical power technologies lab highlighting the design, implementation and lessons learned for a modern 5 MVA system.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10412125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139732005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-16DOI: 10.1109/OJPEL.2024.3354807
Andrea Cremasco;Daniel Rothmund;Marco Milone;Sudheer Mokkapaty;Elena A. Lomonova
The safe operation of high-power solid-state transformers (SSTs) in medium-voltage grid-connected applications relies on medium-frequency transformers (MFTs). In MFTs, hybrid foil-litz windings present a cost-effective alternative to litz wire, since foil is employed as the main conductor. This innovative topology exhibits lower ohmic losses than conventional foil windings. Besides, the dielectric stress in the insulation is mitigated, facilitating a more compact design. This paper presents the experimental validation of a ${166}; mathrm{k}mathrm{W}$ MFT prototype rated for the $ {17.5};mathrm{k}mathrm{V}$ AC/ $ {26.3}; mathrm{k}mathrm{V}$ DC insulation class. The MFT features hybrid foil-litz windings insulated with ester liquid. The design of the active parts, the insulation and the cooling system are described. The performances of alternative design concepts is evaluated. The power rating of the MFT prototype is verified experimentally by the temperature rise test at full load, operating the MFT within the cell of an SST. The insulation withstand is confirmed through dielectric tests, including AC and DC overvoltage tests up to $ {54}; mathrm{k}mathrm{V}$ peak, and the lightning impulse up to $ {95}; mathrm{k}mathrm{V}$ .
{"title":"166 kW Liquid-Insulated Medium-Frequency Transformer With Hybrid Foil-Litz Windings","authors":"Andrea Cremasco;Daniel Rothmund;Marco Milone;Sudheer Mokkapaty;Elena A. Lomonova","doi":"10.1109/OJPEL.2024.3354807","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3354807","url":null,"abstract":"The safe operation of high-power solid-state transformers (SSTs) in medium-voltage grid-connected applications relies on medium-frequency transformers (MFTs). In MFTs, hybrid foil-litz windings present a cost-effective alternative to litz wire, since foil is employed as the main conductor. This innovative topology exhibits lower ohmic losses than conventional foil windings. Besides, the dielectric stress in the insulation is mitigated, facilitating a more compact design. This paper presents the experimental validation of a \u0000<inline-formula><tex-math>${166}; mathrm{k}mathrm{W}$</tex-math></inline-formula>\u0000 MFT prototype rated for the \u0000<inline-formula><tex-math>$ {17.5};mathrm{k}mathrm{V}$</tex-math></inline-formula>\u0000 AC/\u0000<inline-formula><tex-math>$ {26.3}; mathrm{k}mathrm{V}$</tex-math></inline-formula>\u0000 DC insulation class. The MFT features hybrid foil-litz windings insulated with ester liquid. The design of the active parts, the insulation and the cooling system are described. The performances of alternative design concepts is evaluated. The power rating of the MFT prototype is verified experimentally by the temperature rise test at full load, operating the MFT within the cell of an SST. The insulation withstand is confirmed through dielectric tests, including AC and DC overvoltage tests up to \u0000<inline-formula><tex-math>$ {54}; mathrm{k}mathrm{V}$</tex-math></inline-formula>\u0000 peak, and the lightning impulse up to \u0000<inline-formula><tex-math>$ {95}; mathrm{k}mathrm{V}$</tex-math></inline-formula>\u0000.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10400858","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139749898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-12DOI: 10.1109/OJPEL.2024.3353678
Sergio Jimenez;Andrew Lemmon;Arthur Boutry
As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power module. This treatment includes an in-depth analysis of the theory of operation for this topology, as well as a set of design guidelines to facilitate the realization of practical implementations. To validate the functionality and performance of the realized prototype module, double-pulse test experiments were conducted under a wide range of operating conditions, deploying metrics specially targeted for the super-cascode switch. These experimental results demonstrate that adherence to the design guidelines provided in this paper yields a super-cascode switch with exceptional performance. In fact, the super-cascode module evaluated in this paper achieves switching performance on par with that of medium voltage SiC MOSFET modules, and far beyond that of medium voltage Si IGBT modules. Overall, this investigation contributes to the understanding of the factors driving the operation and performance of the super-cascode switch, especially under high current conditions.
随着对中压功率半导体的需求不断增加，超级级联开关已成为一种前景广阔的解决方案。本文介绍了 6.5 kV、400 A 超级级联功率模块的设计、实施和实验评估。其中包括对这种拓扑结构工作理论的深入分析，以及一套设计指南，以促进实际应用的实现。为了验证已实现原型模块的功能和性能，我们在广泛的工作条件下进行了双脉冲测试实验，采用了专门针对超级级联开关的指标。这些实验结果表明，按照本文提供的设计指南，超级级联开关具有卓越的性能。事实上，本文评估的超级级联模块的开关性能与中压 SiC MOSFET 模块相当，远远超过了中压 Si IGBT 模块。总之，这项研究有助于理解驱动超级级联开关运行和性能的因素，尤其是在大电流条件下。
{"title":"Design and Evaluation of a 6.5 kV, 400 A Super-Cascode Power Module","authors":"Sergio Jimenez;Andrew Lemmon;Arthur Boutry","doi":"10.1109/OJPEL.2024.3353678","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3353678","url":null,"abstract":"As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power module. This treatment includes an in-depth analysis of the theory of operation for this topology, as well as a set of design guidelines to facilitate the realization of practical implementations. To validate the functionality and performance of the realized prototype module, double-pulse test experiments were conducted under a wide range of operating conditions, deploying metrics specially targeted for the super-cascode switch. These experimental results demonstrate that adherence to the design guidelines provided in this paper yields a super-cascode switch with exceptional performance. In fact, the super-cascode module evaluated in this paper achieves switching performance on par with that of medium voltage SiC MOSFET modules, and far beyond that of medium voltage Si IGBT modules. Overall, this investigation contributes to the understanding of the factors driving the operation and performance of the super-cascode switch, especially under high current conditions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10398429","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139750048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-10DOI: 10.1109/OJPEL.2024.3352117
Mustapha Al Sakka;Farzad Hosseinabadi;Thomas Geury;Mohamed El Baghdadi;Monzer Al Sakka;Omar Hegazy
This article investigates and validates the applicability of the recently developed stray voltage capture (SVC) ultra-fast short-circuit (SC) detection method and its extended version (ESVC) to fault-tolerant multi-motor drives. As these methods are system-based, a fault localization algorithm is also developed. Simulation analysis of the inverter stray inductances shows additional challenges for the SVC method making it hard to achieve ultra-fast SC detection. The ESVC method is slower but overcomes these challenges. The methods are adapted for a 400 V 6-phase Silicon Carbide based inverter equipped with a 2-level turn-Off hardware protection scheme. Fault under load and hard switching fault tests are performed showing the effectiveness of the ESVC in fast (smaller than 330 ns) and reliable SC detection and protection for SiC MOSFETs. The fault localization algorithm is also validated showing a localization speed smaller than 20 μs.
{"title":"Extension of the Stray Voltage Capture Short-Circuit Detection Method to a 6-Phase Fault-Tolerant Dual-Motor Drive","authors":"Mustapha Al Sakka;Farzad Hosseinabadi;Thomas Geury;Mohamed El Baghdadi;Monzer Al Sakka;Omar Hegazy","doi":"10.1109/OJPEL.2024.3352117","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3352117","url":null,"abstract":"This article investigates and validates the applicability of the recently developed stray voltage capture (SVC) ultra-fast short-circuit (SC) detection method and its extended version (ESVC) to fault-tolerant multi-motor drives. As these methods are system-based, a fault localization algorithm is also developed. Simulation analysis of the inverter stray inductances shows additional challenges for the SVC method making it hard to achieve ultra-fast SC detection. The ESVC method is slower but overcomes these challenges. The methods are adapted for a 400 V 6-phase Silicon Carbide based inverter equipped with a 2-level turn-Off hardware protection scheme. Fault under load and hard switching fault tests are performed showing the effectiveness of the ESVC in fast (smaller than 330 ns) and reliable SC detection and protection for SiC MOSFETs. The fault localization algorithm is also validated showing a localization speed smaller than 20 μs.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10387720","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139573137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：