Pub Date : 2024-10-24DOI: 10.1109/OJPEL.2024.3485891
Anliang Hu;Jürgen Biela
Fast and accurate switching loss models that can be used for different devices are crucial for optimization-based converter design. This paper proposes a novel data sheet based, fully analytical loss model for a SiC MOSFET and Schottky diode half-bridge including parasitics. In the model, nonlinear device characteristics are approximated by multi-step piecewise constants. Furthermore, a small number of assumptions are used to derive and to solve the approximated nonlinear differential equations for obtaining the switching losses. To evaluate the model, a new accuracy measure is proposed for a fair accuracy comparison with existing models. The proposed model is also comprehensively verified by double pulse tests using 5 SiC MOSFET (with different structures) and Schottky diode pairs from different manufacturers. The proposed fully analytical model exhibits on average the best accuracy with a high computational efficiency (less than 1 ms per operating point) compared to state-of-the-art analytical switching loss models, as validated by using both data sheet information and measured device characteristics.
可用于不同器件的快速准确开关损耗模型对于基于优化的转换器设计至关重要。本文针对 SiC MOSFET 和肖特基二极管半桥（包括寄生效应）提出了一种基于数据表的新型全分析损耗模型。在该模型中，非线性器件特性由多级片式常数近似表示。此外，还使用了少量假设来推导和求解近似非线性微分方程，以获得开关损耗。为了评估该模型，提出了一种新的精度测量方法，以便与现有模型进行公平的精度比较。此外，还通过使用 5 个不同制造商生产的 SiC MOSFET（具有不同结构）和肖特基二极管对进行双脉冲测试，对所提出的模型进行了全面验证。与最先进的分析开关损耗模型相比，所提出的全分析模型平均精度最高，计算效率高（每个工作点小于 1 毫秒），数据表信息和测量的器件特性均验证了这一点。
{"title":"Fast and Accurate Data Sheet Based Analytical Switching Loss Model for a SiC MOSFET and Schottky Diode Half-Bridge","authors":"Anliang Hu;Jürgen Biela","doi":"10.1109/OJPEL.2024.3485891","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3485891","url":null,"abstract":"Fast and accurate switching loss models that can be used for different devices are crucial for optimization-based converter design. This paper proposes a novel data sheet based, fully analytical loss model for a SiC MOSFET and Schottky diode half-bridge including parasitics. In the model, nonlinear device characteristics are approximated by multi-step piecewise constants. Furthermore, a small number of assumptions are used to derive and to solve the approximated nonlinear differential equations for obtaining the switching losses. To evaluate the model, a new accuracy measure is proposed for a fair accuracy comparison with existing models. The proposed model is also comprehensively verified by double pulse tests using 5 SiC MOSFET (with different structures) and Schottky diode pairs from different manufacturers. The proposed fully analytical model exhibits on average the best accuracy with a high computational efficiency (less than 1 ms per operating point) compared to state-of-the-art analytical switching loss models, as validated by using both data sheet information and measured device characteristics.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1684-1696"},"PeriodicalIF":5.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10734143","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increasing penetration of wind turbine (WT) systems with permanent magnet synchronous generators (PMSGs) into the power grids, the back-to-back converter (BTB) has become the key element interfacing wind sources and power grids. Compared to the grid-following voltage source converter (GFL-VSC), the grid-forming VSC (GFM-VSC) shows voltage and frequency support capabilities, which meets the requirement of grid codes for WT systems. Usually, the linear regulator is employed to realize the tracking of voltage and current of GFM-VSCs, but it has limitations of complex parameter design and dynamic performance. Recently, the model predictive control (MPC) is a promising alternative controller due to the easy adoption and fast control response. This paper proposes a novel MPC method for BTB to achieve grid-forming function. The model-based control concept of the MPC effectively overcomes the complex parameter-tuning process of the cascaded linear regulators. In addition, the overshoot in the step-response of the active power of GFM-VSCs during transient process is effectively improved by using a new multi-objective cost function. The reduced power overshoot is beneficial for fully utilizing the overload capacity of the converter, avoiding damage to semiconductor devices and causing system blocking. Finally, the simulation and experiments have confirmed the feasibility of the proposed MPC method.
{"title":"A Model Predictive Control With Grid-Forming Capability for Back-to-Back Converters in Wind Turbine Systems","authors":"Zhijie Zeng;Dawei Chen;Shiyao Qin;Shuai Yuan;Zhixiang Zou;Jinyu Chen;Chen Qi","doi":"10.1109/OJPEL.2024.3476028","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3476028","url":null,"abstract":"With the increasing penetration of wind turbine (WT) systems with permanent magnet synchronous generators (PMSGs) into the power grids, the back-to-back converter (BTB) has become the key element interfacing wind sources and power grids. Compared to the grid-following voltage source converter (GFL-VSC), the grid-forming VSC (GFM-VSC) shows voltage and frequency support capabilities, which meets the requirement of grid codes for WT systems. Usually, the linear regulator is employed to realize the tracking of voltage and current of GFM-VSCs, but it has limitations of complex parameter design and dynamic performance. Recently, the model predictive control (MPC) is a promising alternative controller due to the easy adoption and fast control response. This paper proposes a novel MPC method for BTB to achieve grid-forming function. The model-based control concept of the MPC effectively overcomes the complex parameter-tuning process of the cascaded linear regulators. In addition, the overshoot in the step-response of the active power of GFM-VSCs during transient process is effectively improved by using a new multi-objective cost function. The reduced power overshoot is beneficial for fully utilizing the overload capacity of the converter, avoiding damage to semiconductor devices and causing system blocking. Finally, the simulation and experiments have confirmed the feasibility of the proposed MPC method.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1697-1708"},"PeriodicalIF":5.0,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10726784","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-16DOI: 10.1109/OJPEL.2024.3479293
Ran Yao;Zheyan Zhu;Hui Li;Wei Lai;Xianping Chen;Francesco Iannuzzo;Renkuan Liu;Xiaorong Luo
The conventional TO-247-3 packages with single-sided cooling limit the thermal and electrical performances of discrete SiC MOSFET devices. In this paper, a double-sided cooling press-pack (PP) packaging approach for the discrete SiC MOSFET device is proposed to optimize its thermal and electrical performances. First, a double-sided cooling PP structure for the discrete SiC MOSFET devices is designed with a copper foam gate pin and an embedded fixture. Then, based on finite element simulations, the steady-state thermal and electrical performances of the discrete SiC MOSFET device with the double-sided cooling PP package are analyzed, and the parasitic inductance of the designed SiC MOSFET device is extracted by the ANSYS Q3D software. Finally, a prototype of the double-sided cooling PP SiC MOSFET device is fabricated, and test platforms are established to verify its performance. The research findings demonstrate that the designed double-sided cooling PP SiC MOSFET device can reduce thermal resistance and switching loss by 47.4 % and 42.3%, respectively.
单面冷却的传统 TO-247-3 封装限制了分立式 SiC MOSFET 器件的热性能和电气性能。本文提出了一种用于分立式 SiC MOSFET 器件的双面冷却压包（PP）封装方法，以优化其热性能和电气性能。首先，设计了一种用于分立 SiC MOSFET 器件的双面冷却 PP 结构，该结构具有泡沫铜栅极引脚和嵌入式夹具。然后，基于有限元仿真，分析了采用双面冷却 PP 封装的分立 SiC MOSFET 器件的稳态热性能和电性能，并利用 ANSYS Q3D 软件提取了所设计 SiC MOSFET 器件的寄生电感。最后，制作了双面冷却 PP SiC MOSFET 器件的原型，并建立了测试平台来验证其性能。研究结果表明，所设计的双面冷却 PP SiC MOSFET 器件可将热阻和开关损耗分别降低 47.4% 和 42.3%。
{"title":"A Double-Sided Cooling Approach of Discrete SiC MOSFET Device Based on Press-Pack Package","authors":"Ran Yao;Zheyan Zhu;Hui Li;Wei Lai;Xianping Chen;Francesco Iannuzzo;Renkuan Liu;Xiaorong Luo","doi":"10.1109/OJPEL.2024.3479293","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3479293","url":null,"abstract":"The conventional TO-247-3 packages with single-sided cooling limit the thermal and electrical performances of discrete SiC MOSFET devices. In this paper, a double-sided cooling press-pack (PP) packaging approach for the discrete SiC MOSFET device is proposed to optimize its thermal and electrical performances. First, a double-sided cooling PP structure for the discrete SiC MOSFET devices is designed with a copper foam gate pin and an embedded fixture. Then, based on finite element simulations, the steady-state thermal and electrical performances of the discrete SiC MOSFET device with the double-sided cooling PP package are analyzed, and the parasitic inductance of the designed SiC MOSFET device is extracted by the ANSYS Q3D software. Finally, a prototype of the double-sided cooling PP SiC MOSFET device is fabricated, and test platforms are established to verify its performance. The research findings demonstrate that the designed double-sided cooling PP SiC MOSFET device can reduce thermal resistance and switching loss by 47.4 % and 42.3%, respectively.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1629-1640"},"PeriodicalIF":5.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10719678","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/OJPEL.2024.3481056
Hussain Sayed;Harish S. Krishnamoorthy
Managing the thermal behavior of GaN devices under test (DUT) poses significant challenges during accelerated thermal cycling (ATC) tests, particularly due to the compact packaging of small GaN devices (e.g., QFN package) and the sharp rise in the device's $R_{rm{DSon}}$ at high junction temperatures. This paper presents a framework for analyzing and modeling the thermal response performance of the ATC test setup and evaluating the impact of non-linear dissipated power on the GaN DUTs. It outlines the limitations of conventional thermal sensors in accurately estimating the DUT's junction temperature through case temperature measurements under ATC conditions. The analysis and modeling of the experimental junction temperature response function shows about 4 s time constant in the measurements using a thermistor placed near the DUT, highlighting the GaN DUT's susceptibility to thermal runaway under ATC conditions ( $T_{rm{j-max}}$ > 125 °C), where the thermal time constant significantly exceeds the DUT's thermal transient time. Consequently, an on-state resistance ( $R_{rm{DSon}}$ )-based $T_{rm{j}}$ estimation method is employed to monitor the $T_{rm{j}}$ and control the thermal cycling window boundaries effectively. Experimental investigations of several e-mode GaN HEMTs under different ATC windows are conducted to validate the ATC testing framework. Moreover, the temperature coefficient of on-state resistance (α) is characterized and quantified - considering fully packaged individual GaN DUTs’ mechanical and electrical degradation mechanisms.
在加速热循环 (ATC) 测试期间，管理 GaN 被测器件 (DUT) 的热行为是一项重大挑战，特别是由于小型 GaN 器件的紧凑封装（如 QFN 封装）以及器件在高结温下 $R_{rm{DSon}}$ 的急剧上升。本文提出了一个框架，用于分析和模拟 ATC 测试装置的热响应性能，并评估非线性耗散功率对 GaN DUT 的影响。它概述了传统热传感器在 ATC 条件下通过外壳温度测量准确估计 DUT 结温的局限性。对实验结温响应函数的分析和建模表明，在使用靠近 DUT 的热敏电阻进行测量时，时间常数约为 4 秒，这凸显了 GaN DUT 在 ATC 条件（$T_{rm{j-max}}$ > 125 °C）下容易发生热失控，热时间常数大大超过了 DUT 的热瞬态时间。因此，采用了基于导通电阻（$R_{rm{DSon}}$）的$T_{rm{j}}$估计方法来监测$T_{rm{j}}$，并有效控制热循环窗口边界。为了验证 ATC 测试框架，对不同 ATC 窗口下的几种电子模式 GaN HEMT 进行了实验研究。此外，考虑到完全封装的单个 GaN DUT 的机械和电气退化机制，对导通电阻 (α)的温度系数进行了表征和量化。
{"title":"Thermal Modeling and Degradation Profiling of E-Mode GaN HEMTs for Aging Characterization","authors":"Hussain Sayed;Harish S. Krishnamoorthy","doi":"10.1109/OJPEL.2024.3481056","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3481056","url":null,"abstract":"Managing the thermal behavior of GaN devices under test (DUT) poses significant challenges during accelerated thermal cycling (ATC) tests, particularly due to the compact packaging of small GaN devices (e.g., QFN package) and the sharp rise in the device's \u0000<inline-formula><tex-math>$R_{rm{DSon}}$</tex-math></inline-formula>\u0000 at high junction temperatures. This paper presents a framework for analyzing and modeling the thermal response performance of the ATC test setup and evaluating the impact of non-linear dissipated power on the GaN DUTs. It outlines the limitations of conventional thermal sensors in accurately estimating the DUT's junction temperature through case temperature measurements under ATC conditions. The analysis and modeling of the experimental junction temperature response function shows about 4 s time constant in the measurements using a thermistor placed near the DUT, highlighting the GaN DUT's susceptibility to thermal runaway under ATC conditions (\u0000<inline-formula><tex-math>$T_{rm{j-max}}$</tex-math></inline-formula>\u0000 > 125 °C), where the thermal time constant significantly exceeds the DUT's thermal transient time. Consequently, an on-state resistance (\u0000<inline-formula><tex-math>$R_{rm{DSon}}$</tex-math></inline-formula>\u0000)-based \u0000<inline-formula><tex-math>$T_{rm{j}}$</tex-math></inline-formula>\u0000 estimation method is employed to monitor the \u0000<inline-formula><tex-math>$T_{rm{j}}$</tex-math></inline-formula>\u0000 and control the thermal cycling window boundaries effectively. Experimental investigations of several e-mode GaN HEMTs under different ATC windows are conducted to validate the ATC testing framework. Moreover, the temperature coefficient of on-state resistance (α) is characterized and quantified - considering fully packaged individual GaN DUTs’ mechanical and electrical degradation mechanisms.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1720-1734"},"PeriodicalIF":5.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10717423","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142598605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The four-switch buck-boost (FSBB) converter is ideal for scenarios such as distributed power supply in data centers and low-voltage DC-DC in electric vehicles as a voltage regulator, because it is easy to achieve zero-voltage switch (ZVS) and has both boost and buck capabilities. In order to avoid complex real-time calculations or the need for large data storage, to realize wide input, and full load range ZVS a dual-peak current control strategy is proposed. This strategy associates two peak points of the inductor current by introducing input and output voltage to achieve the boosting and bucking. Further, the working principle of the strategy is analyzed and the RMS value of the inductor current is optimized to improve the efficiency. And the case of inductor current not being reset is analyzed and set limits to ensure the inductor current can be reset at constant frequency. The strategy can be realized by high-speed comparators as well as low-delay logic gates, thus saving the storage and computational resources of the controller. Finally, a 300 W prototype with an input voltage range of 36-60 V and an output voltage of 48 V is built to verify the correctness of the strategy.
四开关降压-升压（FSBB）转换器是数据中心分布式电源和电动汽车低压直流-直流稳压器等应用场景的理想选择，因为它易于实现零电压开关（ZVS），并同时具备升压和降压功能。为了避免复杂的实时计算或大量数据存储的需要，实现宽输入和全负载范围的 ZVS，提出了一种双峰值电流控制策略。该策略通过引入输入和输出电压，将电感器电流的两个峰值点联系起来，从而实现升压和降压。此外，还分析了该策略的工作原理，并优化了电感器电流的有效值，以提高效率。此外，还分析了电感器电流无法复位的情况，并设定了限制，以确保电感器电流能在恒定频率下复位。该策略可通过高速比较器和低延迟逻辑门实现，从而节省控制器的存储和计算资源。最后，我们制作了一个 300 W 的原型，输入电压范围为 36-60 V，输出电压为 48 V，以验证该策略的正确性。
{"title":"A Dual-Peak Current Control Strategy and Implementation for Four-Switch Buck-Boost Converter","authors":"Zhaoliang Wen;Xiangjun Zhang;Hongyu Zhang;Dianguo Xu","doi":"10.1109/OJPEL.2024.3481001","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3481001","url":null,"abstract":"The four-switch buck-boost (FSBB) converter is ideal for scenarios such as distributed power supply in data centers and low-voltage DC-DC in electric vehicles as a voltage regulator, because it is easy to achieve zero-voltage switch (ZVS) and has both boost and buck capabilities. In order to avoid complex real-time calculations or the need for large data storage, to realize wide input, and full load range ZVS a dual-peak current control strategy is proposed. This strategy associates two peak points of the inductor current by introducing input and output voltage to achieve the boosting and bucking. Further, the working principle of the strategy is analyzed and the RMS value of the inductor current is optimized to improve the efficiency. And the case of inductor current not being reset is analyzed and set limits to ensure the inductor current can be reset at constant frequency. The strategy can be realized by high-speed comparators as well as low-delay logic gates, thus saving the storage and computational resources of the controller. Finally, a 300 W prototype with an input voltage range of 36-60 V and an output voltage of 48 V is built to verify the correctness of the strategy.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1709-1719"},"PeriodicalIF":5.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10717453","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/OJPEL.2024.3478178
Francois P. du Toit;Ivan W. Hofsajer
Wide Bandgap devices are becoming more popular because of their higher switching performance. However, this higher performance comes at the cost of increased susceptibility to parasitic effects and leads to problems such as voltage overshoot and ringing of the switching node. Many strategies have been described in the literature that suppress these undesirable effects and enable faster switching. Generally, the literature describes the effectiveness of a new suppression method by experimentally comparing the outcomes when the strategy is used versus when it is not used. However there is no study that compares experimental results of the many different reported strategies with each other. This work is a meta-analysis of previously reported experimental results of WBG devices that compare the different reported strategies against one another. This shows which class of strategy holds the most promise for future development. The data presented also enables future strategies to be benchmarked against the current state-of-the-art.
{"title":"A Review of the Experimental Performance of Turn-Off Methods in Wide Bandgap Semiconductors","authors":"Francois P. du Toit;Ivan W. Hofsajer","doi":"10.1109/OJPEL.2024.3478178","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3478178","url":null,"abstract":"Wide Bandgap devices are becoming more popular because of their higher switching performance. However, this higher performance comes at the cost of increased susceptibility to parasitic effects and leads to problems such as voltage overshoot and ringing of the switching node. Many strategies have been described in the literature that suppress these undesirable effects and enable faster switching. Generally, the literature describes the effectiveness of a new suppression method by experimentally comparing the outcomes when the strategy is used versus when it is not used. However there is no study that compares experimental results of the many different reported strategies with each other. This work is a meta-analysis of previously reported experimental results of WBG devices that compare the different reported strategies against one another. This shows which class of strategy holds the most promise for future development. The data presented also enables future strategies to be benchmarked against the current state-of-the-art.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1671-1683"},"PeriodicalIF":5.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10713838","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/OJPEL.2024.3478288
Yicheng Zhu;Nathan MILES Ellis;Robert C. N. Pilawa-Podgurski
Hybrid switched-capacitor (SC) converters have received increased attention for point-of-load (PoL) applications because they can effectively leverage the superior energy density of capacitors and the improved figures-of-merit of low-voltage switching devices. This manuscript introduces an analytical framework for characterizing and comparing regulated hybrid SC topologies for direct 48-V-to-PoL conversion. In the proposed framework, a regulated hybrid SC topology is generally represented as a fixed-ratio SC stage merged with a subsequent regulated buck-type stage, with the total conversion ratio allocated between them. Three metrics are used for performance comparison: a) normalized switch stress as an indicator of efficiency, b) normalized passive component volume as an indicator of power density, and c) normalized total inductor current slew rate as an indicator of transient performance. This framework reveals that increasing the SC stage conversion ratio reduces switch stress and passive component volume while accelerating the falling slew rate of the total inductor current, thereby improving efficiency, power density, and load step-down transient performance concurrently. Although a larger SC step-down ratio typically decreases the rising slew rate of the total inductor current, potentially impairing the load step-up transient performance, proper designs can achieve balanced load step-up and step-down transient performances.
{"title":"Comparative Performance Analysis of Regulated Hybrid Switched-Capacitor Topologies for Direct 48 V to Point-of-Load Conversion","authors":"Yicheng Zhu;Nathan MILES Ellis;Robert C. N. Pilawa-Podgurski","doi":"10.1109/OJPEL.2024.3478288","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3478288","url":null,"abstract":"Hybrid switched-capacitor (SC) converters have received increased attention for point-of-load (PoL) applications because they can effectively leverage the superior energy density of capacitors and the improved figures-of-merit of low-voltage switching devices. This manuscript introduces an analytical framework for characterizing and comparing regulated hybrid SC topologies for direct 48-V-to-PoL conversion. In the proposed framework, a regulated hybrid SC topology is generally represented as a fixed-ratio SC stage merged with a subsequent regulated buck-type stage, with the total conversion ratio allocated between them. Three metrics are used for performance comparison: a) normalized switch stress as an indicator of efficiency, b) normalized passive component volume as an indicator of power density, and c) normalized total inductor current slew rate as an indicator of transient performance. This framework reveals that increasing the SC stage conversion ratio reduces switch stress and passive component volume while accelerating the falling slew rate of the total inductor current, thereby improving efficiency, power density, and load step-down transient performance concurrently. Although a larger SC step-down ratio typically decreases the rising slew rate of the total inductor current, potentially impairing the load step-up transient performance, proper designs can achieve balanced load step-up and step-down transient performances.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1735-1755"},"PeriodicalIF":5.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10713508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel modulation scheme for a multilevel Dual Active Bridge (DAB) DC–DC converter with direct power transfer capability in PV applications. The proposed modulation scheme has the ability to shape the high-frequency current waveforms, leading to lower peak/RMS values of current over a wide range of PV voltages. In addition, the multi-level structure allows for the use of low-voltage devices with significantly smaller channel resistance. The power circuit topology is based on a current-fed half-bridge (CF-HB) converter, with a coupled inductor, which facilitates the direct power transfer, resulting in significantly lower conduction losses. In summary, the proposed topology tackles both the conduction and switching losses through a multi-faceted approach by using the novel modulation scheme, the multi-level structure, the direct power transfer, and the inherent soft-switching. Detailed mathematical analysis and extensive experimental results demonstrate the superior performance of the proposed converter.
{"title":"A Multilevel Current-Fed DAB Converter With Direct Power Transfer","authors":"Sajjad Goudarzitaemeh;Lucas Melanson;Justin Woelfle;Majid Pahlevani","doi":"10.1109/OJPEL.2024.3476496","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3476496","url":null,"abstract":"This paper proposes a novel modulation scheme for a multilevel Dual Active Bridge (DAB) DC–DC converter with direct power transfer capability in PV applications. The proposed modulation scheme has the ability to shape the high-frequency current waveforms, leading to lower peak/RMS values of current over a wide range of PV voltages. In addition, the multi-level structure allows for the use of low-voltage devices with significantly smaller channel resistance. The power circuit topology is based on a current-fed half-bridge (CF-HB) converter, with a coupled inductor, which facilitates the direct power transfer, resulting in significantly lower conduction losses. In summary, the proposed topology tackles both the conduction and switching losses through a multi-faceted approach by using the novel modulation scheme, the multi-level structure, the direct power transfer, and the inherent soft-switching. Detailed mathematical analysis and extensive experimental results demonstrate the superior performance of the proposed converter.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1612-1628"},"PeriodicalIF":5.0,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10709643","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142550503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/OJPEL.2024.3476166
Chengbo Li;Ming Cheng;Wei Qin;Zheng Wang;Xiang Ma;Wei Wang
Currently, some empirical formula methods, such as the Steinmetz equation, have been widely used in calculating high-frequency magnetic core loss. Although these methods may provide satisfactory accuracy under some certain conditions, they not only cannot present clear physical interpretation and fail to account for the origin and variation of losses, but also offer much lower accuracy for wide operation ranges. In this article, a new analytical model is proposed for the first time to predict core loss by the new vector magnetic circuit theory. In addition to reluctance, two new components, i.e., magductance and hysteretance are proposed in the vector magnetic circuit, which are used to describe the eddy-current loss and the hysteresis loss, respectively. Thus, the clear physical significance is available with the proposed loss model. Given the geometrical and physical parameters of cores, the loss can be predicted. Furthermore, the uneven distribution of magnetic flux inside the magnetic core is characterized by parallel vector magnetic circuits. By comparing with the available empirical formulas, it has been proven that the proposed analytical model not only offers clear physical concepts, but also has much higher accuracy.
{"title":"Analytical Loss Model for Magnetic Cores Based on Vector Magnetic Circuit Theory","authors":"Chengbo Li;Ming Cheng;Wei Qin;Zheng Wang;Xiang Ma;Wei Wang","doi":"10.1109/OJPEL.2024.3476166","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3476166","url":null,"abstract":"Currently, some empirical formula methods, such as the Steinmetz equation, have been widely used in calculating high-frequency magnetic core loss. Although these methods may provide satisfactory accuracy under some certain conditions, they not only cannot present clear physical interpretation and fail to account for the origin and variation of losses, but also offer much lower accuracy for wide operation ranges. In this article, a new analytical model is proposed for the first time to predict core loss by the new vector magnetic circuit theory. In addition to reluctance, two new components, i.e., magductance and hysteretance are proposed in the vector magnetic circuit, which are used to describe the eddy-current loss and the hysteresis loss, respectively. Thus, the clear physical significance is available with the proposed loss model. Given the geometrical and physical parameters of cores, the loss can be predicted. Furthermore, the uneven distribution of magnetic flux inside the magnetic core is characterized by parallel vector magnetic circuits. By comparing with the available empirical formulas, it has been proven that the proposed analytical model not only offers clear physical concepts, but also has much higher accuracy.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1659-1670"},"PeriodicalIF":5.0,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10707354","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142550547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1109/OJPEL.2024.3474707
Venugopal Ramadoss;Balaji Chandrasekar;M.M.R. Ahmed;Dominic Savio A;Narayanamoorthi Rajamanickam;Thamer A. H. Alghamdi
Electric vehicles (EVs) penetrating the transportation sector are accelerated through environmental concerns, low prices, and increased power density. At the same time, the technologies for wireless charging of EVs are advancing due to their convenience, cost-effectiveness, and reliability as charging solutions. The crucial part of Wireless EV (W-EV) chargers, apart from charging pads and compensation, is the power electronics converters. These converters are essential for converting electrical energy into an appropriate form for efficient transmission and reception. This article provides a comprehensive review of the recent advancements in power converter topologies and their control methods used in W-EV chargers. Depending on the specific requirements of the W-EV charger, these converters can be classified into DC-DC, DC-AC, AC-AC, and AC-DC converters. In addition, the article explores specialized converters such as multiple-stage, multiple-phase, multiple transmitter and multiple receiver-based converters, discussing their technical details, merits and limitations. The control techniques for the power electronics converters utilised in W-EV chargers such as transmitter-side control, receiver-side control and dual controls are presented along with various technical comparative analyses. Challenges and future research directions in advanced power converter topologies for W-EV chargers are outlined at last. This article assists researchers in gaining insights into the recent technological advancements and developments aimed at enhancing the performance of the W-EV charger.
{"title":"Research Insights on Recent Power Converter Topologies and Control Strategies for Wireless EV Chargers: A Comprehensive Study","authors":"Venugopal Ramadoss;Balaji Chandrasekar;M.M.R. Ahmed;Dominic Savio A;Narayanamoorthi Rajamanickam;Thamer A. H. Alghamdi","doi":"10.1109/OJPEL.2024.3474707","DOIUrl":"https://doi.org/10.1109/OJPEL.2024.3474707","url":null,"abstract":"Electric vehicles (EVs) penetrating the transportation sector are accelerated through environmental concerns, low prices, and increased power density. At the same time, the technologies for wireless charging of EVs are advancing due to their convenience, cost-effectiveness, and reliability as charging solutions. The crucial part of Wireless EV (W-EV) chargers, apart from charging pads and compensation, is the power electronics converters. These converters are essential for converting electrical energy into an appropriate form for efficient transmission and reception. This article provides a comprehensive review of the recent advancements in power converter topologies and their control methods used in W-EV chargers. Depending on the specific requirements of the W-EV charger, these converters can be classified into DC-DC, DC-AC, AC-AC, and AC-DC converters. In addition, the article explores specialized converters such as multiple-stage, multiple-phase, multiple transmitter and multiple receiver-based converters, discussing their technical details, merits and limitations. The control techniques for the power electronics converters utilised in W-EV chargers such as transmitter-side control, receiver-side control and dual controls are presented along with various technical comparative analyses. Challenges and future research directions in advanced power converter topologies for W-EV chargers are outlined at last. This article assists researchers in gaining insights into the recent technological advancements and developments aimed at enhancing the performance of the W-EV charger.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1641-1658"},"PeriodicalIF":5.0,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10705693","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142550546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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