Pub Date : 2025-12-18DOI: 10.1109/OJPEL.2025.3645999
Liang Han;Liangzong He
Aiming at the problems of low power density and limited efficiency of the traditional two-stage single-phase Boost inverter, a high-frequency and low-frequency dual-mode control strategy is proposed. By dynamically adjusting the bus voltage waveform (partial sinusoidal form/constant DC form), the alternating high-frequency operation of the front-stage Boost converter and the rear-stage inverter is realized. When the Boost converter operates in high-frequency to match the peak/trough of the output sinusoidal voltage, a pair of power switches in the inverter is directly turned on at low frequency, which reduces switching losses. When the inverter performs high-frequency modulation on the middle section of the output sinusoidal voltage, the power switch of the Boost converter is turned off, which reduces conduction losses, and the system efficiency is improved. and improves the system efficiency. Furthermore, based on the bus voltage waveform under dual-mode control, the minimum power loss of the single-phase Boost inverter is calculated, so as to obtain the dual-mode switching point with optimal efficiency and further enhance the efficiency. This work pioneers a time-domain power processing paradigm that intelligently allocates high-frequency switching operations. Validated by a 500 W prototype, it achieves a record-high efficiency of 97.1% for its class while virtually eliminating the bulky electrolytic capacitor (96.3% volume reduction).
{"title":"Dual-Mode Control Strategy for Single-Phase Boost Inverter Based on Bus Voltage Waveform Optimization Regulation","authors":"Liang Han;Liangzong He","doi":"10.1109/OJPEL.2025.3645999","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3645999","url":null,"abstract":"Aiming at the problems of low power density and limited efficiency of the traditional two-stage single-phase Boost inverter, a high-frequency and low-frequency dual-mode control strategy is proposed. By dynamically adjusting the bus voltage waveform (partial sinusoidal form/constant DC form), the alternating high-frequency operation of the front-stage Boost converter and the rear-stage inverter is realized. When the Boost converter operates in high-frequency to match the peak/trough of the output sinusoidal voltage, a pair of power switches in the inverter is directly turned on at low frequency, which reduces switching losses. When the inverter performs high-frequency modulation on the middle section of the output sinusoidal voltage, the power switch of the Boost converter is turned off, which reduces conduction losses, and the system efficiency is improved. and improves the system efficiency. Furthermore, based on the bus voltage waveform under dual-mode control, the minimum power loss of the single-phase Boost inverter is calculated, so as to obtain the dual-mode switching point with optimal efficiency and further enhance the efficiency. This work pioneers a time-domain power processing paradigm that intelligently allocates high-frequency switching operations. Validated by a 500 W prototype, it achieves a record-high efficiency of 97.1% for its class while virtually eliminating the bulky electrolytic capacitor (96.3% volume reduction).","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"180-192"},"PeriodicalIF":3.9,"publicationDate":"2025-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11303885","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/OJPEL.2025.3644673
Arjit Bali;Xiaolong Zhang;Anubhav Bose;Kiruba S. Haran;Andrew Stillwell
Electric vehicle and electric aviation applications require lightweight electro-mechanical energy conversion. However, passive components in the drive system can constrain the power density. Slotless machines enable high power density, but their low per-phase inductance imposes significant filtering challenges. This reduced inductance necessitates additional filtering between the inverter and motor, thereby offsetting the power density advantages of slotless designs. Additionally, the dc-link capacitor constitutes a substantial portion of the inverter's weight and volume. In this paper, the advantages of interleaved and multilevel topologies are discussed, and a partially interleaved hybrid active neutral point clamped (I-HANPC) converter is proposed to achieve reduced output filter sizes and enable a smaller dc-link capacitor. The design is demonstrated using a seven-level I-HANPC experimental hardware prototype at 10 kW, achieving a peak efficiency of 98.8%, an approximately 25% reduction in dc-link capacitor RMS current, and output total harmonic distortion well below 5%.
{"title":"Analysis and Design of a Multilevel Interleaved Hybrid Active Neutral Point Clamped Inverter for Electric Aircraft Propulsion","authors":"Arjit Bali;Xiaolong Zhang;Anubhav Bose;Kiruba S. Haran;Andrew Stillwell","doi":"10.1109/OJPEL.2025.3644673","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3644673","url":null,"abstract":"Electric vehicle and electric aviation applications require lightweight electro-mechanical energy conversion. However, passive components in the drive system can constrain the power density. Slotless machines enable high power density, but their low per-phase inductance imposes significant filtering challenges. This reduced inductance necessitates additional filtering between the inverter and motor, thereby offsetting the power density advantages of slotless designs. Additionally, the dc-link capacitor constitutes a substantial portion of the inverter's weight and volume. In this paper, the advantages of interleaved and multilevel topologies are discussed, and a partially interleaved hybrid active neutral point clamped (I-HANPC) converter is proposed to achieve reduced output filter sizes and enable a smaller dc-link capacitor. The design is demonstrated using a seven-level I-HANPC experimental hardware prototype at 10 kW, achieving a peak efficiency of 98.8%, an approximately 25% reduction in dc-link capacitor RMS current, and output total harmonic distortion well below 5%.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"209-225"},"PeriodicalIF":3.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11301024","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/OJPEL.2025.3643511
GiWon Kim;HyunJoon Jeong;Jisoo Hwang;SoYoung Kim
This study presents an algorithm based on an artificial neural network (ANN) to optimize the design of inductors used in fully integrated voltage regulators (FIVRs). Because FIVRs are customized for specific chips, even identical inductor structures require adjustments based on the fabrication process and insertion method. The proposed algorithm evaluates the feasibility of inductor structures by considering their actual geometric constraints and then applies additional constraints to ensure that they remain within a user-defined inductance range. Using data from the structure identification process, the algorithm explores and optimizes structures that exceed the user-defined targets using Bayesian optimization (BO) to derive optimal results. After training, the algorithm can successfully identify inductor structures that meet target specifications and comply with relevant package design rules. Results verified through optimization examples of 5 nH and 2 nH inductors showed that in the 5 nH case, the DC resistance per unit volume decreased by 43.2% and the volume decreased by 24.5% under the same volume conditions. The proposed algorithm is versatile and can be applied to a wide range of inductor structures and designs. It efficiently identifies configurations that meet specific inductance targets. Moreover, the user-defined constraints can be adapted to various processes and insertion methods, enabling the algorithm to adjust to new targets effectively.
{"title":"Machine Learning-Based Package-Embedded Inductor Optimization for Integrated Voltage Regulators","authors":"GiWon Kim;HyunJoon Jeong;Jisoo Hwang;SoYoung Kim","doi":"10.1109/OJPEL.2025.3643511","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3643511","url":null,"abstract":"This study presents an algorithm based on an artificial neural network (ANN) to optimize the design of inductors used in fully integrated voltage regulators (FIVRs). Because FIVRs are customized for specific chips, even identical inductor structures require adjustments based on the fabrication process and insertion method. The proposed algorithm evaluates the feasibility of inductor structures by considering their actual geometric constraints and then applies additional constraints to ensure that they remain within a user-defined inductance range. Using data from the structure identification process, the algorithm explores and optimizes structures that exceed the user-defined targets using Bayesian optimization (BO) to derive optimal results. After training, the algorithm can successfully identify inductor structures that meet target specifications and comply with relevant package design rules. Results verified through optimization examples of 5 nH and 2 nH inductors showed that in the 5 nH case, the DC resistance per unit volume decreased by 43.2% and the volume decreased by 24.5% under the same volume conditions. The proposed algorithm is versatile and can be applied to a wide range of inductor structures and designs. It efficiently identifies configurations that meet specific inductance targets. Moreover, the user-defined constraints can be adapted to various processes and insertion methods, enabling the algorithm to adjust to new targets effectively.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"106-117"},"PeriodicalIF":3.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11300708","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, the hybrid dc-dc dual-path step-down topology is analyzed and selected for an automotive application due to its numerous benefits: it enables reduced inductor usage, which can be miniaturized, employs an auto-balanced flying capacitor, imposes limited stress on power switches, and offers, at the same time, a relatively wide conversion range. These features are achieved while maintaining the circuit complexity contained compared to many other competing hybrid topologies. A power loss analysis of the converter is carried out, which is exploited to obtain optimal sizing of the power stage and the inductor, and the chip architecture is described. Finally, the benefits of the topology are demonstrated experimentally through a highly-integrated prototype fabricated in $130 ,mathrm{n}mathrm{m}$ CMOS technology, capable of converting an input voltage from the range $3.3$–$4.3 ,mathrm{V}$ down to an output voltage in the range $0.7$–$1.2 ,mathrm{V}$, at a maximum power of $1.8 ,mathrm{W}$. The prototype, operating at a switching frequency of $2.5 ,mathrm{M}mathrm{Hz}$, achieves a peak efficiency of $89.7 %$ at a load current of $500 ,mathrm{m}mathrm{A}$, in a compact solution that features a power density of 1.73 $mathrm{W}$$mathrm{/}$$mathrm{m}$$mathrm{m}$$^{2}$.
{"title":"A Highly Integrated Dual-Path Step-Down Hybrid DC–DC Converter With Self-Balanced Flying Capacitor and Reduced Inductor Current","authors":"Domenico Frassetto;Stefano Cabizza;Nicolo' Zilio;Asif Karim;Cristian Garbossa;Matteo Agostinelli;Giorgio Spiazzi;Andrea Bevilacqua;Andrea Neviani","doi":"10.1109/OJPEL.2025.3644229","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3644229","url":null,"abstract":"In this article, the hybrid dc-dc dual-path step-down topology is analyzed and selected for an automotive application due to its numerous benefits: it enables reduced inductor usage, which can be miniaturized, employs an auto-balanced flying capacitor, imposes limited stress on power switches, and offers, at the same time, a relatively wide conversion range. These features are achieved while maintaining the circuit complexity contained compared to many other competing hybrid topologies. A power loss analysis of the converter is carried out, which is exploited to obtain optimal sizing of the power stage and the inductor, and the chip architecture is described. Finally, the benefits of the topology are demonstrated experimentally through a highly-integrated prototype fabricated in <inline-formula><tex-math>$130 ,mathrm{n}mathrm{m}$</tex-math></inline-formula> CMOS technology, capable of converting an input voltage from the range <inline-formula><tex-math>$3.3$</tex-math></inline-formula>–<inline-formula><tex-math>$4.3 ,mathrm{V}$</tex-math></inline-formula> down to an output voltage in the range <inline-formula><tex-math>$0.7$</tex-math></inline-formula>–<inline-formula><tex-math>$1.2 ,mathrm{V}$</tex-math></inline-formula>, at a maximum power of <inline-formula><tex-math>$1.8 ,mathrm{W}$</tex-math></inline-formula>. The prototype, operating at a switching frequency of <inline-formula><tex-math>$2.5 ,mathrm{M}mathrm{Hz}$</tex-math></inline-formula>, achieves a peak efficiency of <inline-formula><tex-math>$89.7 %$</tex-math></inline-formula> at a load current of <inline-formula><tex-math>$500 ,mathrm{m}mathrm{A}$</tex-math></inline-formula>, in a compact solution that features a power density of 1.73 <inline-formula><tex-math>$mathrm{W}$</tex-math></inline-formula><inline-formula><tex-math>$mathrm{/}$</tex-math></inline-formula><inline-formula><tex-math>$mathrm{m}$</tex-math></inline-formula><inline-formula><tex-math>$mathrm{m}$</tex-math></inline-formula><inline-formula><tex-math>$^{2}$</tex-math></inline-formula>.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"167-179"},"PeriodicalIF":3.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11299508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/OJPEL.2025.3642655
{"title":"IEEE Open Journal of Power Electronics Information for Authors","authors":"","doi":"10.1109/OJPEL.2025.3642655","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3642655","url":null,"abstract":"","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"C3-C3"},"PeriodicalIF":3.9,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11297891","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/OJPEL.2025.3642653
{"title":"IEEE Power Electronics Society Information","authors":"","doi":"10.1109/OJPEL.2025.3642653","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3642653","url":null,"abstract":"","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"C2-C2"},"PeriodicalIF":3.9,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11297959","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-10DOI: 10.1109/OJPEL.2025.3642554
Édwin Augusto Tonolo;Jefferson Wilhelm Meyer Soares;Alceu André Badin
This article proposes an interleaved modified flyback converter employing pulse frequency modulation (PFM) for power factor correction (PFC) applications. The topology integrates a switching cell (SC) and coupled inductors, enabling soft commutation over a wide frequency range, a current-fed configuration, and low input current ripple. The reverse recovery losses are eliminated as the diodes block naturally, and the switches operate under zero-voltage transition (ZVT). The converter exhibits resistive input behavior and functions as a voltage follower, allowing for simplified control with a reduced component count and a single voltage feedback loop. The main features of the proposed converter include high voltage gain, galvanic isolation, and efficient AC-DC power conversion with improved power quality. A detailed analysis of the operating principle, mathematical modeling, and design procedure is presented. Experimental validation uses a 350 W prototype operating at 69 kHz with a 127 V RMS input and a 400 V output. The results demonstrate a peak efficiency of 95.1%, a low output voltage ripple, a near-unity power factor (PF), minimal zero-crossing distortion, and a low total harmonic distortion (THD).
{"title":"An Interleaved Current-Fed PFC Flyback Converter With Voltage Follower Characteristic","authors":"Édwin Augusto Tonolo;Jefferson Wilhelm Meyer Soares;Alceu André Badin","doi":"10.1109/OJPEL.2025.3642554","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3642554","url":null,"abstract":"This article proposes an interleaved modified flyback converter employing pulse frequency modulation (PFM) for power factor correction (PFC) applications. The topology integrates a switching cell (SC) and coupled inductors, enabling soft commutation over a wide frequency range, a current-fed configuration, and low input current ripple. The reverse recovery losses are eliminated as the diodes block naturally, and the switches operate under zero-voltage transition (ZVT). The converter exhibits resistive input behavior and functions as a voltage follower, allowing for simplified control with a reduced component count and a single voltage feedback loop. The main features of the proposed converter include high voltage gain, galvanic isolation, and efficient AC-DC power conversion with improved power quality. A detailed analysis of the operating principle, mathematical modeling, and design procedure is presented. Experimental validation uses a 350 W prototype operating at 69 kHz with a 127 V RMS input and a 400 V output. The results demonstrate a peak efficiency of 95.1%, a low output voltage ripple, a near-unity power factor (PF), minimal zero-crossing distortion, and a low total harmonic distortion (THD).","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"118-127"},"PeriodicalIF":3.9,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293811","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-05DOI: 10.1109/OJPEL.2025.3640644
Xin Gao;JiangBiao He
Solid-state transformers (SSTs) are attracting increasing attention in modern power conversion systems due to their higher efficiency, improved power density, and increased power quality compared with conventional bulky electromagnetic transformers. Despite these advantages, the widespread adoption of SSTs is still limited by reliability concerns, mainly due to the large utilization of semiconductor power devices and the resulting higher probability of switch faults, among which open-circuit faults (OCFs) are probably the most common type of device failures for practical SST applications. To address this challenge, a fast online OCF diagnostic method is proposed in this paper. The method monitors abnormal variations in the high-frequency transformer current and voltage, combined with the existing real-time switching state information, to detect and identify faulty switches without requiring any additional hardware. This non-intrusive and cost-effective method avoids extra system complexity and cost, and achieves rapid OCF detection within only a few switching cycles (i.e., 30 $mu$s of detection time in this study). Simulations and experimental results validate the accuracy, robustness, and fast diagnostic capability of the proposed method under various operating conditions.
{"title":"Online Diagnosis of Open-Circuit Switch Faults in GaN DAB Converter for Solid-State Transformers","authors":"Xin Gao;JiangBiao He","doi":"10.1109/OJPEL.2025.3640644","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3640644","url":null,"abstract":"Solid-state transformers (SSTs) are attracting increasing attention in modern power conversion systems due to their higher efficiency, improved power density, and increased power quality compared with conventional bulky electromagnetic transformers. Despite these advantages, the widespread adoption of SSTs is still limited by reliability concerns, mainly due to the large utilization of semiconductor power devices and the resulting higher probability of switch faults, among which open-circuit faults (OCFs) are probably the most common type of device failures for practical SST applications. To address this challenge, a fast online OCF diagnostic method is proposed in this paper. The method monitors abnormal variations in the high-frequency transformer current and voltage, combined with the existing real-time switching state information, to detect and identify faulty switches without requiring any additional hardware. This non-intrusive and cost-effective method avoids extra system complexity and cost, and achieves rapid OCF detection within only a few switching cycles (i.e., 30 <inline-formula><tex-math>$mu$</tex-math></inline-formula>s of detection time in this study). Simulations and experimental results validate the accuracy, robustness, and fast diagnostic capability of the proposed method under various operating conditions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"59-68"},"PeriodicalIF":3.9,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278735","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/OJPEL.2025.3640291
Yifei Li;Heng Wu;Xiongfei Wang
The distinct fault characteristics of inverter-based systems, compared to those of synchronous generator (SG)-based power systems, can cause malfunctions in distance relays, including distance, directional, and phase selection elements. Recent updates to grid codes and standards aim to standardize the behavior of inverter-based resources (IBRs), ensuring their fault characteristics more closely resemble those of SG-based systems. These updates enable IBR-based systems to fulfill certain preconditions required for the reliable operation of distance relays, e.g., presenting a highly inductive IBR output impedance for negative-sequence quantities. However, due to fundamental limitations in IBR control and hardware, not all the preconditions for distance relays are met, even in systems compliant with updated grid codes. This paper reviews the preconditions necessary for reliable distance relay operation, identifying those that are fulfilled by grid code-compliant IBRs and those that remain unmet. It is found that, due to the unmet preconditions, the IBRs not only exacerbate pre-existing challenges in distance relay inherited from SG-based systems but also introduce IBR-specific issues. Finally, potential solutions to address the challenges caused by the unmet preconditions are shared.
{"title":"Challenges for Distance Relays in Grid Code-Compliant Inverter-Based Power Systems: A Review","authors":"Yifei Li;Heng Wu;Xiongfei Wang","doi":"10.1109/OJPEL.2025.3640291","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3640291","url":null,"abstract":"The distinct fault characteristics of inverter-based systems, compared to those of synchronous generator (SG)-based power systems, can cause malfunctions in distance relays, including distance, directional, and phase selection elements. Recent updates to grid codes and standards aim to standardize the behavior of inverter-based resources (IBRs), ensuring their fault characteristics more closely resemble those of SG-based systems. These updates enable IBR-based systems to fulfill certain preconditions required for the reliable operation of distance relays, e.g., presenting a highly inductive IBR output impedance for negative-sequence quantities. However, due to fundamental limitations in IBR control and hardware, not all the preconditions for distance relays are met, even in systems compliant with updated grid codes. This paper reviews the preconditions necessary for reliable distance relay operation, identifying those that are fulfilled by grid code-compliant IBRs and those that remain unmet. It is found that, due to the unmet preconditions, the IBRs not only exacerbate pre-existing challenges in distance relay inherited from SG-based systems but also introduce IBR-specific issues. Finally, potential solutions to address the challenges caused by the unmet preconditions are shared.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"128-145"},"PeriodicalIF":3.9,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11277382","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-03DOI: 10.1109/OJPEL.2025.3639525
Shuyan Zhao;Yao Wang;Reza Kheirollahi;Amr Mostafa;Hua Zhang;Fei Lu
This paper presents a high frequency high power superconducting inductive wireless power transfer system (WPT) for electric vehicle (EV) charging. There are two major contributions. First, an emerging Gadolinium Barium Copper Oxide (GdBaCuO) based high temperature superconducting (HTS) tape is adopted, targeting minimizing power loss on the magnetic coupler, and enhancing efficiency of the wireless charger. Second, a superconducting wireless charging infrastructure with underground cryogenic structure is proposed to realize a HTS transmitter-copper receiver configuration for practical EV charging scenarios. HTS based- and a copper based WPT system prototypes are implemented with liquid nitrogen (LN2) cooling at 500 kHz frequency for comparative investigations. Experiments first validate the efficiency enhancement of the HTS based WPT system compared to copper-based counterpart at a relatively lower output power of 1 kW. Then experiments further validate the power transfer performance of the HTS WPT system, with 3.44 kW output power at a 95.05% dc–dc efficiency, and the peak efficiency achieves 97.01% at 1.87 kW output power.
{"title":"Superconducting Inductive Wireless Power Transfer System With Underground Cryogenic Transmitter Structure for Electric Vehicle Charging","authors":"Shuyan Zhao;Yao Wang;Reza Kheirollahi;Amr Mostafa;Hua Zhang;Fei Lu","doi":"10.1109/OJPEL.2025.3639525","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3639525","url":null,"abstract":"This paper presents a high frequency high power superconducting inductive wireless power transfer system (WPT) for electric vehicle (EV) charging. There are two major contributions. First, an emerging Gadolinium Barium Copper Oxide (GdBaCuO) based high temperature superconducting (HTS) tape is adopted, targeting minimizing power loss on the magnetic coupler, and enhancing efficiency of the wireless charger. Second, a superconducting wireless charging infrastructure with underground cryogenic structure is proposed to realize a HTS transmitter-copper receiver configuration for practical EV charging scenarios. HTS based- and a copper based WPT system prototypes are implemented with liquid nitrogen (LN<sub>2</sub>) cooling at 500 kHz frequency for comparative investigations. Experiments first validate the efficiency enhancement of the HTS based WPT system compared to copper-based counterpart at a relatively lower output power of 1 kW. Then experiments further validate the power transfer performance of the HTS WPT system, with 3.44 kW output power at a 95.05% dc–dc efficiency, and the peak efficiency achieves 97.01% at 1.87 kW output power.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"69-78"},"PeriodicalIF":3.9,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11275640","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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