Pub Date : 2024-07-15DOI: 10.1109/JMW.2024.3413865
Sebastien Fregonese;Thomas Zimmer
This work focuses on a novel methodology to establish on-wafer calibration standards for the 16-Term Error Calibration Technique. It combines TRL-calibrated data with EM simulation to precisely generate S-parameters of standards. Applied to the advanced BiCMOS 55 nm technology, with a layout maintaining consistent coupling between standards, the 16 error-terms calibration results in significant improvements from 40 GHz onward compared to standard calibration (SOLT or TRL) techniques. Notably, it corrects probe couplings, eliminates discontinuities between frequency bands, and ensures the accuracy of S-parameter measurements. Unlike traditional SOLT and TRL methods, this new approach attributes measured quantities solely to intrinsic transistor behavior.
这项工作的重点是为 16 期误差校准技术建立晶圆上校准标准的新方法。它将 TRL 校准数据与电磁模拟相结合,精确生成标准的 S 参数。与标准校准(SOLT 或 TRL)技术相比,16 误差项校准应用于先进的 BiCMOS 55 nm 技术,其布局保持了标准之间的一致耦合。特别是,它校正了探头耦合,消除了频带之间的不连续性,并确保了 S 参数测量的准确性。与传统的 SOLT 和 TRL 方法不同,这一新方法将测量量完全归因于晶体管的内在行为。
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