Pub Date : 2023-01-01DOI: 10.12677/ojcs.2023.121001
吉飞 杜
The wireless charging module designed in this paper uses the principle of magnetic coupling resonant wireless charging, uses DC power supply mode to convert into the required alternating current through the inverter circuit, generates high-frequency sinusoidal oscillation current to drive the transmitting coil, makes the transmitting circuit in a resonant state, transmits energy to
{"title":"Study on AC/DC Power Converter Based on Magnetic Coupling Resonance","authors":"吉飞 杜","doi":"10.12677/ojcs.2023.121001","DOIUrl":"https://doi.org/10.12677/ojcs.2023.121001","url":null,"abstract":"The wireless charging module designed in this paper uses the principle of magnetic coupling resonant wireless charging, uses DC power supply mode to convert into the required alternating current through the inverter circuit, generates high-frequency sinusoidal oscillation current to drive the transmitting coil, makes the transmitting circuit in a resonant state, transmits energy to","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84939123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3237839
Yanhan Zeng;Zhixian Li;Weijian Chen;Wei Zhou;Yuchen Bao;Yongsen Chen;Yongfu Li
This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in $0.18 ~mu text{m}$ CMOS process, the circuit only occupies an area of $0.122 mm^{2}$ and consumes $0.62 ~mu text{W}$ at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30–45 dB and 65–105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.
{"title":"A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector","authors":"Yanhan Zeng;Zhixian Li;Weijian Chen;Wei Zhou;Yuchen Bao;Yongsen Chen;Yongfu Li","doi":"10.1109/OJCAS.2023.3237839","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3237839","url":null,"abstract":"This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in <inline-formula> <tex-math notation=\"LaTeX\">$0.18 ~mu text{m}$ </tex-math></inline-formula> CMOS process, the circuit only occupies an area of <inline-formula> <tex-math notation=\"LaTeX\">$0.122 mm^{2}$ </tex-math></inline-formula> and consumes <inline-formula> <tex-math notation=\"LaTeX\">$0.62 ~mu text{W}$ </tex-math></inline-formula> at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30–45 dB and 65–105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"25-35"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10020171.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dB $Omega $ , a BW of 14.8 GHz, an input-referred noise of 33.6 pA/ $surd $ Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consumes 49 mW and occupies an active area of 0.0076 mm 2.
本文介绍了一种可提供高增益增益积的全差分跨阻放大器(TIA)。在所提出的结构中，采用级联码交叉耦合结构使级联码器件的有效跨导率增加一倍，从而提高了TIA的BW。此外，差分架构使用RC高通滤波器以及需要更小电容和电阻的缓冲级来实现。此外，在TIA的输入端采用了一个单端负电容产生(NCG)电路来部分补偿输入寄生电容。采用16nm FinFET工艺设计和布局的TIA，与采用所提出的TIA设计的级联编码和传统TIA相比，分别表现出57%和79%的优势。通过布局后仿真和统计分析，验证了该结构的有效性。仿真结果表明，在数据速率为56 Gbps PAM4、误码率(BER)为1e6的情况下，光接收机的峰值透阻增益为58.5 dB $Omega $， BW为14.8 GHz，输入参考噪声为33.6 pA/ $ $ surd $ Hz，开眼值为30 mV。整个电路消耗49 mW，占用0.0076 mm 2的有源面积。
{"title":"An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process","authors":"Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2023.3236567","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3236567","url":null,"abstract":"In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dB $Omega $ , a BW of 14.8 GHz, an input-referred noise of 33.6 pA/ $surd $ Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consumes 49 mW and occupies an active area of 0.0076 mm 2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"36-49"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10015890.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3292712
Dong-Hyun Seo;Archisman Ghosh;Debayan Das;Mayukh Nath;Santosh Ghosh;Shreyas Sen
This paper presents the design and analysis of a pro-active strategy to detect the presence of an electromagnetic (EM) side-channel analysis (SCA) attack, using Patterned-Ground co-planar Capacitive Asymmetry Sensing (PG-CAS) system. The PG-CAS system senses the asymmetry created in the plate-ground capacitance and turns on a SCA countermeasure in presence of an EM probe. The proposed PG-CAS system for approaching probe consists of the EM SCA detection sensor plate and circuits. The EM SCA detection sensor is implemented as a grid of four metal plates of the same dimensions using the top metal layer along with a patterned-ground plane at the immediate lower metal layer. The EM SCA detection system consists of a proximity to capacitance conversion circuit, digital synchronization logic circuit to detect and alarm the IC, and an EM SCA countermeasure. When an attack is detected, the countermeasure is turned on based on the deviation of the symmetry of the plate-ground capacitance pairs. The PG-CAS system-level post-layout simulation results using TSMC 65nm technology and Ansys Maxwell show a $>5times $ improvement in the detection range and a $sim 29times $ improvement in power consumption over existing inductive sensing methods for attack detection.
{"title":"PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing","authors":"Dong-Hyun Seo;Archisman Ghosh;Debayan Das;Mayukh Nath;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJCAS.2023.3292712","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3292712","url":null,"abstract":"This paper presents the design and analysis of a pro-active strategy to detect the presence of an electromagnetic (EM) side-channel analysis (SCA) attack, using Patterned-Ground co-planar Capacitive Asymmetry Sensing (PG-CAS) system. The PG-CAS system senses the asymmetry created in the plate-ground capacitance and turns on a SCA countermeasure in presence of an EM probe. The proposed PG-CAS system for approaching probe consists of the EM SCA detection sensor plate and circuits. The EM SCA detection sensor is implemented as a grid of four metal plates of the same dimensions using the top metal layer along with a patterned-ground plane at the immediate lower metal layer. The EM SCA detection system consists of a proximity to capacitance conversion circuit, digital synchronization logic circuit to detect and alarm the IC, and an EM SCA countermeasure. When an attack is detected, the countermeasure is turned on based on the deviation of the symmetry of the plate-ground capacitance pairs. The PG-CAS system-level post-layout simulation results using TSMC 65nm technology and Ansys Maxwell show a $>5times $ improvement in the detection range and a $sim 29times $ improvement in power consumption over existing inductive sensing methods for attack detection.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"271-282"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10192257.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.12677/ojcs.2023.122003
雨泽 李
In this paper
{"title":"Design of a Non-Contact Human Sign Monitoring System Based on Microwave Sensors","authors":"雨泽 李","doi":"10.12677/ojcs.2023.122003","DOIUrl":"https://doi.org/10.12677/ojcs.2023.122003","url":null,"abstract":"In this paper","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"20 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87755717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2024.3356108
{"title":"2023 Index IEEE Open Journal of Circuits and Systems Vol. 4","authors":"","doi":"10.1109/OJCAS.2024.3356108","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3356108","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"363-369"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10410125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139504507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.12677/ojcs.2023.122002
启煌 朱
Due to the change in automobile working conditions, the structure coefficient of automobile power battery pack also appears to nonlinear change. In order to realize efficient control of such nonlinear battery components, this paper chooses the second-order RC model as the equivalent circuit model of the battery, and uses the constant current charge-discharge test of the battery, the calibra-朱启煌
{"title":"Research on Model Parameter Identification of Lithium Ion Battery","authors":"启煌 朱","doi":"10.12677/ojcs.2023.122002","DOIUrl":"https://doi.org/10.12677/ojcs.2023.122002","url":null,"abstract":"Due to the change in automobile working conditions, the structure coefficient of automobile power battery pack also appears to nonlinear change. In order to realize efficient control of such nonlinear battery components, this paper chooses the second-order RC model as the equivalent circuit model of the battery, and uses the constant current charge-discharge test of the battery, the calibra-朱启煌","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"44 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81867409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2022.3232638
Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander
Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in $0.35 mu mathrm{m}$ CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape $Pleft(T_Eright)$ and yield loss $Pleft(Y_Lright)$ of $5 cdot 10^{-2}$ and $1.89 cdot 10^{-2}$ respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.
基于振荡的测试(OBT)和基于振荡的内置自检(OBIST)电路能够检测模拟和射频电路中的灾难性故障，但两者都对过程、电压和温度(PVT)变化敏感。本文研究了15种OBT和OBIST特征提取策略，以及四种阈值选择方法，通过计算PVT变化的价值图(FOM)。这是使用$0.35 mu mathrm{m}$ CMOS中的2.4 GHz LNA作为DUT完成的。在15种特征提取方法中，OBT方法被发现更有效，并且从切换状态检测中获得了一些好处。在四种阈值选择方法(名义范围静态阈值、极端范围静态阈值、温度动态阈值和简单噪声滤波的色调检测)中，动态阈值的平均FoM最高为0.919，最佳FoM为0.952，相应的试验逃逸概率$Pleft(T_Eright)$和产量损失$Pleft(Y_Lright)$分别为$5 cdot 10^{-2}$和$1.89 cdot 10^{-2}$，但需要精确的温度测量。极端静态阈值选择导致平均FoM为0.912，但对工艺变化的敏感性较低，不需要测量温度。对噪声滤波后的振荡音调进行二值检测是最简单的方法，其平均FoM为0.891。
{"title":"Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers","authors":"Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander","doi":"10.1109/OJCAS.2022.3232638","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3232638","url":null,"abstract":"Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in <inline-formula> <tex-math notation=\"LaTeX\">$0.35 mu mathrm{m}$ </tex-math></inline-formula> CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(T_Eright)$ </tex-math></inline-formula> and yield loss <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(Y_Lright)$ </tex-math></inline-formula> of <inline-formula> <tex-math notation=\"LaTeX\">$5 cdot 10^{-2}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$1.89 cdot 10^{-2}$ </tex-math></inline-formula> respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"70-84"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10002329.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3245061
Tsung-Han Tsai;Ding-Bang Lin
In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since neural network algorithms are computationally intensive, they require GPUs or accelerated hardware for real-time computation. However, the high cost and high power consumption of GPUs result in low energy efficiency. It recently led to much research on accelerated digital circuit hardware design for deep neural networks. In this paper, we propose an efficient and flexible neural network training processor for fully connected layers. Our proposed training processor features low power consumption, high throughput, and high energy efficiency. It uses the sparsity of neuron activations to reduce the number of memory accesses and memory space to achieve an efficient training accelerator. The proposed processor uses a novel reconfigurable computing architecture to maintain high performance when operating Forward Propagation and Backward Propagation. The processor is implemented in Xilinx Zynq UltraSacle+MPSoC ZCU104 FPGA, with an operating frequency of 200MHz and power consumption of 6.444W, and can achieve 102.43 GOPS.
{"title":"An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness","authors":"Tsung-Han Tsai;Ding-Bang Lin","doi":"10.1109/OJCAS.2023.3245061","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3245061","url":null,"abstract":"In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since neural network algorithms are computationally intensive, they require GPUs or accelerated hardware for real-time computation. However, the high cost and high power consumption of GPUs result in low energy efficiency. It recently led to much research on accelerated digital circuit hardware design for deep neural networks. In this paper, we propose an efficient and flexible neural network training processor for fully connected layers. Our proposed training processor features low power consumption, high throughput, and high energy efficiency. It uses the sparsity of neuron activations to reduce the number of memory accesses and memory space to achieve an efficient training accelerator. The proposed processor uses a novel reconfigurable computing architecture to maintain high performance when operating Forward Propagation and Backward Propagation. The processor is implemented in Xilinx Zynq UltraSacle+MPSoC ZCU104 FPGA, with an operating frequency of 200MHz and power consumption of 6.444W, and can achieve 102.43 GOPS.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"85-98"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10051716.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3262204
Richelle L. Smith;Thomas H. Lee
This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking. Four possible states per oscillator are encoded in a polychronous fashion, where the steady state oscillator phases are analogous to the time-locked neuronal firing patterns of polychronous neurons. We apply impulse sensitivity function (ISF) theory to model and optimize the high-order injection locking of the oscillators. CMOS circuit design of a polychronous oscillatory neural network is presented, and coloring of a geographic map is demonstrated, with simulation results and design guidelines. There is good agreement between theory and Spectre simulation.
{"title":"Polychronous Oscillatory Cellular Neural Networks for Solving Graph Coloring Problems","authors":"Richelle L. Smith;Thomas H. Lee","doi":"10.1109/OJCAS.2023.3262204","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3262204","url":null,"abstract":"This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking. Four possible states per oscillator are encoded in a polychronous fashion, where the steady state oscillator phases are analogous to the time-locked neuronal firing patterns of polychronous neurons. We apply impulse sensitivity function (ISF) theory to model and optimize the high-order injection locking of the oscillators. CMOS circuit design of a polychronous oscillatory neural network is presented, and coloring of a geographic map is demonstrated, with simulation results and design guidelines. There is good agreement between theory and Spectre simulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"156-164"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10081435.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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