Pub Date : 2025-12-26DOI: 10.1109/TNANO.2025.3648734
L. Hemanth Krishna;B. Srinivasu;K. Sridharan
In this paper, we present efficient designs of approximate ternary multipliers applicable to several emerging nanodevices. The proposed multipliers are motivated by the multiply-and-accumulate (MAC) operation in convolutional neural networks (CNNs). In particular, CNN applications in imaging are resilient to errors and it is therefore advantageous to examine methods that save energy and reduce the delay. Two approximate single-digit ternary multipliers are proposed. The single-digit approximate multipliers are used to develop an approximate $3 times 3$ and $6 times 6$ ternary multipliers. The proposed approximate $6 times 6$ multiplier saves energy in the range of 22% to 40% over recent approximate designs. Further, there is a reduction of delay of roughly 21$%$ with the proposed multipliers over the best existing design. The multipliers are based on their exact counterparts which are, in turn, developed using an efficient exact ternary carry adder (TCAD) that generates the sum of two carry outputs of a single ternary digit multiplier. The application of the approximate multipliers to CNN-based imaging is then demonstrated. In particular, the proposed approximate multipliers have excellent performance for CNN-based image denoising. Further, the approximate multipliers show good performance on MNIST and CIFAR-10 datasets. Simulations for Carbon Nanotube FET (CNTFET) reveal energy savings in excess of 50% over the best existing multipliers.
{"title":"Efficient Approximate Ternary Multipliers for Emerging Nanodevices","authors":"L. Hemanth Krishna;B. Srinivasu;K. Sridharan","doi":"10.1109/TNANO.2025.3648734","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3648734","url":null,"abstract":"In this paper, we present efficient designs of <italic>approximate ternary multipliers</i> applicable to several emerging nanodevices. The proposed multipliers are motivated by the multiply-and-accumulate (MAC) operation in convolutional neural networks (CNNs). In particular, CNN applications in imaging are resilient to errors and it is therefore advantageous to examine methods that save energy and reduce the delay. Two <italic>approximate single-digit ternary multipliers</i> are proposed. The single-digit approximate multipliers are used to develop an approximate <inline-formula><tex-math>$3 times 3$</tex-math></inline-formula> and <inline-formula><tex-math>$6 times 6$</tex-math></inline-formula> ternary multipliers. The proposed approximate <inline-formula><tex-math>$6 times 6$</tex-math></inline-formula> multiplier saves energy in the range of 22% to 40% over recent approximate designs. Further, there is a reduction of delay of roughly 21<inline-formula><tex-math>$%$</tex-math></inline-formula> with the proposed multipliers over the best existing design. The multipliers are based on their <italic>exact</i> counterparts which are, in turn, developed using an efficient exact <italic>ternary carry adder (TCAD)</i> that generates the sum of two carry outputs of a single ternary digit multiplier. The application of the approximate multipliers to CNN-based imaging is then demonstrated. In particular, the proposed approximate multipliers have excellent performance for CNN-based image denoising. Further, the approximate multipliers show good performance on MNIST and CIFAR-10 datasets. Simulations for Carbon Nanotube FET (CNTFET) reveal energy savings in excess of 50% over the best existing multipliers.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"1-12"},"PeriodicalIF":2.1,"publicationDate":"2025-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/TSTE.2025.3640786
{"title":"IEEE Transactions on Sustainable Energy Information for Authors","authors":"","doi":"10.1109/TSTE.2025.3640786","DOIUrl":"https://doi.org/10.1109/TSTE.2025.3640786","url":null,"abstract":"","PeriodicalId":452,"journal":{"name":"IEEE Transactions on Sustainable Energy","volume":"17 1","pages":"C4-C4"},"PeriodicalIF":10.0,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313738","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, the widespread adoption of drones, while offering convenience, has also led to significant security challenges such as illegal intrusions and privacy violations, creating an urgent need for reliable identification and classification systems. A primary obstacle to achieving this reliability is the high similarity of radio frequency (RF) signals among different drone models, which often leads to misclassification. In this study, we propose the DS-UAVNet, a network that employs a dual-branch architecture to independently process complementary information from the time and frequency domains, thereby preventing information loss. Within this network, a designed parallel convolution module efficiently extracts multiscale features while reducing model complexity. To address the inherent vulnerabilities of the single-modality drone identification system, we further design M-DS-UAVNet, a multimodal framework that enhances identification robustness by leveraging a transfer learning strategy to fuse audio and RF features. Evaluations show that DS-UAVNet achieves accuracies of 98.74% and 98.56% on the public DroneRF dataset for drone classification and operation mode recognition, respectively, outperforming existing methods. Moreover, the M-DS-UAVNet framework achieves 100.00% and 99.78% accuracy on the constructed multimodal dataset, validating the effectiveness of the multimodal fusion strategy for building identification systems.
{"title":"An Efficient Dual-Branch Network and Multimodal Fusion Framework for Drone Identification","authors":"Borong Fu;Yan Zhang;Jiaming Wu;Feiyang Ye;Wancheng Zhang","doi":"10.1109/JSEN.2025.3645409","DOIUrl":"https://doi.org/10.1109/JSEN.2025.3645409","url":null,"abstract":"In recent years, the widespread adoption of drones, while offering convenience, has also led to significant security challenges such as illegal intrusions and privacy violations, creating an urgent need for reliable identification and classification systems. A primary obstacle to achieving this reliability is the high similarity of radio frequency (RF) signals among different drone models, which often leads to misclassification. In this study, we propose the DS-UAVNet, a network that employs a dual-branch architecture to independently process complementary information from the time and frequency domains, thereby preventing information loss. Within this network, a designed parallel convolution module efficiently extracts multiscale features while reducing model complexity. To address the inherent vulnerabilities of the single-modality drone identification system, we further design M-DS-UAVNet, a multimodal framework that enhances identification robustness by leveraging a transfer learning strategy to fuse audio and RF features. Evaluations show that DS-UAVNet achieves accuracies of 98.74% and 98.56% on the public DroneRF dataset for drone classification and operation mode recognition, respectively, outperforming existing methods. Moreover, the M-DS-UAVNet framework achieves 100.00% and 99.78% accuracy on the constructed multimodal dataset, validating the effectiveness of the multimodal fusion strategy for building identification systems.","PeriodicalId":447,"journal":{"name":"IEEE Sensors Journal","volume":"26 3","pages":"5241-5253"},"PeriodicalIF":4.3,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"综合性期刊","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/TSTE.2025.3640784
{"title":"IEEE Industry Applications Society Information","authors":"","doi":"10.1109/TSTE.2025.3640784","DOIUrl":"https://doi.org/10.1109/TSTE.2025.3640784","url":null,"abstract":"","PeriodicalId":452,"journal":{"name":"IEEE Transactions on Sustainable Energy","volume":"17 1","pages":"C3-C3"},"PeriodicalIF":10.0,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313739","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-Electro-Mechanical System (MEMS) devices show better performance as compared to solid-state devices in terms of radio frequency (RF) response, like insertion loss and isolation. However, MEMS devices face reliability issues, and stress is one of the main concerns. MEMS devices involve many non-traditional fabrication steps, like releasing hanging structures. Released MEMS structures show built-in stress from the fabrication process. This stress can cause them to bend, curl, or buckle. Especially in the case of Radio Frequency (RF) MEMS switches, curling buckling increases the pull-in voltage. In the literature, to address stress-related buckling, thermal annealing was applied at different temperatures after release. However, post-release annealing reduces the stress and results in curled-up and unstable structures. The present paper explores a novel and innovative method for thermally annealing structures at an appropriate stage to reduce stress and buckling in released cantilever structures. Annealing at the appropriate step results in a significant reduction in cantilever bending and warping, indicating effective stress relaxation and yielding straight, mechanically stable cantilevers. After controlling the stress and buckling, the pull-in voltage is reduced to 40 V, which is in close agreement with the simulated results. The measured insertion loss of the switch is –0.4 dB, and isolation is –22 dB for the DC to 20 GHz frequency range.
{"title":"Buckling and Stress-Controlled RF MEMS Structures Using Annealing","authors":"Khushbu Singh Raghav;Amit Kumar;Prashant Sharma;Prateek Kothari;Mahesh Angira;Deepak Bansal","doi":"10.1109/TSM.2025.3646670","DOIUrl":"https://doi.org/10.1109/TSM.2025.3646670","url":null,"abstract":"Micro-Electro-Mechanical System (MEMS) devices show better performance as compared to solid-state devices in terms of radio frequency (RF) response, like insertion loss and isolation. However, MEMS devices face reliability issues, and stress is one of the main concerns. MEMS devices involve many non-traditional fabrication steps, like releasing hanging structures. Released MEMS structures show built-in stress from the fabrication process. This stress can cause them to bend, curl, or buckle. Especially in the case of Radio Frequency (RF) MEMS switches, curling buckling increases the pull-in voltage. In the literature, to address stress-related buckling, thermal annealing was applied at different temperatures after release. However, post-release annealing reduces the stress and results in curled-up and unstable structures. The present paper explores a novel and innovative method for thermally annealing structures at an appropriate stage to reduce stress and buckling in released cantilever structures. Annealing at the appropriate step results in a significant reduction in cantilever bending and warping, indicating effective stress relaxation and yielding straight, mechanically stable cantilevers. After controlling the stress and buckling, the pull-in voltage is reduced to 40 V, which is in close agreement with the simulated results. The measured insertion loss of the switch is –0.4 dB, and isolation is –22 dB for the DC to 20 GHz frequency range.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"28-35"},"PeriodicalIF":2.3,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Graphene has long been considered a revolutionary material for the field of electronics due to its remarkable set of electronic properties, standing as a very promising candidate for the post-silicon era. However, it is not just a silicon replacement, but rather an enabling material for different computing paradigms. In this work, we investigate the use of graphene in devices and circuits that are employed for the realisation of computing architectures and systems. More specifically, we focus on impactful key applications such as conventional computing and Boolean logic, high-radix computing and multi-valued logic, memristive devices and in-memory-computing, neuromorphic applications, quantum computing and photonics. Additionally, taking into consideration the state-of-the-art as well as the existing graphene-related challenges that are still present, this work attempts to assess the possible future development of graphene-based devices, circuits and systems in each of the aforementioned fields and to propose a coarse yet directive roadmap for the material’s future in computing architectures.
{"title":"Graphene for Computing: Devices to Architectures","authors":"Konstantinos Rallis;Georgios Kleitsiotis;Athanasios Passias;Evangelos Tsipas;Theodoros Panagiotis Chatzinikolaou;Karolos Tsakalos;Antonio Rubio;Sorin Cotofana;Ioannis Karafyllidis;Panagiotis Dimitrakis;Georgios Ch. Sirakoulis","doi":"10.1109/OJNANO.2025.3646972","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3646972","url":null,"abstract":"Graphene has long been considered a revolutionary material for the field of electronics due to its remarkable set of electronic properties, standing as a very promising candidate for the post-silicon era. However, it is not just a silicon replacement, but rather an enabling material for different computing paradigms. In this work, we investigate the use of graphene in devices and circuits that are employed for the realisation of computing architectures and systems. More specifically, we focus on impactful key applications such as conventional computing and Boolean logic, high-radix computing and multi-valued logic, memristive devices and in-memory-computing, neuromorphic applications, quantum computing and photonics. Additionally, taking into consideration the state-of-the-art as well as the existing graphene-related challenges that are still present, this work attempts to assess the possible future development of graphene-based devices, circuits and systems in each of the aforementioned fields and to propose a coarse yet directive roadmap for the material’s future in computing architectures.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"7 ","pages":"1-17"},"PeriodicalIF":1.9,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11309749","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146049292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/JPHOTOV.2025.3642585
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on “Ultrawide Band Gap Semiconductor Device for RF, Power and Optoelectronic Applications”","authors":"","doi":"10.1109/JPHOTOV.2025.3642585","DOIUrl":"https://doi.org/10.1109/JPHOTOV.2025.3642585","url":null,"abstract":"","PeriodicalId":445,"journal":{"name":"IEEE Journal of Photovoltaics","volume":"16 1","pages":"187-188"},"PeriodicalIF":2.6,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11311579","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145802325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/JPHOTOV.2025.3642495
{"title":"IEEE Journal of Photovoltaics Information for Authors","authors":"","doi":"10.1109/JPHOTOV.2025.3642495","DOIUrl":"https://doi.org/10.1109/JPHOTOV.2025.3642495","url":null,"abstract":"","PeriodicalId":445,"journal":{"name":"IEEE Journal of Photovoltaics","volume":"16 1","pages":"C3-C3"},"PeriodicalIF":2.6,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11311604","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145802350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/TSM.2025.3646674
Jae Hwan Shin;Hyunbeen Kim;Jin Hwan Park;Young-Woo Lee
As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture’s operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS’89 and OpenCores benchmarks compared to prior work.
{"title":"Scalable Multi-Site Test Architecture for Chiplet-Based Systems on ATE Platforms","authors":"Jae Hwan Shin;Hyunbeen Kim;Jin Hwan Park;Young-Woo Lee","doi":"10.1109/TSM.2025.3646674","DOIUrl":"https://doi.org/10.1109/TSM.2025.3646674","url":null,"abstract":"As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture’s operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS’89 and OpenCores benchmarks compared to prior work.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"139-147"},"PeriodicalIF":2.3,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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