Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3206393
Mhd Saria Allahham;Amr Mohamed;Aiman Erbad;Mohsen Guizani
Mobile edge learning (MEL) is a learning paradigm that enables distributed training of machine learning (ML) models over heterogeneous edge devices (e.g., IoT devices). Multiorchestrator MEL refers to the coexistence of multiple learning tasks with different datasets, each of which being governed by an orchestrator to facilitate the distributed training process. In MEL, the training performance deteriorates without the availability of sufficient training data or computing resources. Therefore, it is crucial to motivate edge devices to become learners and offer their computing resources, and either offer their private data or receive the needed data from the orchestrator and participate in the training process of a learning task. In this work, we propose an incentive mechanism, where we formulate the orchestrators-learners’ interactions as a 2-round Stackelberg game to motivate the participation of the learners. In the first round, the learners decide which learning task to get engaged in, and then in the second round, the training parameters and the amount of data for training in case of participation such that their utility is maximized. We then study the training round analytically and derive the learners’ optimal strategy. Finally, numerical experiments have been conducted to evaluate the performance of the proposed incentive mechanism.
{"title":"Motivating Learners in Multiorchestrator Mobile Edge Learning: A Stackelberg Game Approach","authors":"Mhd Saria Allahham;Amr Mohamed;Aiman Erbad;Mohsen Guizani","doi":"10.1109/ICJECE.2022.3206393","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3206393","url":null,"abstract":"Mobile edge learning (MEL) is a learning paradigm that enables distributed training of machine learning (ML) models over heterogeneous edge devices (e.g., IoT devices). Multiorchestrator MEL refers to the coexistence of multiple learning tasks with different datasets, each of which being governed by an orchestrator to facilitate the distributed training process. In MEL, the training performance deteriorates without the availability of sufficient training data or computing resources. Therefore, it is crucial to motivate edge devices to become learners and offer their computing resources, and either offer their private data or receive the needed data from the orchestrator and participate in the training process of a learning task. In this work, we propose an incentive mechanism, where we formulate the orchestrators-learners’ interactions as a 2-round Stackelberg game to motivate the participation of the learners. In the first round, the learners decide which learning task to get engaged in, and then in the second round, the training parameters and the amount of data for training in case of participation such that their utility is maximized. We then study the training round analytically and derive the learners’ optimal strategy. Finally, numerical experiments have been conducted to evaluate the performance of the proposed incentive mechanism.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"46 1","pages":"69-76"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68038580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3199563
Christopher DeSantis;Ahmed Refaey Hussein
Speech classification acceleration using field-programmable gate arrays (FPGAs) is a well-studied field and enables the potential to gain both speed and better energy efficiency over other processor-intensive classifiers. System-on-chip (SoC) architecture allows for an integrated system between programmable logic and processor and for increased bandwidth communications to on- chip peripherals and memory. This article serves as an investigation of the utility of an edge-based support-vector machine (SVM) implemented onto a Zynq-XC7Z020 multiprocessor system on a chip (MPSoC) for the acceleration of three speech class pairs. The system allows for a parallelized structure, which yielded a faster classifier model. The results were found to be an acceleration factor of $2.08times $ . This appears to have come at the cost of a decrease in prediction accuracy, lowering from 92.5% to 83.5% positive prediction percentage likely due to decreased data resolution. The resolution used in this model was a 16-bit fixed-point format for the hardware interpretation and a floating-point format for the software benchmark. The resource usage of the FPGA was also analyzed for both overlays and can yield a 21% reduction in CPU usage. Résumé—L’accélération de la classification de la parole à l’aide de réseaux de portes programmables par l’utilisateur (FPGAs) est un domaine bien étudié et offre la possibilité de gagner à la fois en vitesse et en efficacité énergétique par rapport à d’autres classificateurs nécessitant un processeur. L’architecture système sur une puce (SoC) permet un système intégré entre la logique programmable et le processeur et une augmentation de la bande passante des communications vers les périphériques sur la puce et la mémoire. Cet article est une étude de l’utilité d’une machine à vecteur de support (SVM) basée sur les périphéries et mise en œuvre sur un système multiprocesseur Zynq-XC7Z020 sur une puce (MPSoC) pour l’accélération de trois paires de classes vocales. Le système permet une structure parallélisée, ce qui permet d’obtenir un modèle de classification plus rapide. Les résultats se sont révélés être un facteur d’accélération de 2, $08times $ . Cela semble s’être fait au prix d’une diminution de la précision de prédiction, passant de 92,5 % à 83,5 % de pourcentage de prédiction positive, probablement en raison de la diminution de la résolution des données. La résolution utilisée dans ce modèle était un format à virgule fixe de 16 bits pour l’interprétation matérielle et un format à virgule flottante pour le benchmark logiciel. L’utilisation des ressources du FPGA a également été analysée pour les deux superpositions et permet de réduire de 21 % l’utilisation du CPU.
{"title":"AI SoC-Based Accelerator for Speech Classification Accélérateur de classification de la parole basé sur un AI SoC","authors":"Christopher DeSantis;Ahmed Refaey Hussein","doi":"10.1109/ICJECE.2022.3199563","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3199563","url":null,"abstract":"Speech classification acceleration using field-programmable gate arrays (FPGAs) is a well-studied field and enables the potential to gain both speed and better energy efficiency over other processor-intensive classifiers. System-on-chip (SoC) architecture allows for an integrated system between programmable logic and processor and for increased bandwidth communications to on- chip peripherals and memory. This article serves as an investigation of the utility of an edge-based support-vector machine (SVM) implemented onto a Zynq-XC7Z020 multiprocessor system on a chip (MPSoC) for the acceleration of three speech class pairs. The system allows for a parallelized structure, which yielded a faster classifier model. The results were found to be an acceleration factor of \u0000<inline-formula> <tex-math>$2.08times $ </tex-math></inline-formula>\u0000. This appears to have come at the cost of a decrease in prediction accuracy, lowering from 92.5% to 83.5% positive prediction percentage likely due to decreased data resolution. The resolution used in this model was a 16-bit fixed-point format for the hardware interpretation and a floating-point format for the software benchmark. The resource usage of the FPGA was also analyzed for both overlays and can yield a 21% reduction in CPU usage. Résumé—L’accélération de la classification de la parole à l’aide de réseaux de portes programmables par l’utilisateur (FPGAs) est un domaine bien étudié et offre la possibilité de gagner à la fois en vitesse et en efficacité énergétique par rapport à d’autres classificateurs nécessitant un processeur. L’architecture système sur une puce (SoC) permet un système intégré entre la logique programmable et le processeur et une augmentation de la bande passante des communications vers les périphériques sur la puce et la mémoire. Cet article est une étude de l’utilité d’une machine à vecteur de support (SVM) basée sur les périphéries et mise en œuvre sur un système multiprocesseur Zynq-XC7Z020 sur une puce (MPSoC) pour l’accélération de trois paires de classes vocales. Le système permet une structure parallélisée, ce qui permet d’obtenir un modèle de classification plus rapide. Les résultats se sont révélés être un facteur d’accélération de 2,\u0000<inline-formula> <tex-math>$08times $ </tex-math></inline-formula>\u0000. Cela semble s’être fait au prix d’une diminution de la précision de prédiction, passant de 92,5 % à 83,5 % de pourcentage de prédiction positive, probablement en raison de la diminution de la résolution des données. La résolution utilisée dans ce modèle était un format à virgule fixe de 16 bits pour l’interprétation matérielle et un format à virgule flottante pour le benchmark logiciel. L’utilisation des ressources du FPGA a également été analysée pour les deux superpositions et permet de réduire de 21 % l’utilisation du CPU.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"222-231"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3200075
Riadul Islam
At leading technology nodes, the industry is facing a stiff challenge to make profitable integrated circuits (ICs). One of the primary issues is the design rule checking (DRC) violation. This research cohort with the DARPA IDEA program aims for “no-human-in-the-loop” and 24-h turnaround time to implement an IC from design specifications. In order to reduce human effort, this work introduces the ensemble random forest, gradient boosting, and Adaboost algorithms to predict DRC violations before detailed routing, which is considered the most time-consuming step in an IC design flow. In addition, this work identifies the features that critically impact DRC violations. The proposed algorithm has a 2% better F1-score compared to the existing support-vector machine (SVM) classifiers. The proposed ensemble approach has up to an area-under-the-curve–receiver operating characteristics (AUC–ROC) curve mean of 0.940 with ± 0.011 standard deviation compared to the state-of-the-art SVM classifier with an AUC–ROC curve mean of 0.854 with ± 0.01 standard deviation. The proposed ensemble approach exhibits up to 28.7% better DRC violation prediction rate compared to those using SVM algorithms on the test data. In addition, the proposed gradient boosting algorithm requires $37.5times $ lower average training time and $50times $ lower average testing time compared to the existing SVM methodologies.
{"title":"Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms","authors":"Riadul Islam","doi":"10.1109/ICJECE.2022.3200075","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3200075","url":null,"abstract":"At leading technology nodes, the industry is facing a stiff challenge to make profitable integrated circuits (ICs). One of the primary issues is the design rule checking (DRC) violation. This research cohort with the DARPA IDEA program aims for “no-human-in-the-loop” and 24-h turnaround time to implement an IC from design specifications. In order to reduce human effort, this work introduces the ensemble random forest, gradient boosting, and Adaboost algorithms to predict DRC violations before detailed routing, which is considered the most time-consuming step in an IC design flow. In addition, this work identifies the features that critically impact DRC violations. The proposed algorithm has a 2% better F1-score compared to the existing support-vector machine (SVM) classifiers. The proposed ensemble approach has up to an area-under-the-curve–receiver operating characteristics (AUC–ROC) curve mean of 0.940 with ± 0.011 standard deviation compared to the state-of-the-art SVM classifier with an AUC–ROC curve mean of 0.854 with ± 0.01 standard deviation. The proposed ensemble approach exhibits up to 28.7% better DRC violation prediction rate compared to those using SVM algorithms on the test data. In addition, the proposed gradient boosting algorithm requires \u0000<inline-formula> <tex-math>$37.5times $ </tex-math></inline-formula>\u0000 lower average training time and \u0000<inline-formula> <tex-math>$50times $ </tex-math></inline-formula>\u0000 lower average testing time compared to the existing SVM methodologies.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 4","pages":"354-364"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68030715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/ICJECE.2022.3178749
Bruno Moraes Rocha;Gabriel S. Vieira;Afonso U. Fonseca;Naiane M. Sousa;Helio Pedrini;Fabrizzio Soares
Sugarcane is one of the main crops in the world due to its economic value promoted by the sale of its derivatives, such as bioethanol and sugar. In order to achieve greater economic performance and productivity in the sugarcane field, several digital image processing studies have been conducted on sugarcane field images. However, mapping and measuring gaps in the planting rows are still being performed manually on-site to determine whether to replant the entire area or only the gaps. High cost of time and manpower is required to perform the manual measurement. Based on that, the aim of this study is to present a novel method to detect crop rows and measure gaps in crop fields. Our method is also able to deal with curved crop rows, which is a real problem and substantially limits numerous solutions in practical applications. The proposed method is evaluated using a mosaic of real scene image that was prepared with the support of a small remotely piloted aircraft. Experimental tests showed a low relative error of approximately 1.65% compared to manual mapping in the planting regions, even for regions with gaps in the curved crop rows. It means that our proposal can identify and measure crop rows accurately, which enables automated inspections with high-precision measurements.
{"title":"Detection of Curved Rows and Gaps in Aerial Images of Sugarcane Field Using Image Processing Techniques","authors":"Bruno Moraes Rocha;Gabriel S. Vieira;Afonso U. Fonseca;Naiane M. Sousa;Helio Pedrini;Fabrizzio Soares","doi":"10.1109/ICJECE.2022.3178749","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3178749","url":null,"abstract":"Sugarcane is one of the main crops in the world due to its economic value promoted by the sale of its derivatives, such as bioethanol and sugar. In order to achieve greater economic performance and productivity in the sugarcane field, several digital image processing studies have been conducted on sugarcane field images. However, mapping and measuring gaps in the planting rows are still being performed manually on-site to determine whether to replant the entire area or only the gaps. High cost of time and manpower is required to perform the manual measurement. Based on that, the aim of this study is to present a novel method to detect crop rows and measure gaps in crop fields. Our method is also able to deal with curved crop rows, which is a real problem and substantially limits numerous solutions in practical applications. The proposed method is evaluated using a mosaic of real scene image that was prepared with the support of a small remotely piloted aircraft. Experimental tests showed a low relative error of approximately 1.65% compared to manual mapping in the planting regions, even for regions with gaps in the curved crop rows. It means that our proposal can identify and measure crop rows accurately, which enables automated inspections with high-precision measurements.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"303-310"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-09DOI: 10.1109/ICJECE.2022.3192312
Ali Mastanabadi;Gholamreza Aghajani;Davar Mirabbasi
Nowadays, with the increasing expansion of the power grid and the use of wind energy systems, the issue of frequency control of the power system in their presence is very important. In traditional power systems, the control of frequency is generally performed by hydroelectric power plants that are the slack bus of the grid. They usually have fast dynamic responses, capable of changing the power output rapidly. This can be difficult in cases such as drought, lack of large hydropower plants, or the expansion of the power grid. In this article, a new topology and control system for a wind farm connected to a four-area grid through an high voltage dc (HVdc) link is presented, which can participate in the issue of frequency control of the power system. The proposed system is based on maximum power point tracking (MPPT) and fine tune control of the permanent magnet synchronous generator (PMSG)-based wind farm. The simulation results were evaluated on a four-area power grid, they were compared with the absence of wind farm in frequency control, and the desired results with appropriate and acceptable dynamic responses were achieved. The simulation results were performed on the MATLAB/Simulink environment.
{"title":"Wind Farm Fast Response Contribution in Power Frequency Control, Using a New Configuration and Control System Based on MPPT and Fine Tune Power Algorithm","authors":"Ali Mastanabadi;Gholamreza Aghajani;Davar Mirabbasi","doi":"10.1109/ICJECE.2022.3192312","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3192312","url":null,"abstract":"Nowadays, with the increasing expansion of the power grid and the use of wind energy systems, the issue of frequency control of the power system in their presence is very important. In traditional power systems, the control of frequency is generally performed by hydroelectric power plants that are the slack bus of the grid. They usually have fast dynamic responses, capable of changing the power output rapidly. This can be difficult in cases such as drought, lack of large hydropower plants, or the expansion of the power grid. In this article, a new topology and control system for a wind farm connected to a four-area grid through an high voltage dc (HVdc) link is presented, which can participate in the issue of frequency control of the power system. The proposed system is based on maximum power point tracking (MPPT) and fine tune control of the permanent magnet synchronous generator (PMSG)-based wind farm. The simulation results were evaluated on a four-area power grid, they were compared with the absence of wind farm in frequency control, and the desired results with appropriate and acceptable dynamic responses were achieved. The simulation results were performed on the MATLAB/Simulink environment.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"339-348"},"PeriodicalIF":0.0,"publicationDate":"2022-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-08DOI: 10.1109/ICJECE.2022.3187348
Sharief Saleh;Amr S. El-Wakeel;Aboelmagd Noureldin
The novel signaling and architectural features of 5G promise a major role in providing accurate, precise, and continuous positioning where satellite-based positioning systems may fail. In the case of time-based trilateration, optimal estimators like extended Kalman filter (EKF) can be used to estimate the position with the aid of time-of-arrival (TOA) and round-trip-time (RTT) measurements. However, the linearization of the measurement model used by EKF may lead to positioning errors. Such errors are further magnified due to the narrow geometrical placement of road-side 5G micro base stations (BSs) and due to the closeness of the vehicle to these BSs, leading to significant positioning errors. In this article, the impact of the 5G geometrical setup on the traditional EKF positioning estimation is analyzed. In addition, we propose a dynamically tuned covariance matrix (DTCM) EKF that is automatically tuned based on the measured ranges to trust less the BSs that would lead to high positioning errors. The performance of the proposed method was tested in Siradel’s S_5GChannel simulator that mimics the urban canyons of downtown Toronto. The proposed DTCM-EKF has sustained reliable positioning with sub-meter-level accuracy 90% of the time. The DTCM-EKF has reduced the rms and maximum position error of the EKF by approximately 60% and 67%, respectively.
{"title":"5G-Enabled Vehicle Positioning Using EKF With Dynamic Covariance Matrix Tuning","authors":"Sharief Saleh;Amr S. El-Wakeel;Aboelmagd Noureldin","doi":"10.1109/ICJECE.2022.3187348","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3187348","url":null,"abstract":"The novel signaling and architectural features of 5G promise a major role in providing accurate, precise, and continuous positioning where satellite-based positioning systems may fail. In the case of time-based trilateration, optimal estimators like extended Kalman filter (EKF) can be used to estimate the position with the aid of time-of-arrival (TOA) and round-trip-time (RTT) measurements. However, the linearization of the measurement model used by EKF may lead to positioning errors. Such errors are further magnified due to the narrow geometrical placement of road-side 5G micro base stations (BSs) and due to the closeness of the vehicle to these BSs, leading to significant positioning errors. In this article, the impact of the 5G geometrical setup on the traditional EKF positioning estimation is analyzed. In addition, we propose a dynamically tuned covariance matrix (DTCM) EKF that is automatically tuned based on the measured ranges to trust less the BSs that would lead to high positioning errors. The performance of the proposed method was tested in Siradel’s S_5GChannel simulator that mimics the urban canyons of downtown Toronto. The proposed DTCM-EKF has sustained reliable positioning with sub-meter-level accuracy 90% of the time. The DTCM-EKF has reduced the rms and maximum position error of the EKF by approximately 60% and 67%, respectively.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"192-198"},"PeriodicalIF":0.0,"publicationDate":"2022-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-07DOI: 10.1109/ICJECE.2022.3192320
Ugljesa Urosevic
In this article, a novel multiplex-multicast approach for virtual reality (VR) applications is proposed. High data rate and low latency are some of the key requirements for these services. Thus, new spatial multiplexing, for increasing overall spectral efficiency, is performed between one gateway (GW) and predefined VR relaying devices (VR-RDs) that act as relays toward other VR devices (VR-D) in a certain cluster. At the first hop, the novel, full-rate, quasi-orthogonal space–time line code (QOSTLC) multiplexing is implemented, while, at the second hop, the multicast channels are performed through a well-known full-rate QOST block code (QOSTBC). Furthermore, in order to facilitate utilization of this dual-hop, downlink, transmission scheme for VR services, it was necessary to deploy low-complexity processing at VR-RDs. Decoding and full-channel state information (CSI) obtaining can affect the processing delay, thus, there is no decoding at VR-RDs, and they do not need full CSI, either for receiving or transmitting. Besides achieving these features, the novel processing at VR-RDs emulates full-orthogonality within the new multiplexing scheme. VR-RDs are equipped with four antennas, while the number of transmitting and receiving antennas at the GW and VR-Ds can be arbitrary. The simulated bit error rate (BER) results are presented for the different simulation parameters.
{"title":"A Multiplex-Multicast Approach for VR Applications","authors":"Ugljesa Urosevic","doi":"10.1109/ICJECE.2022.3192320","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3192320","url":null,"abstract":"In this article, a novel multiplex-multicast approach for virtual reality (VR) applications is proposed. High data rate and low latency are some of the key requirements for these services. Thus, new spatial multiplexing, for increasing overall spectral efficiency, is performed between one gateway (GW) and predefined VR relaying devices (VR-RDs) that act as relays toward other VR devices (VR-D) in a certain cluster. At the first hop, the novel, full-rate, quasi-orthogonal space–time line code (QOSTLC) multiplexing is implemented, while, at the second hop, the multicast channels are performed through a well-known full-rate QOST block code (QOSTBC). Furthermore, in order to facilitate utilization of this dual-hop, downlink, transmission scheme for VR services, it was necessary to deploy low-complexity processing at VR-RDs. Decoding and full-channel state information (CSI) obtaining can affect the processing delay, thus, there is no decoding at VR-RDs, and they do not need full CSI, either for receiving or transmitting. Besides achieving these features, the novel processing at VR-RDs emulates full-orthogonality within the new multiplexing scheme. VR-RDs are equipped with four antennas, while the number of transmitting and receiving antennas at the GW and VR-Ds can be arbitrary. The simulated bit error rate (BER) results are presented for the different simulation parameters.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"349-353"},"PeriodicalIF":0.0,"publicationDate":"2022-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-07DOI: 10.1109/ICJECE.2022.3189687
Abarna Rajkumar;Sivasankar Gangatharan
One of the major perceptions of distribution system is frequent power conversion. Conversion losses and the generation of harmonics by the converter have been kneeling day by day and polluting the power network. In this article, an effective energy management scheme has been proposed in the microgrid (MG) framework to promote diminishing energy usage by considering both energy storage and renewable energy sources integration. Integration of renewable energy systems along with battery energy storage systems encourages in promoting energy and also minimizes the cost. The objective of this work is to construct a flexible ac/dc MG to feed ac and dc loads separately in order to reduce multiple conversion losses and to design a hybrid bidirectional converter to manage power sharing between ac and dc grids effectively. Energy-saving possibility of 30.87% is expected by incorporating the MG scheme compared to the conventional scheme and power loss can be reduced by 59.8% compared to the conventional direct grid-tie solar photovoltaic (PV) scheme. Conversion losses happen only during unavoidable circumstances. Energy conversion is managed through an automatic centralized MG controller and the loads are scheduled accordingly, and thereby, utilizing the renewable energy is effectively utilized and the demand optimization is scheduled.
{"title":"A Novel Solar PV Equipped Flexible AC/DC Microgrid Based Energy Management for Effective Residential Power Distribution","authors":"Abarna Rajkumar;Sivasankar Gangatharan","doi":"10.1109/ICJECE.2022.3189687","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3189687","url":null,"abstract":"One of the major perceptions of distribution system is frequent power conversion. Conversion losses and the generation of harmonics by the converter have been kneeling day by day and polluting the power network. In this article, an effective energy management scheme has been proposed in the microgrid (MG) framework to promote diminishing energy usage by considering both energy storage and renewable energy sources integration. Integration of renewable energy systems along with battery energy storage systems encourages in promoting energy and also minimizes the cost. The objective of this work is to construct a flexible ac/dc MG to feed ac and dc loads separately in order to reduce multiple conversion losses and to design a hybrid bidirectional converter to manage power sharing between ac and dc grids effectively. Energy-saving possibility of 30.87% is expected by incorporating the MG scheme compared to the conventional scheme and power loss can be reduced by 59.8% compared to the conventional direct grid-tie solar photovoltaic (PV) scheme. Conversion losses happen only during unavoidable circumstances. Energy conversion is managed through an automatic centralized MG controller and the loads are scheduled accordingly, and thereby, utilizing the renewable energy is effectively utilized and the demand optimization is scheduled.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"328-338"},"PeriodicalIF":0.0,"publicationDate":"2022-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-07DOI: 10.1109/ICJECE.2022.3189043
Moona Yakhchi;Mahdi Fazeli;Seyyed Amir Asghari
Silent data corruptions (SDCs) have been always regarded as the serious effect of radiation-induced faults. Traditional solutions based on redundancies are very expensive in terms of chip area, energy consumption, and performance. Consequently, providing low-cost and efficient approaches to cope with SDCs has received researchers’ attention more than ever. On the other hand, identifying SDC-prone data and instruction in a program is a very challenging issue, as it requires time-consuming fault injection processes into different parts of a program. In this article, we present a cost-efficient approach to detecting and mitigating the rate of SDCs in the whole program with the presence of multibit faults without a fault injection process. This approach uses a combination of machine learning and a metaheuristic algorithm that predicts the SDC event rate of each instruction. The evaluation results show that the proposed approach provides a high level of detection accuracy of 99% while offering a low-performance overhead of 58%.
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Pub Date : 2022-09-01DOI: 10.1109/ICJECE.2022.3233731
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本期出版物的编辑委员会、董事会、现任工作人员、委员会成员和/或协会编辑。
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