Pub Date : 2025-12-15DOI: 10.1109/OJSSCS.2025.3644337
Ratul Das;Hanh-Phuc Le
This work presents a shared-switched-capacitor multioutput hybrid (SSC-MoH) converter to support large conversion ratios from a 12–24 V input to three separate outputs of 0.8–1.8 V. The 6-switch converter includes a 3X-step-down switched capacitor (SC) front-end that is fully soft-charged and shared by three output inductors. The output voltages are individually regulated using PWM signals from a power-collaborative control (PCC). The chip was manufactured in a 130-nm high-voltage BCD process, achieving a peak efficiency of 87.14%, 30X conversion ratio, and 11.93-W peak output power in system evaluation.
{"title":"Shared Switched Capacitor Multioutput Hybrid Converter for High Conversion Ratio Applications","authors":"Ratul Das;Hanh-Phuc Le","doi":"10.1109/OJSSCS.2025.3644337","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3644337","url":null,"abstract":"This work presents a shared-switched-capacitor multioutput hybrid (SSC-MoH) converter to support large conversion ratios from a 12–24 V input to three separate outputs of 0.8–1.8 V. The 6-switch converter includes a 3X-step-down switched capacitor (SC) front-end that is fully soft-charged and shared by three output inductors. The output voltages are individually regulated using PWM signals from a power-collaborative control (PCC). The chip was manufactured in a 130-nm high-voltage BCD process, achieving a peak efficiency of 87.14%, 30X conversion ratio, and 11.93-W peak output power in system evaluation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"3-14"},"PeriodicalIF":3.2,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11300850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/OJSSCS.2025.3644839
Donghyun Youn;Daehyeon Kwon;Minkyu Je
Wireless capsule endoscopy requires simultaneous support of ultralow-power operation and high data rate to enable long diagnostic time and reliable image transmission. To support both design requirements, this work presents a 75-pJ/bit 435-MHz modulator for 16 quadrature amplitude modulation (16-QAM) with aggressive symbol-level duty cycling (SLDC). An SLDC is supported by a fast startup technique, which enhances duty cycling efficiency. During startup, the proposed technique minimizes transient DC error components at the modulator input, which results in fast settling of the output envelope. A fully on-chip auto calibration detects and corrects this error without impacting modulator performance. The calibration is fully digital, scalable, and robust against process, voltage, and temperature variations. After the calibration process, the modulator exhibits a 20-ns startup time. Even with 50% SLDC, a data rate of 20 Mb/s is achieved with −8-dBm average output power and 1.6-mW power consumption. Combining spectrum-efficient QAM and SLDC, this work satisfies both low-power and high-data-rate requirements for wireless medical capsule endoscopy (WMCE).
{"title":"A 75-pJ/bit 435-MHz 16-QAM Modulator With 20-ns Startup Time and Symbol-Level Duty Cycling for Capsule Endoscopy","authors":"Donghyun Youn;Daehyeon Kwon;Minkyu Je","doi":"10.1109/OJSSCS.2025.3644839","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3644839","url":null,"abstract":"Wireless capsule endoscopy requires simultaneous support of ultralow-power operation and high data rate to enable long diagnostic time and reliable image transmission. To support both design requirements, this work presents a 75-pJ/bit 435-MHz modulator for 16 quadrature amplitude modulation (16-QAM) with aggressive symbol-level duty cycling (SLDC). An SLDC is supported by a fast startup technique, which enhances duty cycling efficiency. During startup, the proposed technique minimizes transient DC error components at the modulator input, which results in fast settling of the output envelope. A fully on-chip auto calibration detects and corrects this error without impacting modulator performance. The calibration is fully digital, scalable, and robust against process, voltage, and temperature variations. After the calibration process, the modulator exhibits a 20-ns startup time. Even with 50% SLDC, a data rate of 20 Mb/s is achieved with −8-dBm average output power and 1.6-mW power consumption. Combining spectrum-efficient QAM and SLDC, this work satisfies both low-power and high-data-rate requirements for wireless medical capsule endoscopy (WMCE).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"354-364"},"PeriodicalIF":3.2,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11300849","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-10DOI: 10.1109/OJSSCS.2025.3642795
Gourab Barik;Samyadip Sarkar;Baibhab Chatterjee;Gaurav K. Kumar;Shreyas Sen
With the rapid advancement of the Internet of Things (IoT) and its expanding applications in health monitoring, body-worn cameras, and smart glasses, the demand for high data rate (DR) video transmission and compact device size has become critical. This shift has necessitated the development of low-power communication systems and battery-efficient or battery-less designs. Traditional high-data-rate communication methods consume mWs of power, such as Wi-Fi and backscatter communication (for high DRs, higher transmitter power is required to handle the two-fold path loss between the transmitter and sensor node), and require converting analog information into digital bits before transmission. These approaches rely on analog-to-digital converters (ADCs), which generate substantial data volumes, resulting in increased storage and processing demands while consuming significant power $P_{text {ADC}} propto 2^{N};(text {exponential}) $ , where $N$ is the number of bits. Consequently, communication power increases $P_{text {comm}} propto N;(text {linearly})$ , resulting in overall higher power consumption. To address these challenges and reduce the communication energy of a video sensor node (VSN) while enabling a more compact form factor, we propose an analog voltage-to-time converter for VSN (ATC-Tx) that exploits a novel time-domain mode of body communication. This system directly converts analog video information into pulse-width modulated signals for transmission, leveraging the wideband characteristics of the human body communication (HBC) channel as the transmission medium. This approach enables low-power sensing and communication by eliminating the need for ADCs and digitization at energy-constrained VSNs. The ATC-Tx achieves an energy efficiency of 21.9 pJ/Sa, leveraging time-domain body communication (TD-BC), which results in a two-order-of-magnitude improvement over existing commercial off-the-shelf (COTS) components. This improvement is accompanied by a $sim 3times $ reduction in power consumption compared to the previous voltage mode electro-quasistatic HBC (EQS-HBC)-based implementation, as well as significant reductions in implementation area.
{"title":"ATC-Tx: A 21.9 pJ/Sa 110 μW Direct Pixel-to-PWM Converter and Time-Domain Body Communication Transmitter for Video Sensor Nodes","authors":"Gourab Barik;Samyadip Sarkar;Baibhab Chatterjee;Gaurav K. Kumar;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3642795","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642795","url":null,"abstract":"With the rapid advancement of the Internet of Things (IoT) and its expanding applications in health monitoring, body-worn cameras, and smart glasses, the demand for high data rate (DR) video transmission and compact device size has become critical. This shift has necessitated the development of low-power communication systems and battery-efficient or battery-less designs. Traditional high-data-rate communication methods consume mWs of power, such as Wi-Fi and backscatter communication (for high DRs, higher transmitter power is required to handle the two-fold path loss between the transmitter and sensor node), and require converting analog information into digital bits before transmission. These approaches rely on analog-to-digital converters (ADCs), which generate substantial data volumes, resulting in increased storage and processing demands while consuming significant power <inline-formula> <tex-math>$P_{text {ADC}} propto 2^{N};(text {exponential}) $ </tex-math></inline-formula>, where <inline-formula> <tex-math>$N$ </tex-math></inline-formula> is the number of bits. Consequently, communication power increases <inline-formula> <tex-math>$P_{text {comm}} propto N;(text {linearly})$ </tex-math></inline-formula>, resulting in overall higher power consumption. To address these challenges and reduce the communication energy of a video sensor node (VSN) while enabling a more compact form factor, we propose an analog voltage-to-time converter for VSN (ATC-Tx) that exploits a novel time-domain mode of body communication. This system directly converts analog video information into pulse-width modulated signals for transmission, leveraging the wideband characteristics of the human body communication (HBC) channel as the transmission medium. This approach enables low-power sensing and communication by eliminating the need for ADCs and digitization at energy-constrained VSNs. The ATC-Tx achieves an energy efficiency of 21.9 pJ/Sa, leveraging time-domain body communication (TD-BC), which results in a two-order-of-magnitude improvement over existing commercial off-the-shelf (COTS) components. This improvement is accompanied by a <inline-formula> <tex-math>$sim 3times $ </tex-math></inline-formula> reduction in power consumption compared to the previous voltage mode electro-quasistatic HBC (EQS-HBC)-based implementation, as well as significant reductions in implementation area.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"335-353"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a neural implant system for prosthetic limbs that enables simultaneous multisite data transmission via galvanically coupled body-channel communication (GC-BCC) for fine, low-latency control. Ultrasound and RF uplinks typically require multiple-access schemes to avoid collisions across implants. Capacitive BCC can support simultaneous links, but the small, motion-variant return-path capacitance reduces channel gain and undermines robustness. In contrast, GC-BCC forms a closed-loop current path for each transmitter–receiver pair via a dedicated termination, enabling simultaneous uplinks without multiple-access scheme. Implemented in 180-nm CMOS, the system integrates a 16-channel neural recording analog front end, a GC-BCC transceiver, and low-dropout regulators. Through 15-mm porcine tissue, the link sustains a 20-Mb/s data rate with a bit-error rate below $1.3 times 10^{-5}$ . Two GC-BCC transceivers operate simultaneously with 100-$Omega $ termination with negligible crosstalk at $geq 1.6$ -cm spacing. The measured energy efficiencies are 20.35 pJ/bit for the transmitter and 467.4 pJ/bit for the receiver.
{"title":"An Implantable Peripheral Nerve Interface System With Simultaneous Multisite Data Transmission via Galvanically Coupled Body-Channel Communication for Next-Generation Prosthetic Limbs","authors":"Dong-Hwi Choi;Dongyoon Lee;Yunchul Chung;Hyunyeop Lee;Kim Hoang Nguyen;Byeongseon Choi;Gichan Yun;Sohmyung Ha;Minkyu Je","doi":"10.1109/OJSSCS.2025.3642787","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642787","url":null,"abstract":"This article presents a neural implant system for prosthetic limbs that enables simultaneous multisite data transmission via galvanically coupled body-channel communication (GC-BCC) for fine, low-latency control. Ultrasound and RF uplinks typically require multiple-access schemes to avoid collisions across implants. Capacitive BCC can support simultaneous links, but the small, motion-variant return-path capacitance reduces channel gain and undermines robustness. In contrast, GC-BCC forms a closed-loop current path for each transmitter–receiver pair via a dedicated termination, enabling simultaneous uplinks without multiple-access scheme. Implemented in 180-nm CMOS, the system integrates a 16-channel neural recording analog front end, a GC-BCC transceiver, and low-dropout regulators. Through 15-mm porcine tissue, the link sustains a 20-Mb/s data rate with a bit-error rate below <inline-formula> <tex-math>$1.3 times 10^{-5}$ </tex-math></inline-formula>. Two GC-BCC transceivers operate simultaneously with 100-<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> termination with negligible crosstalk at <inline-formula> <tex-math>$geq 1.6$ </tex-math></inline-formula>-cm spacing. The measured energy efficiencies are 20.35 pJ/bit for the transmitter and 467.4 pJ/bit for the receiver.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"324-334"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293770","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents an energy-autonomous, self-resetting (SR), and multi-node temperature sensor powered by hybrid energy harvesting (EH). The ultralow leakage self-adaptive full bridge rectifier (SA-FBR) accepts any hybrid EH source at both sparse and abundant inputs and suppresses the leakage by $1000times $ . The dynamic power management unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in $0.18~mu $ m CMOS uses active SR, spike-based coding to achieve the widest measurement range of –$10~^{circ }$ C to $110~^{circ }$ C to date.
本文介绍了一种由混合能量收集（EH）驱动的能量自主、自复位（SR）和多节点温度传感器。超低漏自适应全桥整流器（SA-FBR）在稀疏和丰富输入下接受任何混合EH源，并将泄漏抑制1000倍。动态电源管理单元（D-PMU）支持事件驱动的唤醒功能，可在待机模式下节省97.3%的电量。0.5 nJ/转换温度传感器在$0.18~mu $ m CMOS中使用有源SR，基于峰值的编码，以实现迄今为止最宽的测量范围- $10~^{circ}$ C至$110~^{circ}$ C。
{"title":"A 0.5 nJ/Conversion Self-Resetting Energy-Autonomous Multi-Node Temperature Sensor With Hybrid Energy Harvesting","authors":"Joanne Si Ying Tan;Zhuoyue Li;Chne-Wuen Tsai;Jeong Hoan Park;Jiamin Li;Yilong Dong;Kwok Hoe Chan;Ghim Wei Ho;Jerald Yoo","doi":"10.1109/OJSSCS.2025.3642796","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642796","url":null,"abstract":"This article presents an energy-autonomous, self-resetting (SR), and multi-node temperature sensor powered by hybrid energy harvesting (EH). The ultralow leakage self-adaptive full bridge rectifier (SA-FBR) accepts any hybrid EH source at both sparse and abundant inputs and suppresses the leakage by <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula>. The dynamic power management unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS uses active SR, spike-based coding to achieve the widest measurement range of –<inline-formula> <tex-math>$10~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$110~^{circ }$ </tex-math></inline-formula>C to date.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"377-387"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293796","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/OJSSCS.2025.3636845
Thomas J. Hoen;Alexander S. Delke;Yanyu Jin;Jos Verlinden;Bram Nauta;Anne-Johan Annema
This article describes a CMOS frequency reference system that achieves quartz-crystal-oscillator-rivaling frequency accuracy and power consumption across a temperature range of 228 °C, with low degradation over lifetime. This system uses only a batch calibration and a sample-specific single-temperature production-time calibration. The reference frequency is generated by a tunable RC-based oscillator (RCO) at relatively low power. The RCO’s significant process and temperature dependencies, and degradation over lifetime, are eliminated by periodically recalibrating it to a co-integrated inherently robust LC-oscillator (LCO). The resulting hybrid RC/LC CMOS frequency reference system combines the low-power properties of the RCO and the single-trim highly accurate and low-aging properties of an LCO. This article reviews circuit and system aspects of this frequency reference system, complemented with measurement results and insights for key devices and for many effects that limit system accuracy over wide temperature ranges and over lifetime.
{"title":"Single-Trim Highly Accurate Frequency Reference Techniques","authors":"Thomas J. Hoen;Alexander S. Delke;Yanyu Jin;Jos Verlinden;Bram Nauta;Anne-Johan Annema","doi":"10.1109/OJSSCS.2025.3636845","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3636845","url":null,"abstract":"This article describes a CMOS frequency reference system that achieves quartz-crystal-oscillator-rivaling frequency accuracy and power consumption across a temperature range of 228 °C, with low degradation over lifetime. This system uses only a batch calibration and a sample-specific single-temperature production-time calibration. The reference frequency is generated by a tunable RC-based oscillator (RCO) at relatively low power. The RCO’s significant process and temperature dependencies, and degradation over lifetime, are eliminated by periodically recalibrating it to a co-integrated inherently robust LC-oscillator (LCO). The resulting hybrid RC/LC CMOS frequency reference system combines the low-power properties of the RCO and the single-trim highly accurate and low-aging properties of an LCO. This article reviews circuit and system aspects of this frequency reference system, complemented with measurement results and insights for key devices and for many effects that limit system accuracy over wide temperature ranges and over lifetime.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"481-496"},"PeriodicalIF":3.2,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11268377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The rapid growth of power-constrained applications, including the Internet of Things (IoT) and wearables, demands sensor interfaces with high accuracy and reliability. A fundamental design challenge arises as their performance is severely limited by thermal drift within the analog front-end (AFE) and analog-to-digital converter (ADC) circuits. To address this, this article reviews two principal strategies: 1) the development of robust voltage and frequency reference circuits and 2) the implementation of on-chip temperature calibration. The review covers state-of-the-art temperature-compensated voltage references, such as subthreshold and BJT/MOS hybrid architectures, as well as stable frequency references based on LC and RC time constants. Furthermore, it examines advanced sensor interfaces that integrate on-chip temperature sensors for real-time error correction, featuring recent case studies on current sensor designs. These comprehensive advances are crucial for enabling reliable, energy-efficient sensor interfaces intended for precision-critical applications.
{"title":"Recent Advances in Energy-Efficient and Temperature-Resilient Sensor Interfaces","authors":"Woojun Choi;Inhee Lee;Youngwoo Ji;Alexander Delke;Sining Pan;Zhong Tang;Youngcheol Chae","doi":"10.1109/OJSSCS.2025.3634970","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3634970","url":null,"abstract":"The rapid growth of power-constrained applications, including the Internet of Things (IoT) and wearables, demands sensor interfaces with high accuracy and reliability. A fundamental design challenge arises as their performance is severely limited by thermal drift within the analog front-end (AFE) and analog-to-digital converter (ADC) circuits. To address this, this article reviews two principal strategies: 1) the development of robust voltage and frequency reference circuits and 2) the implementation of on-chip temperature calibration. The review covers state-of-the-art temperature-compensated voltage references, such as subthreshold and BJT/MOS hybrid architectures, as well as stable frequency references based on LC and RC time constants. Furthermore, it examines advanced sensor interfaces that integrate on-chip temperature sensors for real-time error correction, featuring recent case studies on current sensor designs. These comprehensive advances are crucial for enabling reliable, energy-efficient sensor interfaces intended for precision-critical applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"456-469"},"PeriodicalIF":3.2,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11260455","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-18DOI: 10.1109/OJSSCS.2025.3633660
Ayman Sakr;Mohamed Atef Hassan;Jens Anders
Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<$10~mu $ A). This work addresses these shortcomings by generating a complementary-to-absolute-temperature (CTAT) current that reproduces the temperature dependence of the proportional-to-absolute-temperature (PTAT) current, including its curvature over process corners, eliminating multitemperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-$mu $ A to single-digit $mu $ A range. To validate the proposed approach, we fabricated a prototype design in a 130-nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6 to 3 V. Measurements from 10 chips yield a mean current of $1.1~mu $ A ($sigma $ /$mu ~approx ~4.4$ %) close to the design target of $1.2~mu $ A. Experimental results further demonstrate an average TC of 110 ppm/°C from $0~^{circ }$ C to $100~^{circ }$ C without multitemperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.
传统的基于带隙的电流参考具有各种局限性。这包括跨工艺角落的大温度系数（tc），需要昂贵的修剪周期，以及低电流值的面积效率低下（$10~mu $ A）。这项工作通过产生互补绝对温度（CTAT）电流来解决这些缺点，该电流再现了比例绝对温度（PTAT）电流的温度依赖性，包括其在工艺拐角上的曲率，消除了多温度TC修剪，同时保留了单点室温校准来设置绝对电流。该设计通过依靠电子迁移率的温度稳定负TC来产生CTAT电流，而不是基于非线性和工艺敏感二极管的CTAT产生，从而提供了这种匹配的PTAT/CTAT特性。此外，由于基于迁移率的CTAT生成，可以使用具有强负TC的高电阻率未掺多电阻，从而在次$mu $ a至一位数$mu $ a范围内实现面积高效的CTAT电流生成。为了验证所提出的方法，我们制作了一个130纳米SOI CMOS技术的原型设计，占用的有效面积仅为0.016 mm2，工作在1.6到3 V的宽电源范围内。来自10个芯片的测量产生的平均电流为$1.1~mu $ a （$sigma $ /） $mu ~approx ~4.4$ %) close to the design target of $1.2~mu $ A. Experimental results further demonstrate an average TC of 110 ppm/°C from $0~^{circ }$ C to $100~^{circ }$ C without multitemperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.
{"title":"A PVT-Tolerant, Curvature-Compensated CMOS Bandgap-Based Current Reference With Single-Point Batch Trim","authors":"Ayman Sakr;Mohamed Atef Hassan;Jens Anders","doi":"10.1109/OJSSCS.2025.3633660","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3633660","url":null,"abstract":"Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>A). This work addresses these shortcomings by generating a complementary-to-absolute-temperature (CTAT) current that reproduces the temperature dependence of the proportional-to-absolute-temperature (PTAT) current, including its curvature over process corners, eliminating multitemperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A to single-digit <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A range. To validate the proposed approach, we fabricated a prototype design in a 130-nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6 to 3 V. Measurements from 10 chips yield a mean current of <inline-formula> <tex-math>$1.1~mu $ </tex-math></inline-formula>A (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>/<inline-formula> <tex-math>$mu ~approx ~4.4$ </tex-math></inline-formula>%) close to the design target of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula>A. Experimental results further demonstrate an average TC of 110 ppm/°C from <inline-formula> <tex-math>$0~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>C without multitemperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"470-480"},"PeriodicalIF":3.2,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11251149","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1109/OJSSCS.2025.3631573
Yuyi Shen;Ethan Chen;Vanessa Chen
Emerging Wireless sensor networks for deep space exploration demand highly reliable RF transmitters capable of operating in extreme environments, where temperatures can drop well below liquid nitrogen temperature. CMOS power amplifiers (PAs) for these systems must withstand wide temperature variations and preserve output power and linearity despite significant cryogenic shifts in MOSFET parameters such as threshold voltage and carrier mobility. Conventional process design kit (PDK) models, limited to–55 °C to 125 °C, exacerbate the challenge by offering insufficient support for cryogenic design and validation. This work introduces a high-efficiency current-steering CMOS PA designed for robust operation at cryogenic temperatures down to 4.2 K. The PA employs a reconfigurable output stage to compensate for temperature-induced device variations and uses current-steering device pairs to shape drain current at the output stage for enhancing efficiency and linearity. A 65-nm CMOS prototype achieves a peak drain efficiency (DE) of 42.8% and an OP1dB of 13.6 dBm at 6.3 GHz when cooled to 4.2 K. These results highlight the potential of highly configurable CMOS PAs for enabling energy-efficient wireless communication in space and other extreme cryogenic environments.
{"title":"A Current-Steering 6-GHz Power Amplifier With Extensive Reconfigurability for Cryogenic Operation in 65 nm CMOS","authors":"Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3631573","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3631573","url":null,"abstract":"Emerging W<sc>ireless</small> sensor networks for deep space exploration demand highly reliable RF transmitters capable of operating in extreme environments, where temperatures can drop well below liquid nitrogen temperature. CMOS power amplifiers (PAs) for these systems must withstand wide temperature variations and preserve output power and linearity despite significant cryogenic shifts in MOSFET parameters such as threshold voltage and carrier mobility. Conventional process design kit (PDK) models, limited to–55 °C to 125 °C, exacerbate the challenge by offering insufficient support for cryogenic design and validation. This work introduces a high-efficiency current-steering CMOS PA designed for robust operation at cryogenic temperatures down to 4.2 K. The PA employs a reconfigurable output stage to compensate for temperature-induced device variations and uses current-steering device pairs to shape drain current at the output stage for enhancing efficiency and linearity. A 65-nm CMOS prototype achieves a peak drain efficiency (DE) of 42.8% and an OP1dB of 13.6 dBm at 6.3 GHz when cooled to 4.2 K. These results highlight the potential of highly configurable CMOS PAs for enabling energy-efficient wireless communication in space and other extreme cryogenic environments.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"497-510"},"PeriodicalIF":3.2,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11240125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1109/OJSSCS.2025.3625891
Christine Weston;Rundao Lu;Zhengqi Xu;Hao Yu;Daniel Lambalot;Michael P. Flynn
A tileable 16-element, 4-beam, 28 GHz digital beamforming chiplet communicates over a power-efficient, low-latency Streaming-Advanced Interface Bus (AIB) data link to distribute digital beamforming processing across multiple chiplets. Spiral chiplet connectivity enables scaling to a large array size with a single beamforming chiplet design. The chiplet includes a 28 GHz frontend, analog-to-digital converters (ADCs), digital beamform processing and Streaming-AIB receive and transmit interfaces. A multichip digital phase-locked loop (PLL) ensures digital clock synchronization between chiplets. Scalability is demonstrated with a prototype 4-chiplet, 64-element module. Over-the-air tests confirm accurate 64-element beam patterns, a double-sideband (DSB) noise figure of 17 dB, a Streaming-AIB bit error rate (BER) of 3E-12, and a low power consumption of 23 mW per beam-channel.
{"title":"A 64-Element 28 GHz Digital Beamformer Based on Tileable Synchronized Distributed Beamforming Chiplets","authors":"Christine Weston;Rundao Lu;Zhengqi Xu;Hao Yu;Daniel Lambalot;Michael P. Flynn","doi":"10.1109/OJSSCS.2025.3625891","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3625891","url":null,"abstract":"A tileable 16-element, 4-beam, 28 GHz digital beamforming chiplet communicates over a power-efficient, low-latency Streaming-Advanced Interface Bus (AIB) data link to distribute digital beamforming processing across multiple chiplets. Spiral chiplet connectivity enables scaling to a large array size with a single beamforming chiplet design. The chiplet includes a 28 GHz frontend, analog-to-digital converters (ADCs), digital beamform processing and Streaming-AIB receive and transmit interfaces. A multichip digital phase-locked loop (PLL) ensures digital clock synchronization between chiplets. Scalability is demonstrated with a prototype 4-chiplet, 64-element module. Over-the-air tests confirm accurate 64-element beam patterns, a double-sideband (DSB) noise figure of 17 dB, a Streaming-AIB bit error rate (BER) of 3E-12, and a low power consumption of 23 mW per beam-channel.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"424-436"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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