Pub Date : 2024-12-16DOI: 10.1109/OJSSCS.2024.3519054
Minoru Fujishima
The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.
{"title":"Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication","authors":"Minoru Fujishima","doi":"10.1109/OJSSCS.2024.3519054","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519054","url":null,"abstract":"The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"21-32"},"PeriodicalIF":0.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78- $mu $ A rms, an averaged INRC density of 6.4 pA/ $sqrt {text {Hz}}$ , consumes 11.4 mW of power, and provides 87-dB $Omega $ transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.
{"title":"A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology","authors":"Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu","doi":"10.1109/OJSSCS.2024.3510478","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3510478","url":null,"abstract":"This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 A rms, an averaged INRC density of 6.4 pA/\u0000<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>\u0000, consumes 11.4 mW of power, and provides 87-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"328-339"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/OJSSCS.2024.3507754
Ali Sadr;Anthony Chan Carusone
This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing $4.7~{V}_{text {pp}}$ digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating $1.7~text {pJ/b}$ at $40~text {Gb/s}$ . With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of $540~mu text {W}$ (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.
本文提出了一种多目标热控制器，用于稳定硅光子微环调制器（MRMs）在不同温度条件和激光功率波动下的谐振波长。当实时数据流动时，控制器在后台运行，调整MRM共振波长以达到最佳的特定应用性能指标，包括消光比（ER），光调制幅度（OMA）或电平分离不匹配比（RLM）中的任何一个。这种通用偏置辅助光电流控制器能够选择性地调谐任何这些发射器指标，而不需要宽带电路。值得注意的是，这是第一个提出调整MRM以优化RLM的控制器，这一点尤其重要，因为MRM现在越来越多地用于4-PAM调制。控制器功能在单片集成于硅光子45纳米CMOS SOI工艺的MRM上进行验证，该MRM采用高摆幅4.7~{V}_{text {pp}}$数模转换器（DAC）的5.5位分辨率驱动程序，在$40~text {Gb/s}$时耗散$1.7~text {pJ/b}$。通过对控制器进行不同目标优化，在不采用非线性前馈均衡器（FFE）或预失真的情况下，实现了10.3 dB的ER、$540~mu text {W}$的OMA（归一化OMA为−3.2 dB）、0.67 dB的发射机色散闭眼四元（TDECQ）和0.96的RLM。
{"title":"A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller","authors":"Ali Sadr;Anthony Chan Carusone","doi":"10.1109/OJSSCS.2024.3507754","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3507754","url":null,"abstract":"This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing \u0000<inline-formula> <tex-math>$4.7~{V}_{text {pp}}$ </tex-math></inline-formula>\u0000 digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating \u0000<inline-formula> <tex-math>$1.7~text {pJ/b}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$40~text {Gb/s}$ </tex-math></inline-formula>\u0000. With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of \u0000<inline-formula> <tex-math>$540~mu text {W}$ </tex-math></inline-formula>\u0000 (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"340-350"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1109/OJSSCS.2024.3506692
Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim
High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.
{"title":"Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers","authors":"Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim","doi":"10.1109/OJSSCS.2024.3506692","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506692","url":null,"abstract":"High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"290-304"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.
{"title":"High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions","authors":"Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai","doi":"10.1109/OJSSCS.2024.3506694","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506694","url":null,"abstract":"The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"351-364"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1109/OJSSCS.2024.3503546
Changjae Moon;Minsoo Choi;Myungguk Lee;Byungsub Kim
From the perspective of channel behaviors, we review several design techniques of resistive termination for wireline applications. Termination impedances strongly affect the channel behaviors. Their impacts vary a lot depending on the types of interconnects and the circuits. Therefore, termination impedances must be appropriately designed for the target applications. In this article, first, we explain an intuitive analytical transfer function model of wireline channels. The model allows designers to easily and intuitively understand the impacts of the termination resistances on the channel behaviors. Second, we review various resistive termination techniques for LC-dominant channels and discuss their design tradeoffs. Especially, we theoretically explain the relaxed impedance matching technique, which allows designers to violate impedance matching for design improvements at the cost of a negligible penalty in signal integrity. Third, we review various resistive termination techniques for RC-dominant channels and their design tradeoffs. We especially emphasize and theoretically explain why and how the design tradeoffs by resistive terminations in RC-dominant channels are different from the ones in LC-dominant channels.
{"title":"Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors","authors":"Changjae Moon;Minsoo Choi;Myungguk Lee;Byungsub Kim","doi":"10.1109/OJSSCS.2024.3503546","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3503546","url":null,"abstract":"From the perspective of channel behaviors, we review several design techniques of resistive termination for wireline applications. Termination impedances strongly affect the channel behaviors. Their impacts vary a lot depending on the types of interconnects and the circuits. Therefore, termination impedances must be appropriately designed for the target applications. In this article, first, we explain an intuitive analytical transfer function model of wireline channels. The model allows designers to easily and intuitively understand the impacts of the termination resistances on the channel behaviors. Second, we review various resistive termination techniques for LC-dominant channels and discuss their design tradeoffs. Especially, we theoretically explain the relaxed impedance matching technique, which allows designers to violate impedance matching for design improvements at the cost of a negligible penalty in signal integrity. Third, we review various resistive termination techniques for RC-dominant channels and their design tradeoffs. We especially emphasize and theoretically explain why and how the design tradeoffs by resistive terminations in RC-dominant channels are different from the ones in LC-dominant channels.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"305-317"},"PeriodicalIF":0.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758758","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1109/OJSSCS.2024.3502315
Liping Zhong;Quan Pan
The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of < $10{^{-}10 }$ and < $10{^{-}12 }$ with a single-ended channel loss of 24 and 25 dB, respectively.
{"title":"Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s","authors":"Liping Zhong;Quan Pan","doi":"10.1109/OJSSCS.2024.3502315","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3502315","url":null,"abstract":"The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <\u0000<inline-formula> <tex-math>$10{^{-}10 }$ </tex-math></inline-formula>\u0000 and <\u0000<inline-formula> <tex-math>$10{^{-}12 }$ </tex-math></inline-formula>\u0000 with a single-ended channel loss of 24 and 25 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"318-327"},"PeriodicalIF":0.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10757331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142870210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/OJSSCS.2024.3499967
Makoto Nagata;Takuji Miki
Semiconductor integrated circuit (IC) chips are regularly exposed to physical attacks and faced to the compromise of information security. An attacker leverages Si substrate backside as the open surface of an IC chip in flip-chip packaging and explores the points of information leakage over the entire backside without being hampered by physical obstacles as well as applying invasive treatments. Physical side channels (SCs), e.g., voltage potentials, current flows, electromagnetic (EM) waves, and photons, are transparent through Si substrate and attributed to the operation of security ICs. An attacker measures SCs using probes as well as antennas and correlates them with secret information, such as secret key bytes, used in a cryptographic processor or analog quantities at the frontend of Internet of Things (IoT) gadgets. This article defines and elucidates the emerging threats of Si-substrate backside attacks on flipped IC chips, demonstrates attacks and proposes countermeasures.
{"title":"Si Substrate Backside—An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging","authors":"Makoto Nagata;Takuji Miki","doi":"10.1109/OJSSCS.2024.3499967","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3499967","url":null,"abstract":"Semiconductor integrated circuit (IC) chips are regularly exposed to physical attacks and faced to the compromise of information security. An attacker leverages Si substrate backside as the open surface of an IC chip in flip-chip packaging and explores the points of information leakage over the entire backside without being hampered by physical obstacles as well as applying invasive treatments. Physical side channels (SCs), e.g., voltage potentials, current flows, electromagnetic (EM) waves, and photons, are transparent through Si substrate and attributed to the operation of security ICs. An attacker measures SCs using probes as well as antennas and correlates them with secret information, such as secret key bytes, used in a cryptographic processor or analog quantities at the frontend of Internet of Things (IoT) gadgets. This article defines and elucidates the emerging threats of Si-substrate backside attacks on flipped IC chips, demonstrates attacks and proposes countermeasures.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"365-375"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10755152","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/OJSSCS.2024.3501975
Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen
System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.
{"title":"Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications","authors":"Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen","doi":"10.1109/OJSSCS.2024.3501975","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3501975","url":null,"abstract":"System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"265-276"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10756610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL ${mathrm {FoM}}_{text {jitter-N}}$ of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.
{"title":"Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques","authors":"Teerachot Siriburanon;Chunxiao Liu;Jianglin Du;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3493803","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3493803","url":null,"abstract":"This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL \u0000<inline-formula> <tex-math>${mathrm {FoM}}_{text {jitter-N}}$ </tex-math></inline-formula>\u0000 of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"212-225"},"PeriodicalIF":0.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10746550","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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