Pub Date : 2023-09-08DOI: 10.1109/OJSSCS.2023.3311418
Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae
The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.
{"title":"Design Techniques for Energy-Efficient Analog-to-Digital Converters","authors":"Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae","doi":"10.1109/OJSSCS.2023.3311418","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3311418","url":null,"abstract":"The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"145-161"},"PeriodicalIF":0.0,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10246164.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-06DOI: 10.1109/OJSSCS.2023.3312354
Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai
A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of $3.8 ~mu text{W}$ at 250 kHz and the normalized energy efficiency is $2.79times $ higher than state of the art.
{"title":"A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks","authors":"Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai","doi":"10.1109/OJSSCS.2023.3312354","DOIUrl":"10.1109/OJSSCS.2023.3312354","url":null,"abstract":"A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of \u0000<inline-formula> <tex-math>$3.8 ~mu text{W}$ </tex-math></inline-formula>\u0000 at 250 kHz and the normalized energy efficiency is \u0000<inline-formula> <tex-math>$2.79times $ </tex-math></inline-formula>\u0000 higher than state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"185-196"},"PeriodicalIF":0.0,"publicationDate":"2023-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10242041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79901424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-11DOI: 10.1109/OJSSCS.2023.3304599
Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang
This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and $1.2times /1.4times $ power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).
{"title":"A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network","authors":"Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang","doi":"10.1109/OJSSCS.2023.3304599","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3304599","url":null,"abstract":"This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and \u0000<inline-formula> <tex-math>$1.2times /1.4times $ </tex-math></inline-formula>\u0000 power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"134-144"},"PeriodicalIF":0.0,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10214532.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-06DOI: 10.1109/OJSSCS.2023.3281904
Jerald Yoo
Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.
{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics","authors":"Jerald Yoo","doi":"10.1109/OJSSCS.2023.3281904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3281904","url":null,"abstract":"Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"63-64"},"PeriodicalIF":0.0,"publicationDate":"2023-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10174830.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-28DOI: 10.1109/OJSSCS.2023.3290550
Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers
This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power $(P_{mathrm{ out}})$ and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a $1.76times $ and $1.93times $ improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average $P_{mathrm{ out}}$ of 14 dBm with an r.m.s. error vector magnitude $({mathrm{ EVM}}_{mathrm{ rms}})$ of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.
{"title":"A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network","authors":"Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3290550","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290550","url":null,"abstract":"This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power \u0000<inline-formula> <tex-math>$(P_{mathrm{ out}})$ </tex-math></inline-formula>\u0000 and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a \u0000<inline-formula> <tex-math>$1.76times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.93times $ </tex-math></inline-formula>\u0000 improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average \u0000<inline-formula> <tex-math>$P_{mathrm{ out}}$ </tex-math></inline-formula>\u0000 of 14 dBm with an r.m.s. error vector magnitude \u0000<inline-formula> <tex-math>$({mathrm{ EVM}}_{mathrm{ rms}})$ </tex-math></inline-formula>\u0000 of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"103-117"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167796.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-28DOI: 10.1109/OJSSCS.2023.3290551
Behzad Razavi
Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.
{"title":"Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2023.3290551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290551","url":null,"abstract":"Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"118-133"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167779.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-12DOI: 10.1109/OJSSCS.2023.3266540
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2023.3266540","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3266540","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2023-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10101697.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-14DOI: 10.1109/OJSSCS.2023.3244759
Po-Han Chen;Shu-Wen Yang;Chao-Tsung Huang
Digital refocusing in multicamera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this article, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/s throughput. The hardware accelerator improves the processing speed by $100times $ to $350times $ that of the original refocusing algorithm running on a general-purpose processor. The chip is fabricated with 40-nm CMOS technology and comprises 271 kB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames/s under 250 mW power consumption.
{"title":"A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices","authors":"Po-Han Chen;Shu-Wen Yang;Chao-Tsung Huang","doi":"10.1109/OJSSCS.2023.3244759","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3244759","url":null,"abstract":"Digital refocusing in multicamera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this article, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/s throughput. The hardware accelerator improves the processing speed by \u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$350times $ </tex-math></inline-formula>\u0000 that of the original refocusing algorithm running on a general-purpose processor. The chip is fabricated with 40-nm CMOS technology and comprises 271 kB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames/s under 250 mW power consumption.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"52-62"},"PeriodicalIF":0.0,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10044201.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-12DOI: 10.1109/OJSSCS.2023.3236305
Hamed Mazhab Jafari;Xilin Liu;Roman Genov
Accurate temperature regulation is critical for amperometric DNA analysis to achieve high fidelity, reliability, and throughput. In this work, a $9times 6$ cell array of mixed-signal CMOS distributed temperature regulators for on-CMOS multimodal amperometric DNA analysis is presented. Three DNA analysis methods are supported, including constant potential amperometry (CPA), cyclic voltammetry (CV), and impedance spectroscopy (IS). In-cell heating and temperature-sensing elements are implemented in standard CMOS technology without post-processing. Using proportional–integral–derivative (PID) control, the local temperature can be regulated to within ±0.5 °C of any desired value between 20 °C and 90 °C. To allow the in-cell integration of independent PID control, a new mixed-signal design is proposed, where the two computationally intensive operations in the PID algorithm, multiplication and subtraction, are performed by an in-cell dual-slope multiplying ADC, resulting in a small area and low power consumption. Over 95% of the circuit blocks are synergistically shared among the four operating modes, including CPA, CV, IS, and the proposed temperature regulation mode. A 3 mm $times3$ mm CMOS prototype fabricated in a 0.13- $mu text{m}$ CMOS technology has been fully experimentally characterized. The proposed distributed temperature regulation design and the mixed-signal PID implementation can be applied to a wide range of sensory and other applications.
{"title":"Synergistic Distributed Thermal Regulation for On-CMOS High-Throughput Multimodal Amperometric DNA-Array Analysis","authors":"Hamed Mazhab Jafari;Xilin Liu;Roman Genov","doi":"10.1109/OJSSCS.2023.3236305","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3236305","url":null,"abstract":"Accurate temperature regulation is critical for amperometric DNA analysis to achieve high fidelity, reliability, and throughput. In this work, a \u0000<inline-formula> <tex-math>$9times 6$ </tex-math></inline-formula>\u0000 cell array of mixed-signal CMOS distributed temperature regulators for on-CMOS multimodal amperometric DNA analysis is presented. Three DNA analysis methods are supported, including constant potential amperometry (CPA), cyclic voltammetry (CV), and impedance spectroscopy (IS). In-cell heating and temperature-sensing elements are implemented in standard CMOS technology without post-processing. Using proportional–integral–derivative (PID) control, the local temperature can be regulated to within ±0.5 °C of any desired value between 20 °C and 90 °C. To allow the in-cell integration of independent PID control, a new mixed-signal design is proposed, where the two computationally intensive operations in the PID algorithm, multiplication and subtraction, are performed by an in-cell dual-slope multiplying ADC, resulting in a small area and low power consumption. Over 95% of the circuit blocks are synergistically shared among the four operating modes, including CPA, CV, IS, and the proposed temperature regulation mode. A 3 mm \u0000<inline-formula> <tex-math>$times3$ </tex-math></inline-formula>\u0000 mm CMOS prototype fabricated in a 0.13-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology has been fully experimentally characterized. The proposed distributed temperature regulation design and the mixed-signal PID implementation can be applied to a wide range of sensory and other applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"89-102"},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10015870.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJSSCS.2024.3363396
{"title":"2023 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 3","authors":"","doi":"10.1109/OJSSCS.2024.3363396","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3363396","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"274-280"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10423723","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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