Pub Date : 2025-03-27DOI: 10.1109/OJSSCS.2025.3573905
Wenyu Peng;Xinling Yue;Willem D. van Driel;Guoqi Zhang;Sijun Du
Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage ac output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-$mu $ m BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.
{"title":"A Dual-SSHC Rectifier With Digital-DCB MPPT for Triboelectric Energy Harvesting","authors":"Wenyu Peng;Xinling Yue;Willem D. van Driel;Guoqi Zhang;Sijun Du","doi":"10.1109/OJSSCS.2025.3573905","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3573905","url":null,"abstract":"Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage ac output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"200-211"},"PeriodicalIF":0.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11016074","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-21DOI: 10.1109/OJSSCS.2025.3540393
Woogeun Rhee
{"title":"New Associate Editors","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3540393","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3540393","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"101-103"},"PeriodicalIF":0.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/OJSSCS.2025.3571334
Archisman Ghosh;Dong-Hyun Seo;Debayan Das;Santosh Ghosh;Shreyas Sen
Side-channel attacks (SCAs) remain a significant threat to the security of cryptographic systems in modern embedded devices. Even mathematically secure cryptographic algorithms, when implemented in hardware, inadvertently leak information through physical side-channel signatures, such as power consumption, electromagnetic (EM) radiation, light emissions, and acoustic emanations. Exploiting these side channels significantly reduces the attacker’s search space. In recent years, physical countermeasures have significantly increased the minimum traces-to-disclosure (MTD) to 1 billion. Among them, signature attenuation is the first method to achieve this mark. Signature attenuation often relies on analog techniques, and digital signature attenuation reduces MTD to 20 million, requiring additional methods for high resilience. We focus on improving the digital signature attenuation by an order of magnitude (MTD 200M). Additionally, we explore possible attacks against signature attenuation countermeasure. We introduce a voltage-drop linear-region biasing (VLB) attack technique that reduces the MTD to over 2000 times less than the previous threshold. This is the first known attack against a physical SCA countermeasure. We have implemented an attack detector with a response time of 0.8 ms to detect such attacks, limiting the SCA leakage window to sub-ms, which is insufficient for a successful attack.
{"title":"R-STELLAR: A Resilient Synthesizable Signature Attenuation SCA Protection on AES-256 With Built-In Attack-on-Countermeasure Detection","authors":"Archisman Ghosh;Dong-Hyun Seo;Debayan Das;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3571334","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3571334","url":null,"abstract":"Side-channel attacks (SCAs) remain a significant threat to the security of cryptographic systems in modern embedded devices. Even mathematically secure cryptographic algorithms, when implemented in hardware, inadvertently leak information through physical side-channel signatures, such as power consumption, electromagnetic (EM) radiation, light emissions, and acoustic emanations. Exploiting these side channels significantly reduces the attacker’s search space. In recent years, physical countermeasures have significantly increased the minimum traces-to-disclosure (MTD) to 1 billion. Among them, signature attenuation is the first method to achieve this mark. Signature attenuation often relies on analog techniques, and digital signature attenuation reduces MTD to 20 million, requiring additional methods for high resilience. We focus on improving the digital signature attenuation by an order of magnitude (MTD 200M). Additionally, we explore possible attacks against signature attenuation countermeasure. We introduce a voltage-drop linear-region biasing (VLB) attack technique that reduces the MTD to over 2000 times less than the previous threshold. This is the first known attack against a physical SCA countermeasure. We have implemented an attack detector with a response time of 0.8 ms to detect such attacks, limiting the SCA leakage window to sub-ms, which is insufficient for a successful attack.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"167-179"},"PeriodicalIF":0.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006887","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1109/OJSSCS.2025.3546889
Durand Jarrett-Amor;Tony Chan Carusone
This article reviews simultaneous bidirectional signaling and its unique signal integrity challenges for die-to-die links: the near-end echo signal and the hybrid circuit required to remove it, signal reflections, and the impact of timing. A few key works in the design of simultaneous bidirectional transceivers are covered, such as dynamic reference-switching, the replica driver, and the split-termination hybrid, followed by a survey of recent simultaneous bidirectional transceivers for die-to-die links. Finally, we present our own split-termination, passive hybrid simultaneous bidirectional transceiver as a low-power alternative for die-to-die links.
{"title":"Simultaneous Bidirectional Signaling for Die-to-Die Links: Signal Integrity Challenges and Hybrid Circuits","authors":"Durand Jarrett-Amor;Tony Chan Carusone","doi":"10.1109/OJSSCS.2025.3546889","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3546889","url":null,"abstract":"This article reviews simultaneous bidirectional signaling and its unique signal integrity challenges for die-to-die links: the near-end echo signal and the hybrid circuit required to remove it, signal reflections, and the impact of timing. A few key works in the design of simultaneous bidirectional transceivers are covered, such as dynamic reference-switching, the replica driver, and the split-termination hybrid, followed by a survey of recent simultaneous bidirectional transceivers for die-to-die links. Finally, we present our own split-termination, passive hybrid simultaneous bidirectional transceiver as a low-power alternative for die-to-die links.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"116-129"},"PeriodicalIF":0.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10907904","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/OJSSCS.2025.3545275
{"title":"2024 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 4","authors":"","doi":"10.1109/OJSSCS.2025.3545275","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3545275","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"381-390"},"PeriodicalIF":0.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1109/OJSSCS.2025.3526922
Woogeun Rhee
{"title":"Editorial Message From the Incoming Editor-in-Chief","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3526922","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526922","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"378-378"},"PeriodicalIF":0.0,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10896768","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-19DOI: 10.1109/OJSSCS.2025.3526924
Sam Palermo;Jaeduk Han
{"title":"Editorial Special section on High-Performance Wireline Transceiver Circuits","authors":"Sam Palermo;Jaeduk Han","doi":"10.1109/OJSSCS.2025.3526924","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526924","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"379-380"},"PeriodicalIF":0.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-19DOI: 10.1109/OJSSCS.2025.3543761
Ke Li;Liang Qi;Mingqiang Guo;Rui P. Martins;Sai-Weng Sin
Continuous-time (CT) delta-sigma modulator (DSM) is a popular choice for its inherent aliasing and resistive input impedance characteristics. With the increased demands for wide-bandwidth (BW) and high-dynamic range (DR), multistage noise shaping (MASH) presents prominent benefits of high-order noise-shaping (NS) without being constrained by $Delta Sigma $ loop stability issues. Recent literature on CT MASH DSM showed promising progress in overcoming the design challenges under wideband application, including signal and quantization leakage, analog-digital matching complexity, signal transfer function (STF) peaking, and high-speed excess loop delay (ELD) compensation. This review article introduces fundamental models and primary design considerations, then discusses the CT MASH DSM’s key challenges and corresponding solutions. Finally, we provide two implementation examples of this architecture with their highlights and challenges.
{"title":"Wideband Continuous-Time MASH ADCs: Principles, Challenges, and Prospects","authors":"Ke Li;Liang Qi;Mingqiang Guo;Rui P. Martins;Sai-Weng Sin","doi":"10.1109/OJSSCS.2025.3543761","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3543761","url":null,"abstract":"Continuous-time (CT) delta-sigma modulator (DSM) is a popular choice for its inherent aliasing and resistive input impedance characteristics. With the increased demands for wide-bandwidth (BW) and high-dynamic range (DR), multistage noise shaping (MASH) presents prominent benefits of high-order noise-shaping (NS) without being constrained by <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> loop stability issues. Recent literature on CT MASH DSM showed promising progress in overcoming the design challenges under wideband application, including signal and quantization leakage, analog-digital matching complexity, signal transfer function (STF) peaking, and high-speed excess loop delay (ELD) compensation. This review article introduces fundamental models and primary design considerations, then discusses the CT MASH DSM’s key challenges and corresponding solutions. Finally, we provide two implementation examples of this architecture with their highlights and challenges.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"104-115"},"PeriodicalIF":0.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892233","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1109/OJSSCS.2025.3526923
Salvatore Levantino;Wanghua Wu
{"title":"Editorial Special Section on High-Performance Frequency Synthesizers","authors":"Salvatore Levantino;Wanghua Wu","doi":"10.1109/OJSSCS.2025.3526923","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526923","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"376-377"},"PeriodicalIF":0.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877780","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143360883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—$0.026~mu $ m2, and high current—$0.032~mu $ m2).
{"title":"SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology","authors":"Rajiv V. Joshi;J. Frougier;Alberto Cestero;Crystal Castellanos;Sudipto Chakraborty;Carl Radens;M. Silvestre;S. Lucarini;I. Ahsan;E. Leobandung","doi":"10.1109/OJSSCS.2024.3524495","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524495","url":null,"abstract":"A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math>$0.026~mu $ </tex-math></inline-formula>m<sup>2</sup>, and high current—<inline-formula> <tex-math>$0.032~mu $ </tex-math></inline-formula>m<sup>2</sup>).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"60-74"},"PeriodicalIF":0.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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