Pub Date : 2025-10-27DOI: 10.1109/OJSSCS.2025.3624690
Henrique Pocinho;Rodrigo Capeleiro;Tiago Moita;José Proença;Floriberto Lima;Marcelino B. Dos Santos;Fábio Passos
This article presents a dynamically reconfigurable power management unit (PMU) with self-monitoring capabilities, designed to enable ultralow power (ULP) operation. The proposed system consumes just $1.68~{mu }$ W, which represents a 30% reduction in power consumption when compared to state-of-the-art implementations operating at 32 kHz. Fabricated in 22-nm FD-SOI technology, the proposed PMU leverages a novel real-time clock (RTC) architecture that provides performance and workload self-monitoring capabilities and also has the capability to change its operation modes automatically based on current workload. With the usage of such RTC, the PMU eliminates the need for external control units, complex state machines or processors, significantly reducing system complexity and silicon area. Since RTCs are already present in many systems and the proposed architecture only requires a 15% area increase for additional state-control registers, it makes it particularly well-suited for implantable, wearable or other Internet of Medical Things (IoMT) devices, where energy autonomy, system miniaturization, and safe long-term operation are essential.
{"title":"A Dynamically Reconfigurable Power Management System With Self-Monitoring Capabilities for Energy-Efficient SoCs","authors":"Henrique Pocinho;Rodrigo Capeleiro;Tiago Moita;José Proença;Floriberto Lima;Marcelino B. Dos Santos;Fábio Passos","doi":"10.1109/OJSSCS.2025.3624690","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3624690","url":null,"abstract":"This article presents a dynamically reconfigurable power management unit (PMU) with self-monitoring capabilities, designed to enable ultralow power (ULP) operation. The proposed system consumes just <inline-formula> <tex-math>$1.68~{mu }$ </tex-math></inline-formula>W, which represents a 30% reduction in power consumption when compared to state-of-the-art implementations operating at 32 kHz. Fabricated in 22-nm FD-SOI technology, the proposed PMU leverages a novel real-time clock (RTC) architecture that provides performance and workload self-monitoring capabilities and also has the capability to change its operation modes automatically based on current workload. With the usage of such RTC, the PMU eliminates the need for external control units, complex state machines or processors, significantly reducing system complexity and silicon area. Since RTCs are already present in many systems and the proposed architecture only requires a 15% area increase for additional state-control registers, it makes it particularly well-suited for implantable, wearable or other Internet of Medical Things (IoMT) devices, where energy autonomy, system miniaturization, and safe long-term operation are essential.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"365-376"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218198","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1109/OJSSCS.2025.3626314
Lukas Pfromm;Alish Kanani;Harsh Sharma;Janardhan Rao Doppa;Partha Pratim Pande;Umit Y. Ogras
Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework’s versatility, up to 340% accuracy improvement, and power/thermal analysis capability.
{"title":"CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems","authors":"Lukas Pfromm;Alish Kanani;Harsh Sharma;Janardhan Rao Doppa;Partha Pratim Pande;Umit Y. Ogras","doi":"10.1109/OJSSCS.2025.3626314","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3626314","url":null,"abstract":"Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework’s versatility, up to 340% accuracy improvement, and power/thermal analysis capability.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"410-423"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218851","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/OJSSCS.2025.3622592
Behzad Razavi
Millimeter-wave radios hold promise for supporting high data rates in wireless communication. A key challenge in the development of these radios relates to the generation of the local oscillator (LO) waveform(s) necessary for upconversion and downconversion. This article presents a number of such techniques in the context of four receivers operating at 28, 140, and 300 GHz. The proposed concepts focus on fundamental-mode LO synthesis and high-speed inductorless frequency dividers. New methods of LO phase shifting for beamforming applications are also introduced. The prototypes have been fabricated in 28-nm CMOS technology and exhibit rms jitter values ranging from 106 fs to 640 fs.
{"title":"LO Generation Techniques for Millimeter-Wave Receivers","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2025.3622592","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3622592","url":null,"abstract":"Millimeter-wave radios hold promise for supporting high data rates in wireless communication. A key challenge in the development of these radios relates to the generation of the local oscillator (LO) waveform(s) necessary for upconversion and downconversion. This article presents a number of such techniques in the context of four receivers operating at 28, 140, and 300 GHz. The proposed concepts focus on fundamental-mode LO synthesis and high-speed inductorless frequency dividers. New methods of LO phase shifting for beamforming applications are also introduced. The prototypes have been fabricated in 28-nm CMOS technology and exhibit rms jitter values ranging from 106 fs to 640 fs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"310-321"},"PeriodicalIF":3.2,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11206376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/OJSSCS.2025.3616271
Wei Deng;Minyoung Song;Aarno Pärssinen
{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on RF Circuits and Wireless Transceivers","authors":"Wei Deng;Minyoung Song;Aarno Pärssinen","doi":"10.1109/OJSSCS.2025.3616271","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3616271","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"269-270"},"PeriodicalIF":3.2,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202698","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Panel-scale reconfigurable photonic interconnects on a glass substrate up to 500-mm $times 500$ -mm or larger are envisioned by proposing a novel photonic switch fabric that enables all directional panel-edge-to-panel-edge reach without active repeaters while offering high communication bandwidth, planar-direction reconfigurability, low energy consumption, and compelling data bandwidth density for heterogeneous integration of an in-package artificial intelligence computing system on a photonic interposer exceeding thousands of centimeters square. The proposed approach focuses on reconfigurable photonic interconnects, which are integration-compatible with commercial processor chiplets and 3-D high-bandwidth memory stacks, to create a novel panel-scale heterogeneously integrated package enabled by high-capacity wavelength-division-multiplexing optical data links using advanced optical modulators, broadband photodetector, novel optical crossbar switches with multilayer waveguides, and on-chip frequency comb sources.
{"title":"Panel-Scale Reconfigurable Photonic Interconnects for Scalable AI Computation","authors":"Tzu-Chien Hsueh;Bill Lin;Zijun Chen;Yeshaiahu Fainman","doi":"10.1109/OJSSCS.2025.3620371","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3620371","url":null,"abstract":"Panel-scale reconfigurable photonic interconnects on a glass substrate up to 500-mm <inline-formula> <tex-math>$times 500$ </tex-math></inline-formula>-mm or larger are envisioned by proposing a novel photonic switch fabric that enables all directional panel-edge-to-panel-edge reach without active repeaters while offering high communication bandwidth, planar-direction reconfigurability, low energy consumption, and compelling data bandwidth density for heterogeneous integration of an in-package artificial intelligence computing system on a photonic interposer exceeding thousands of centimeters square. The proposed approach focuses on reconfigurable photonic interconnects, which are integration-compatible with commercial processor chiplets and 3-D high-bandwidth memory stacks, to create a novel panel-scale heterogeneously integrated package enabled by high-capacity wavelength-division-multiplexing optical data links using advanced optical modulators, broadband photodetector, novel optical crossbar switches with multilayer waveguides, and on-chip frequency comb sources.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"437-453"},"PeriodicalIF":3.2,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11201050","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/OJSSCS.2025.3610567
Archisman Ghosh;Md. Abdur Rahman;Debayan Das;Santosh Ghosh;Shreyas Sen
Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the $V_{DD}$ port. Although any digital implementation has two generic ports, namely, clock and $V_{DD}$ , circuit-level countermeasures primarily focus on the $V_{DD}$ port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by $100times $ with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect ($1800times $ ) more than the multiplication of individual techniques ($100times $ and $5times $ , respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).
{"title":"Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Toward Power and EMSCA Resilience","authors":"Archisman Ghosh;Md. Abdur Rahman;Debayan Das;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3610567","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610567","url":null,"abstract":"Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port. Although any digital implementation has two generic ports, namely, clock and <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>, circuit-level countermeasures primarily focus on the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect (<inline-formula> <tex-math>$1800times $ </tex-math></inline-formula>) more than the multiplication of individual techniques (<inline-formula> <tex-math>$100times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$5times $ </tex-math></inline-formula>, respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"295-309"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/OJSSCS.2025.3610583
Jiawei Xu;Tianxiang Qu;Qinjing Pan;Yijie Li;Liheng Liu;Yuying Li;Jianhong Zhou;Chang Yao;Zhiliang Hong
Wearable platforms that concurrently acquire multiple physiological signals enable comprehensive health monitoring but impose stringent requirements on front-end circuit design. The reliable extraction of low-amplitude and low-frequency biosignals is hindered by electrode offset, noise, motion artifacts, and environmental interference. Recent efforts have advanced analog front ends (AFEs) for biopotential (ExG), bioimpedance (BioZ), and photoplethysmography (PPG) sensing, with emphasis on optimizing key metrics such as noise efficiency, input impedance, dynamic range, CMRR, and power consumption. In addition, digitally-assisted calibration and direct-digitization schemes have emerged as alternative design directions, offering enhanced robustness and scalability while introducing tradeoffs in complexity and energy efficiency. This review surveys these circuit techniques, analyzes their design tradeoffs, and outlines future opportunities for next-generation wearable biomedical interfaces.
{"title":"Analog Front-End Circuit Techniques for Wearable ExG, BioZ, and PPG Signal Acquisition: A Review","authors":"Jiawei Xu;Tianxiang Qu;Qinjing Pan;Yijie Li;Liheng Liu;Yuying Li;Jianhong Zhou;Chang Yao;Zhiliang Hong","doi":"10.1109/OJSSCS.2025.3610583","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610583","url":null,"abstract":"Wearable platforms that concurrently acquire multiple physiological signals enable comprehensive health monitoring but impose stringent requirements on front-end circuit design. The reliable extraction of low-amplitude and low-frequency biosignals is hindered by electrode offset, noise, motion artifacts, and environmental interference. Recent efforts have advanced analog front ends (AFEs) for biopotential (ExG), bioimpedance (BioZ), and photoplethysmography (PPG) sensing, with emphasis on optimizing key metrics such as noise efficiency, input impedance, dynamic range, CMRR, and power consumption. In addition, digitally-assisted calibration and direct-digitization schemes have emerged as alternative design directions, offering enhanced robustness and scalability while introducing tradeoffs in complexity and energy efficiency. This review surveys these circuit techniques, analyzes their design tradeoffs, and outlines future opportunities for next-generation wearable biomedical interfaces.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"251-268"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-03DOI: 10.1109/OJSSCS.2025.3605558
Zuoguo Wu;Jong-Ru Guo
The Universal Chiplet Interconnect Express (UCIe) standard, developed with significant contributions from the authors, has emerged as a key solution for chiplet-based architectures, offering enhanced scalability, efficiency, and performance. This article presents an analysis of UCIe electrical links operating at data rates of 48 and 64 GT/s. Leveraging our experience in the UCIe standard since its inception, we explore the technical advancements that enable these data rates, including improvements in signal integrity and power efficiency. The analysis provided in this article served as critical data inputs for the UCIe consortium, leading to the subsequent evolution of the standard. We examine link performance and reliability through detailed modeling of failure probability distributions, highlighting the challenges and solutions associated with error management and fault tolerance. Design considerations for extending UCIe data rates are discussed, along with future directions for the standard.
{"title":"Analysis of UCIe 48/64-GT/s Electrical Links","authors":"Zuoguo Wu;Jong-Ru Guo","doi":"10.1109/OJSSCS.2025.3605558","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3605558","url":null,"abstract":"The Universal Chiplet Interconnect Express (UCIe) standard, developed with significant contributions from the authors, has emerged as a key solution for chiplet-based architectures, offering enhanced scalability, efficiency, and performance. This article presents an analysis of UCIe electrical links operating at data rates of 48 and 64 GT/s. Leveraging our experience in the UCIe standard since its inception, we explore the technical advancements that enable these data rates, including improvements in signal integrity and power efficiency. The analysis provided in this article served as critical data inputs for the UCIe consortium, leading to the subsequent evolution of the standard. We examine link performance and reliability through detailed modeling of failure probability distributions, highlighting the challenges and solutions associated with error management and fault tolerance. Design considerations for extending UCIe data rates are discussed, along with future directions for the standard.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"401-409"},"PeriodicalIF":3.2,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11150380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-${mathrm { mm}}^{2}$ core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of $4.925~mu $ s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K ($85~^{circ }$ C) to 4.2 K (–$269~^{circ }$ C).
{"title":"A 0.45-mm² 3.49-TOPS/W Cryogenic Deep Reinforcement Learning Module for End-to-End Integrated Circuits Control","authors":"Jiachen Xu;John Kan;Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3601153","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3601153","url":null,"abstract":"This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-<inline-formula> <tex-math>${mathrm { mm}}^{2}$ </tex-math></inline-formula> core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of <inline-formula> <tex-math>$4.925~mu $ </tex-math></inline-formula>s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (<inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C) to 4.2 K (–<inline-formula> <tex-math>$269~^{circ }$ </tex-math></inline-formula>C).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"240-250"},"PeriodicalIF":3.2,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/OJSSCS.2025.3597907
Sumit Pratap Singh;Mostafa Jafari Nokandi;Timo Rahkonen;Marko E. Leinonen;Aarno Pärssinen
This work presents a sliding-IF mixer-first IQ receiver front-end, in 130 nm SiGe BiCMOS technology with ${f_{t}}/{f_{mathrm { max}}}$ of 300 GHz/450 GHz, operating in 300 GHz band. For near-$f_{mathrm { max}}$ operation, the sliding-IF architecture eliminates the need for the local oscillator (LO) frequency to be the same as the carrier frequency. Consequently, the power consumption of the LO chain is significantly reduced with carefully optimized multiplier chain. Signal amplification is performed at the IF stage. LO frequency at two thirds and one third of the carrier frequency is generated, from an external 50 GHz LO signal using on-chip frequency doublers for RF and I/Q mixers, respectively. The receiver provides 15.2 dB of conversion gain, input-referred compression point of –17 dBm and single sideband noise figure of 29.5 dB at 310 GHz. The 3-dB RF and BB bandwidths are measured to be 26 GHz and 10 GHz, respectively. Despite operating at 0.69x$f_{mathrm { max}}$ , the receiver front-end operates with 16-quadrature amplitude modulation (QAM) modulation with 4 GHz, 64-QAM with 2 GHz and 256-QAM with 0.5 GHz wide modulated signal centered at low-baseband frequency with 8.2%, 5.5%, and 2.7% error vector magnitude (EVM), respectively. In low gain mode, the receiver offers a 10 dB improvement in the dynamic range with a 30% reduction in power consumption in the signal chain, which makes it one of the most energy efficient receiver front-ends in its class.
{"title":"A 300-GHz Band Sliding-IF I/Q Receiver Front-End in 130-nm SiGe Technology","authors":"Sumit Pratap Singh;Mostafa Jafari Nokandi;Timo Rahkonen;Marko E. Leinonen;Aarno Pärssinen","doi":"10.1109/OJSSCS.2025.3597907","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3597907","url":null,"abstract":"This work presents a sliding-IF mixer-first IQ receiver front-end, in 130 nm SiGe BiCMOS technology with <inline-formula> <tex-math>${f_{t}}/{f_{mathrm { max}}}$ </tex-math></inline-formula> of 300 GHz/450 GHz, operating in 300 GHz band. For near-<inline-formula> <tex-math>$f_{mathrm { max}}$ </tex-math></inline-formula> operation, the sliding-IF architecture eliminates the need for the local oscillator (LO) frequency to be the same as the carrier frequency. Consequently, the power consumption of the LO chain is significantly reduced with carefully optimized multiplier chain. Signal amplification is performed at the IF stage. LO frequency at two thirds and one third of the carrier frequency is generated, from an external 50 GHz LO signal using on-chip frequency doublers for RF and I/Q mixers, respectively. The receiver provides 15.2 dB of conversion gain, input-referred compression point of –17 dBm and single sideband noise figure of 29.5 dB at 310 GHz. The 3-dB RF and BB bandwidths are measured to be 26 GHz and 10 GHz, respectively. Despite operating at 0.69x<inline-formula> <tex-math>$f_{mathrm { max}}$ </tex-math></inline-formula>, the receiver front-end operates with 16-quadrature amplitude modulation (QAM) modulation with 4 GHz, 64-QAM with 2 GHz and 256-QAM with 0.5 GHz wide modulated signal centered at low-baseband frequency with 8.2%, 5.5%, and 2.7% error vector magnitude (EVM), respectively. In low gain mode, the receiver offers a 10 dB improvement in the dynamic range with a 30% reduction in power consumption in the signal chain, which makes it one of the most energy efficient receiver front-ends in its class.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"284-294"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11122561","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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