Pub Date : 2024-10-30DOI: 10.1109/OJSSCS.2024.3488654
Henry Park;Mohammed Abdullatif;Ehung Chen;Tamer Ali
As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.
{"title":"112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems","authors":"Henry Park;Mohammed Abdullatif;Ehung Chen;Tamer Ali","doi":"10.1109/OJSSCS.2024.3488654","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3488654","url":null,"abstract":"As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"277-289"},"PeriodicalIF":0.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738450","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.
无线频谱是一种共享资源。发射机只能在其分配的频率范围内发射，而不能在其他频率上发射。发射机并非十全十美，因此有规定限制预定发射频率以外的发射能量。在本文中，我们将概述 5G FR2 的发射掩模要求，以及造成不必要发射的主要因素。然后，我们将介绍一些关键的无线电架构和电路设计注意事项，以帮助满足这些发射要求。由于本地振荡器 (LO) 漏电杂散是最严重的问题之一，我们还在上混频器中引入了 LO 消除技术。我们引入了两个执行器电路来控制上混频器输出端的两个独立 LO 信号，一个是从直流到 LO 的上变频信号，另一个是从 2 LO 到 LO 的下变频信号。这两个独立的 LO 输出可提供二维相位和振幅控制，并可在上混频器输出端组合成一个相等且相反的 LO 信号。LO 取消后，所有候选频率的 LO 泄漏均优于-57-dBc。最后，我们对不同频率、信号电平和 60 波束转向范围内的 64 元波束转向的 LO 抑制进行了广泛的空中 (OTA) 测量验证。
{"title":"The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation","authors":"Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu","doi":"10.1109/OJSSCS.2024.3487548","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3487548","url":null,"abstract":"The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"193-211"},"PeriodicalIF":0.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10737135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142679264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/OJSSCS.2024.3476035
Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms,> $(Delta Sigma )$ quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order $Delta Sigma $ modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.
{"title":"Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation","authors":"Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3476035","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3476035","url":null,"abstract":"A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms,> <tex-math>$(Delta Sigma )$ </tex-math></inline-formula>\u0000 quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"226-237"},"PeriodicalIF":0.0,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10707313","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/OJSSCS.2024.3472000
Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.
SAR ADC 具有功耗低、硬件结构紧凑等显著优势，因此在按比例 CMOS 技术中尤其具有吸引力，备受关注。SAR ADC 在转换后会在电容数模转换器 (CDAC) 上留下残留物，因此无需复杂的残留物提取电路。这一关键特性激发了众多 SAR 辅助架构的变化，并被应用于从高分辨率到高速度的一系列应用中。本文介绍了几种将 SAR ADC 作为子模块的高能效混合 ADC 架构，包括以下几种：SAR 辅助亚量程 SAR，可节省 DAC 开关电源，并能检测时间交错 ADC 的偏斜误差；SAR-闪存混合，可实现高能效高速转换；SAR 辅助双残差流水线 ADC，可消除对残差增益精度的严格要求；以及 SAR 辅助三角积分调制器 (DSM)，具有数域噪声耦合功能，可减少所需的模拟积分器数量。
{"title":"SAR-Assisted Energy-Efficient Hybrid ADCs","authors":"Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu","doi":"10.1109/OJSSCS.2024.3472000","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3472000","url":null,"abstract":"The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"163-175"},"PeriodicalIF":0.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702510","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/OJSSCS.2024.3469109
Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi
A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.
{"title":"Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth","authors":"Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi","doi":"10.1109/OJSSCS.2024.3469109","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3469109","url":null,"abstract":"A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"147-162"},"PeriodicalIF":0.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-20DOI: 10.1109/OJSSCS.2024.3464551
Yuncheng Zhang;Dingxin Xu;Kenichi Okada
This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.
{"title":"Digital Phase-Locked Loops: Exploring Different Boundaries","authors":"Yuncheng Zhang;Dingxin Xu;Kenichi Okada","doi":"10.1109/OJSSCS.2024.3464551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3464551","url":null,"abstract":"This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"176-192"},"PeriodicalIF":0.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.1109/OJSSCS.2024.3458900
Joo-Hyung Chae
Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.
{"title":"High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects","authors":"Joo-Hyung Chae","doi":"10.1109/OJSSCS.2024.3458900","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3458900","url":null,"abstract":"Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"252-264"},"PeriodicalIF":0.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10677348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/OJSSCS.2024.3455269
Pingda Guan;Haikun Jia;Wei Deng;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi
The rapidly advancing field of millimeter-wave (mm-wave) radio-frequency integrated circuit (RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on-chip passive devices. Among them, 8-shaped inductors have emerged as a novel and promising variant, attracting significant research interest thanks to their unique geometry and electromagnetic (EM) properties. The distinctive feature of 8-shaped inductors lies in their antiparallel magnetic fields due to the opposing current flows within the two turns, enabling manifold applications. In this article, we comprehensively explore the 8-shaped inductors with a focus on their diverse utilizations, including EM interference (EMI) reduction, compactness of RF layout, provision for a magnetic feedforward/feedback arrangement, and oscillation mode manipulation, thereby demonstrating that the 8-shaped inductor can be an essential addition to RFIC designers’ toolbox.
{"title":"8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox","authors":"Pingda Guan;Haikun Jia;Wei Deng;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/OJSSCS.2024.3455269","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3455269","url":null,"abstract":"The rapidly advancing field of millimeter-wave (mm-wave) radio-frequency integrated circuit (RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on-chip passive devices. Among them, 8-shaped inductors have emerged as a novel and promising variant, attracting significant research interest thanks to their unique geometry and electromagnetic (EM) properties. The distinctive feature of 8-shaped inductors lies in their antiparallel magnetic fields due to the opposing current flows within the two turns, enabling manifold applications. In this article, we comprehensively explore the 8-shaped inductors with a focus on their diverse utilizations, including EM interference (EMI) reduction, compactness of RF layout, provision for a magnetic feedforward/feedback arrangement, and oscillation mode manipulation, thereby demonstrating that the 8-shaped inductor can be an essential addition to RFIC designers’ toolbox.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"131-146"},"PeriodicalIF":0.0,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668829","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142323057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/OJSSCS.2024.3453777
Sungwon Kwon;Minjae Jung;Byung-Wook Min
In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was $11.6pm 0$ .8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was $11.9pm 1$ .1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.
{"title":"Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band","authors":"Sungwon Kwon;Minjae Jung;Byung-Wook Min","doi":"10.1109/OJSSCS.2024.3453777","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3453777","url":null,"abstract":"In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.6pm 0$ </tex-math></inline-formula>\u0000.8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.9pm 1$ </tex-math></inline-formula>\u0000.1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"122-130"},"PeriodicalIF":0.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/OJSSCS.2024.3451401
Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen
The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.
{"title":"Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations","authors":"Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2024.3451401","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3451401","url":null,"abstract":"The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"83-96"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10660491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142235709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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