Pub Date : 2024-08-26DOI: 10.1109/OJSSCS.2024.3450410
Michael Peter Kennedy;Xu Lu;Xu Wang
A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.
由于小数 N 频率合成器的输出频率不是其参考频率的整数倍，因此它本身就会产生脉冲。直到最近，人们似乎还能理解并控制分数脉冲。然而，随着人们对频率合成器的性能要求越来越高，新的脉冲产生机制和现象也不断被报道出来。因此，人们开始了紧张的研究工作，以了解造成这些问题的原因，并开发出缓解这些问题的方法。本文回顾了已知的情况，重点介绍了在理解和缓解技术方面的一些最新进展，并指出了数字密集型架构面临的新挑战。文章只关注架构中固有的（而不是由于耦合或封装问题造成的）、因此适合架构解决方案的刺激机制。
{"title":"Insights Into Architectural Spurs in High-Performance Fractional-N Frequency Synthesizers","authors":"Michael Peter Kennedy;Xu Lu;Xu Wang","doi":"10.1109/OJSSCS.2024.3450410","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3450410","url":null,"abstract":"A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"238-251"},"PeriodicalIF":0.0,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10648812","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at $85~{^{circ }}$ C. Based on several MAC operations, the estimated $512times 512$ matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.
{"title":"A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking","authors":"Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti","doi":"10.1109/OJSSCS.2024.3432468","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3432468","url":null,"abstract":"This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at \u0000<inline-formula> <tex-math>$85~{^{circ }}$ </tex-math></inline-formula>\u0000C. Based on several MAC operations, the estimated \u0000<inline-formula> <tex-math>$512times 512$ </tex-math></inline-formula>\u0000 matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"69-82"},"PeriodicalIF":0.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequence estimation parameters, for a given channel and within a given set of constraints as dictated by the application requirements so as to minimize the link’s bit error rate. The modulation can be any of the PAM signaling schemes, such as NRZ or 4-PAM. To this end, we first model a general link architecture in Part I, and then optimize the link parameters in Part II.
{"title":"High-Speed Wireline Links—Part I: Modeling","authors":"Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami","doi":"10.1109/OJSSCS.2024.3433324","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3433324","url":null,"abstract":"In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequence estimation parameters, for a given channel and within a given set of constraints as dictated by the application requirements so as to minimize the link’s bit error rate. The modulation can be any of the PAM signaling schemes, such as NRZ or 4-PAM. To this end, we first model a general link architecture in Part I, and then optimize the link parameters in Part II.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"97-109"},"PeriodicalIF":0.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10608184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In Part I of this article, we described the modeling of a general wireline link architecture. In this part, we provide a scheme for optimizing the link parameters and assessing its performance. The optimization process involves many parameters with constraints coming from application and implementation requirements. A brute-force approach to optimization can take a prohibitively long time and may not provide sufficient insight into the design iteration. To address this challenge, we divide the optimization process into specifying fixed parameters, calculating select parameters, and sweeping the rest. We then perform a link performance assessment to determine metrics typically used in wireline systems.
{"title":"High-Speed Wireline Links—Part II: Optimization and Performance Assessment","authors":"Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami","doi":"10.1109/OJSSCS.2024.3421868","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3421868","url":null,"abstract":"In Part I of this article, we described the modeling of a general wireline link architecture. In this part, we provide a scheme for optimizing the link parameters and assessing its performance. The optimization process involves many parameters with constraints coming from application and implementation requirements. A brute-force approach to optimization can take a prohibitively long time and may not provide sufficient insight into the design iteration. To address this challenge, we divide the optimization process into specifying fixed parameters, calculating select parameters, and sweeping the rest. We then perform a link performance assessment to determine metrics typically used in wireline systems.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"110-121"},"PeriodicalIF":0.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/OJSSCS.2024.3416893
Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier
This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low- $V_{t}$ and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.
{"title":"A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized Q-Boosted LNA","authors":"Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier","doi":"10.1109/OJSSCS.2024.3416893","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3416893","url":null,"abstract":"This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low-\u0000<inline-formula> <tex-math>$V_{t}$ </tex-math></inline-formula>\u0000 and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"57-68"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10564201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-10DOI: 10.1109/OJSSCS.2024.3387388
Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2– $171~mu $ A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.
{"title":"A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL","authors":"Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers","doi":"10.1109/OJSSCS.2024.3387388","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3387388","url":null,"abstract":"This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–\u0000<inline-formula> <tex-math>$171~mu $ </tex-math></inline-formula>\u0000A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"43-56"},"PeriodicalIF":0.0,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496457","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140902616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-04DOI: 10.1109/OJSSCS.2023.3346008
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2023.3346008","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3346008","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10381509","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139109689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-22DOI: 10.1109/OJSSCS.2023.3346150
{"title":"IEEE Open Journal of the Solid-State Circuits Society Information for Authors","authors":"","doi":"10.1109/OJSSCS.2023.3346150","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3346150","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"C3-C4"},"PeriodicalIF":0.0,"publicationDate":"2023-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10371322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The computing-in-memory (CIM) technique is emerging with the evolvement of big data and artificial intelligence (AI) application. The manuscript presents a systematic review of existing CIM works in a bottom-up view from circuit to application. Various types of CIM circuits based on different volatile/nonvolatile devices are introduced. The micro CIM architectures are illustrated to support multibit precision computation. After that, several types of processor-level CIM chips are analyzed to reveal the system architecture design considerations. The corresponding CIM tool chains and applications beyond AI applications are also introduced. From circuit to application levels, this manuscript analyzes the design tradeoffs, remained challenges, and possible future design trends at different design hierarchies of CIM processors.
{"title":"A Survey of Computing-in-Memory Processor: From Circuit to Application","authors":"Wenyu Sun;Jinshan Yue;Yifan He;Zongle Huang;Jingyu Wang;Wenbin Jia;Yaolei Li;Luchang Lei;Hongyang Jia;Yongpan Liu","doi":"10.1109/OJSSCS.2023.3328290","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3328290","url":null,"abstract":"The computing-in-memory (CIM) technique is emerging with the evolvement of big data and artificial intelligence (AI) application. The manuscript presents a systematic review of existing CIM works in a bottom-up view from circuit to application. Various types of CIM circuits based on different volatile/nonvolatile devices are introduced. The micro CIM architectures are illustrated to support multibit precision computation. After that, several types of processor-level CIM chips are analyzed to reveal the system architecture design considerations. The corresponding CIM tool chains and applications beyond AI applications are also introduced. From circuit to application levels, this manuscript analyzes the design tradeoffs, remained challenges, and possible future design trends at different design hierarchies of CIM processors.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"25-42"},"PeriodicalIF":0.0,"publicationDate":"2023-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10371329","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-21DOI: 10.1109/OJSSCS.2023.3338431
Patrick P. Mercier;Steven M. Bowers
Radios are everywhere. They allow us to watch terrestrial TV broadcasts, connect our cars to satellite-based navigation systems, and connect our computers, phones, and other smart devices to the Internet. As the Internet of Things continues to proliferate, radios will start to connect food packaging, pets, environmental monitors, and all sorts of other things to the Internet as well. A large percentage of these emerging applications will operate on either very small batteries or small energy harvesters, and thus must support all application requirements on very tight power budgets. Since radios often dominate the power consumption of low-power sensing nodes, anything we can do to help reduce the power consumption of wireless communications will help enable these new applications. Of course, this should be accomplished thoughtfully, with careful consideration of coexistence, standards, regulations, security, privacy, and other application-level constraints.
{"title":"Editorial OJ-SSCS Special Issue on Low-Power RF Circuits and Systems","authors":"Patrick P. Mercier;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3338431","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3338431","url":null,"abstract":"Radios are everywhere. They allow us to watch terrestrial TV broadcasts, connect our cars to satellite-based navigation systems, and connect our computers, phones, and other smart devices to the Internet. As the Internet of Things continues to proliferate, radios will start to connect food packaging, pets, environmental monitors, and all sorts of other things to the Internet as well. A large percentage of these emerging applications will operate on either very small batteries or small energy harvesters, and thus must support all application requirements on very tight power budgets. Since radios often dominate the power consumption of low-power sensing nodes, anything we can do to help reduce the power consumption of wireless communications will help enable these new applications. Of course, this should be accomplished thoughtfully, with careful consideration of coexistence, standards, regulations, security, privacy, and other application-level constraints.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"223-224"},"PeriodicalIF":0.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10368310","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：