Pub Date : 2023-09-29DOI: 10.1109/OJSSCS.2023.3317817
Lucien J. Breems;Muhammed Bolatkale;Qilong Liu;Pierluigi Cenci
This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.
{"title":"High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers","authors":"Lucien J. Breems;Muhammed Bolatkale;Qilong Liu;Pierluigi Cenci","doi":"10.1109/OJSSCS.2023.3317817","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3317817","url":null,"abstract":"This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"174-184"},"PeriodicalIF":0.0,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10268251","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134794993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, wireless power transfer (WPT) has become a widespread method for charging and powering devices, including but not limited to consumer electronics, industrial applications, electric vehicles, medical devices, and sensor nodes. This article provides an overview of the available WPT technologies, focusing on the near-field case, and highlights the main architecture and circuit-level challenges encountered in the implementation of magnetic-based near-field WPT systems while reviewing the proposed solutions in the literature, in order to identify the main research interests as well as the trends for the future.
{"title":"Recent Trends and Challenges in Near-Field Wireless Power Transfer Systems","authors":"Elisabetta Moisello;Alessandro Liotta;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/OJSSCS.2023.3313575","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3313575","url":null,"abstract":"In recent years, wireless power transfer (WPT) has become a widespread method for charging and powering devices, including but not limited to consumer electronics, industrial applications, electric vehicles, medical devices, and sensor nodes. This article provides an overview of the available WPT technologies, focusing on the near-field case, and highlights the main architecture and circuit-level challenges encountered in the implementation of magnetic-based near-field WPT systems while reviewing the proposed solutions in the literature, in order to identify the main research interests as well as the trends for the future.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"197-213"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246316","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134795090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-11DOI: 10.1109/OJSSCS.2023.3313579
Hajime Shibata
The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide- bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT $Delta Sigma $ ADCs, such as inherent anti-aliasing, while achieving the wide- BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.
{"title":"Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion","authors":"Hajime Shibata","doi":"10.1109/OJSSCS.2023.3313579","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3313579","url":null,"abstract":"The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide- bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 ADCs, such as inherent anti-aliasing, while achieving the wide- BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"162-173"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10246305.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-11DOI: 10.1109/OJSSCS.2023.3308530
Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier
This article introduces a dual-mode backscatter integrated circuit that supports both WiFi and Bluetooth low-energy (BLE) transmissions. It enables a multiantenna WiFi mode with reconfigurable beam steering of single-sideband (SSB) quadrature phase shift-keying (QPSK) signals, while also facilitating omnidirectional SSB BLE-to-BLE backscatter communication. To achieve beam steering, two techniques are proposed: 1) a transmission-line-less fully reflective SP4T backscatter switch is employed to minimize power loss and maximize the communication range and 2) a multiantenna array is constructed using the aforementioned SP4T switches together with a baseband phase-shifting technique to reradiate the incident WiFi signal with a controllable angle of direction. The chip implementation is based on a 65-nm CMOS process and operates at a power consumption of $5.5 mu text{W}$ in standby mode. In backscattering mode, it consumes $39 mu text{W}$ for the single-antenna approach and $88 mu text{W}$ for the multiantenna approach. The proposed design achieves a worst-case access point (AP)-to-AP range of 35 and 56 m for the single-antenna and multiantenna approaches, respectively.
本文介绍了一种同时支持 WiFi 和低能耗蓝牙 (BLE) 传输的双模反向散射集成电路。它实现了多天线 WiFi 模式，可对单边带（SSB）正交相移键控（QPSK）信号进行可重新配置的波束转向，同时还促进了全向 SSB BLE 到 BLE 的反向散射通信。为实现波束转向，提出了两种技术：1）采用无传输线的全反射 SP4T 后向散射开关，以最大限度地减少功率损耗并最大限度地扩大通信范围；2）使用上述 SP4T 开关和基带移相技术构建多天线阵列，以可控的方向角重新散射入射 WiFi 信号。芯片基于 65 纳米 CMOS 工艺实现，待机模式下的功耗为 5.5 mu text{W}$。在反向散射模式下，单天线方法的功耗为 39 mu text{W}$，多天线方法的功耗为 88 mu text{W}$。在最坏情况下，单天线和多天线方法的接入点（AP）到接入点（AP）的距离分别为 35 米和 56 米。
{"title":"A WiFi and Bluetooth Low-Energy Backscatter Combo Chip With Beam Steering Capabilities","authors":"Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier","doi":"10.1109/OJSSCS.2023.3308530","DOIUrl":"10.1109/OJSSCS.2023.3308530","url":null,"abstract":"This article introduces a dual-mode backscatter integrated circuit that supports both WiFi and Bluetooth low-energy (BLE) transmissions. It enables a multiantenna WiFi mode with reconfigurable beam steering of single-sideband (SSB) quadrature phase shift-keying (QPSK) signals, while also facilitating omnidirectional SSB BLE-to-BLE backscatter communication. To achieve beam steering, two techniques are proposed: 1) a transmission-line-less fully reflective SP4T backscatter switch is employed to minimize power loss and maximize the communication range and 2) a multiantenna array is constructed using the aforementioned SP4T switches together with a baseband phase-shifting technique to reradiate the incident WiFi signal with a controllable angle of direction. The chip implementation is based on a 65-nm CMOS process and operates at a power consumption of \u0000<inline-formula> <tex-math>$5.5 mu text{W}$ </tex-math></inline-formula>\u0000 in standby mode. In backscattering mode, it consumes \u0000<inline-formula> <tex-math>$39 mu text{W}$ </tex-math></inline-formula>\u0000 for the single-antenna approach and \u0000<inline-formula> <tex-math>$88 mu text{W}$ </tex-math></inline-formula>\u0000 for the multiantenna approach. The proposed design achieves a worst-case access point (AP)-to-AP range of 35 and 56 m for the single-antenna and multiantenna approaches, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"239-248"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-08DOI: 10.1109/OJSSCS.2023.3311418
Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae
The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.
{"title":"Design Techniques for Energy-Efficient Analog-to-Digital Converters","authors":"Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae","doi":"10.1109/OJSSCS.2023.3311418","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3311418","url":null,"abstract":"The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"145-161"},"PeriodicalIF":0.0,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10246164.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-06DOI: 10.1109/OJSSCS.2023.3312354
Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai
A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of $3.8 ~mu text{W}$ at 250 kHz and the normalized energy efficiency is $2.79times $ higher than state of the art.
{"title":"A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks","authors":"Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai","doi":"10.1109/OJSSCS.2023.3312354","DOIUrl":"10.1109/OJSSCS.2023.3312354","url":null,"abstract":"A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of \u0000<inline-formula> <tex-math>$3.8 ~mu text{W}$ </tex-math></inline-formula>\u0000 at 250 kHz and the normalized energy efficiency is \u0000<inline-formula> <tex-math>$2.79times $ </tex-math></inline-formula>\u0000 higher than state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"185-196"},"PeriodicalIF":0.0,"publicationDate":"2023-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10242041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79901424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-11DOI: 10.1109/OJSSCS.2023.3304599
Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang
This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and $1.2times /1.4times $ power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).
{"title":"A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network","authors":"Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang","doi":"10.1109/OJSSCS.2023.3304599","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3304599","url":null,"abstract":"This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and \u0000<inline-formula> <tex-math>$1.2times /1.4times $ </tex-math></inline-formula>\u0000 power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"134-144"},"PeriodicalIF":0.0,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10214532.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-06DOI: 10.1109/OJSSCS.2023.3281904
Jerald Yoo
Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.
{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics","authors":"Jerald Yoo","doi":"10.1109/OJSSCS.2023.3281904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3281904","url":null,"abstract":"Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"63-64"},"PeriodicalIF":0.0,"publicationDate":"2023-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10174830.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-28DOI: 10.1109/OJSSCS.2023.3290550
Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers
This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power $(P_{mathrm{ out}})$ and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a $1.76times $ and $1.93times $ improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average $P_{mathrm{ out}}$ of 14 dBm with an r.m.s. error vector magnitude $({mathrm{ EVM}}_{mathrm{ rms}})$ of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.
{"title":"A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network","authors":"Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3290550","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290550","url":null,"abstract":"This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power \u0000<inline-formula> <tex-math>$(P_{mathrm{ out}})$ </tex-math></inline-formula>\u0000 and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a \u0000<inline-formula> <tex-math>$1.76times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.93times $ </tex-math></inline-formula>\u0000 improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average \u0000<inline-formula> <tex-math>$P_{mathrm{ out}}$ </tex-math></inline-formula>\u0000 of 14 dBm with an r.m.s. error vector magnitude \u0000<inline-formula> <tex-math>$({mathrm{ EVM}}_{mathrm{ rms}})$ </tex-math></inline-formula>\u0000 of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"103-117"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167796.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-28DOI: 10.1109/OJSSCS.2023.3290551
Behzad Razavi
Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.
{"title":"Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2023.3290551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290551","url":null,"abstract":"Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"118-133"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167779.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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