Pub Date : 2021-09-17DOI: 10.1109/OJSSCS.2021.3113264
Aroutin Khachaturian;Reza Fatemi;Ali Hajimiri
Silicon photonics (SiP) integrated coherent image sensors offer higher sensitivity and improved range-resolution-product compared to direct detection image sensors such as CCD and CMOS devices. Previous generations of SiP coherent imagers suffer from relative optical phase fluctuations between the signal and reference paths, which results in random phase and amplitude fluctuations in the output signal. This limitation negatively impacts the SNR and signal acquisition times. Here, we present a coherent imager system that suppresses the optical carrier signal and removes non-idealities from the relative optical path using a photonic in-phase (I) and quadrature (Q) receiver via a 90° hybrid detector. Furthermore, we incorporate row-column read-out and row-column addressing schemes to address the electro-optical interconnect density challenge. Our novel row-column read-out architecture for the sensor array requires only $2N$ interconnects for N 2 sensors. An $8times 8$ IQ sensor array is presented as a proof-of-concept demonstration with $1.2times 10^{-5}$ resolution over range accuracy. Free-space FMCW ranging with $250 mu text {m}$ resolution at 1 m distance has been demonstrated using this sensor array.
{"title":"IQ Photonic Receiver for Coherent Imaging With a Scalable Aperture","authors":"Aroutin Khachaturian;Reza Fatemi;Ali Hajimiri","doi":"10.1109/OJSSCS.2021.3113264","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3113264","url":null,"abstract":"Silicon photonics (SiP) integrated coherent image sensors offer higher sensitivity and improved range-resolution-product compared to direct detection image sensors such as CCD and CMOS devices. Previous generations of SiP coherent imagers suffer from relative optical phase fluctuations between the signal and reference paths, which results in random phase and amplitude fluctuations in the output signal. This limitation negatively impacts the SNR and signal acquisition times. Here, we present a coherent imager system that suppresses the optical carrier signal and removes non-idealities from the relative optical path using a photonic in-phase (I) and quadrature (Q) receiver via a 90° hybrid detector. Furthermore, we incorporate row-column read-out and row-column addressing schemes to address the electro-optical interconnect density challenge. Our novel row-column read-out architecture for the sensor array requires only \u0000<inline-formula> <tex-math>$2N$ </tex-math></inline-formula>\u0000 interconnects for \u0000<italic>N</i>\u0000<sup>2</sup>\u0000 sensors. An \u0000<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula>\u0000 IQ sensor array is presented as a proof-of-concept demonstration with \u0000<inline-formula> <tex-math>$1.2times 10^{-5}$ </tex-math></inline-formula>\u0000 resolution over range accuracy. Free-space FMCW ranging with \u0000<inline-formula> <tex-math>$250 mu text {m}$ </tex-math></inline-formula>\u0000 resolution at 1 m distance has been demonstrated using this sensor array.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"263-270"},"PeriodicalIF":0.0,"publicationDate":"2021-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09540747.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67862739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-14DOI: 10.1109/OJSSCS.2021.3112398
Behzad Razavi
Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV $_{pp}$ with a clock jitter of 205 fs $_{rms}$ while drawing 44 mW.
{"title":"Design Techniques for High-Speed Wireline Transmitters","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2021.3112398","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3112398","url":null,"abstract":"Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV\u0000<inline-formula> <tex-math>$_{pp}$ </tex-math></inline-formula>\u0000 with a clock jitter of 205 fs\u0000<inline-formula> <tex-math>$_{rms}$ </tex-math></inline-formula>\u0000 while drawing 44 mW.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"53-66"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09536949.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/OJSSCS.2021.3110748
Payam Heydari
This paper presents challenges and design perspectives for terahertz (THz) integrated circuits and systems. THz means different things to different people. From International Telecommunication Union (ITU) perspective, THz radiation primarily means frequency range from 300 – 3000 GHz. However, recently, a more expansive definition of THz has emerged that covers frequencies from 100 GHz to 10 THz, which includes sub-THz (100 – 300 GHz), ITU-defined THz frequencies. This definition is now commonly used by communication theorists, and since this paper is intended for people with a wide variety of expertise in system and circuit design, we have adopted the latter definition. The paper brings to the open unmitigated shortcomings of conventional transceiver architectures for multi gigabit-per-second wireless applications, unfolds challenges in designing THz transceivers, and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.
{"title":"Terahertz Integrated Circuits and Systems for High-Speed Wireless Communications: Challenges and Design Perspectives","authors":"Payam Heydari","doi":"10.1109/OJSSCS.2021.3110748","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3110748","url":null,"abstract":"This paper presents challenges and design perspectives for terahertz (THz) integrated circuits and systems. THz means different things to different people. From International Telecommunication Union (ITU) perspective, THz radiation primarily means frequency range from 300 – 3000 GHz. However, recently, a more expansive definition of THz has emerged that covers frequencies from 100 GHz to 10 THz, which includes sub-THz (100 – 300 GHz), ITU-defined THz frequencies. This definition is now commonly used by communication theorists, and since this paper is intended for people with a wide variety of expertise in system and circuit design, we have adopted the latter definition. The paper brings to the open unmitigated shortcomings of conventional transceiver architectures for multi gigabit-per-second wireless applications, unfolds challenges in designing THz transceivers, and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"18-36"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09530765.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-07DOI: 10.1109/OJSSCS.2021.3110943
Andrea Zazzi;Juliana Müller;Maxim Weizel;Jonas Koch;Dengyang Fang;Alvaro Moscoso-Mártir;Ali Tabatabaei Mashayekh;Arka D. Das;Daniel Drayß;Florian Merget;Franz X. Kärtner;Stephan Pachnicke;Christian Koos;J. Christoph Scheytt;Jeremy Witzens
Electrical-optical signal processing has been shown to be a promising path to overcome the limitations of state-of-the-art all-electrical data converters. In addition to ultra-broadband signal processing, it allows leveraging ultra-low jitter mode-locked lasers and thus increasing the aperture jitter limited effective number of bits at high analog signal frequencies. In this paper, we review our recent progress towards optically enabled time- and frequency-interleaved analog-to-digital converters, as well as their monolithic integration in electronic-photonic integrated circuits. For signal frequencies up to 65 GHz, an optoelectronic track-and-hold amplifier based on the source-emitter-follower architecture is shown as a power efficient approach in optically enabled BiCMOS technology. At higher signal frequencies, integrated photonic filters enable signal slicing in the frequency domain and further scaling of the conversion bandwidth, with the reconstruction of a 140 GHz optical signal being shown. We further show how such optically enabled data converter architectures can be applied to a nonlinear Fourier transform based integrated transceiver in particular and discuss their applicability to broadband optical links in general.
{"title":"Optically Enabled ADCs and Application to Optical Communications","authors":"Andrea Zazzi;Juliana Müller;Maxim Weizel;Jonas Koch;Dengyang Fang;Alvaro Moscoso-Mártir;Ali Tabatabaei Mashayekh;Arka D. Das;Daniel Drayß;Florian Merget;Franz X. Kärtner;Stephan Pachnicke;Christian Koos;J. Christoph Scheytt;Jeremy Witzens","doi":"10.1109/OJSSCS.2021.3110943","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3110943","url":null,"abstract":"Electrical-optical signal processing has been shown to be a promising path to overcome the limitations of state-of-the-art all-electrical data converters. In addition to ultra-broadband signal processing, it allows leveraging ultra-low jitter mode-locked lasers and thus increasing the aperture jitter limited effective number of bits at high analog signal frequencies. In this paper, we review our recent progress towards optically enabled time- and frequency-interleaved analog-to-digital converters, as well as their monolithic integration in electronic-photonic integrated circuits. For signal frequencies up to 65 GHz, an optoelectronic track-and-hold amplifier based on the source-emitter-follower architecture is shown as a power efficient approach in optically enabled BiCMOS technology. At higher signal frequencies, integrated photonic filters enable signal slicing in the frequency domain and further scaling of the conversion bandwidth, with the reconstruction of a 140 GHz optical signal being shown. We further show how such optically enabled data converter architectures can be applied to a nonlinear Fourier transform based integrated transceiver in particular and discuss their applicability to broadband optical links in general.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"209-221"},"PeriodicalIF":0.0,"publicationDate":"2021-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09530562.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-06DOI: 10.1109/OJSSCS.2021.3110461
Ehsan Kargaran;Danilo Manstretta;Rinaldo Castello
Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phase-tracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm 2 and consumes only $350~{mu }text{W}$ from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.
{"title":"Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things","authors":"Ehsan Kargaran;Danilo Manstretta;Rinaldo Castello","doi":"10.1109/OJSSCS.2021.3110461","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3110461","url":null,"abstract":"Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phase-tracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm\u0000<sup>2</sup>\u0000 and consumes only \u0000<inline-formula> <tex-math>$350~{mu }text{W}$ </tex-math></inline-formula>\u0000 from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"37-52"},"PeriodicalIF":0.0,"publicationDate":"2021-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09530456.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-06DOI: 10.1109/OJSSCS.2021.3109854
Pietro Andreani;Andrea Bevilacqua
The harmonic oscillator is a truly irreplaceable as well as ubiquitous analog integrated circuit. Starting from the basics of its CMOS implementation, we will discuss the phase noise of the harmonic oscillator in some detail, where the intrinsic large-signal operation mandates a time-variant analysis. This will be followed by a survey of the most popular design techniques enabling a low phase noise and a wide range of oscillation frequencies.
{"title":"Harmonic Oscillators in CMOS—A Tutorial Overview","authors":"Pietro Andreani;Andrea Bevilacqua","doi":"10.1109/OJSSCS.2021.3109854","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3109854","url":null,"abstract":"The harmonic oscillator is a truly irreplaceable as well as ubiquitous analog integrated circuit. Starting from the basics of its CMOS implementation, we will discuss the phase noise of the harmonic oscillator in some detail, where the intrinsic large-signal operation mandates a time-variant analysis. This will be followed by a survey of the most popular design techniques enabling a low phase noise and a wide range of oscillation frequencies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"2-17"},"PeriodicalIF":0.0,"publicationDate":"2021-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09530265.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1007/978-3-030-78771-4_43
Styliani Geronikolou, Ioannis Koutelekos, George Lambrou, Anna Tagka, Dennis Cokkinos, George P Chrousos
{"title":"Correction to: Adults' Stress Response to Unexpected Oral and Arithmetic Tasks in Supine Position.","authors":"Styliani Geronikolou, Ioannis Koutelekos, George Lambrou, Anna Tagka, Dennis Cokkinos, George P Chrousos","doi":"10.1007/978-3-030-78771-4_43","DOIUrl":"10.1007/978-3-030-78771-4_43","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"C1"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50979011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/OJSSCS.2022.3150526
Presents the 2021 subject/author index for this publication.
提供本出版物2021年主题/作者索引。
{"title":"2021 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 1","authors":"","doi":"10.1109/OJSSCS.2022.3150526","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3150526","url":null,"abstract":"Presents the 2021 subject/author index for this publication.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"271-276"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09709883.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67862740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/OJSSCS.2021.3120245
Describes the above-named upcoming conference event. May include topics to be covered or calls for papers.
描述上述即将举行的会议事件。可能包括要报道的主题或论文征集。
{"title":"RFIC 2022 Call for Papers","authors":"","doi":"10.1109/OJSSCS.2021.3120245","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3120245","url":null,"abstract":"Describes the above-named upcoming conference event. May include topics to be covered or calls for papers.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"277-278"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09677064.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-10DOI: 10.1109/OJSSC.2019.2949191
Provides a listing of current staff, committee members and society officers.
提供现有工作人员、委员会成员和社会官员的名单。
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSC.2019.2949191","DOIUrl":"https://doi.org/10.1109/OJSSC.2019.2949191","url":null,"abstract":"Provides a listing of current staff, committee members and society officers.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09113798.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：