Pub Date : 2021-10-13DOI: 10.1109/OJSSCS.2021.3119910
Lu Jie;Xiyuan Tang;Jiaxin Liu;Linxiao Shen;Shaolan Li;Nan Sun;Michael P. Flynn
The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines the advantages of the SAR and the DSM architectures. NS SAR shows excellent potential for high efficiency and low cost, and is highly suited to process scaling. This paper gives an overview of the history of NS-SAR, reviews the fundamentals challenges, and summarizes the latest developments, including advanced loop filtering techniques, DAC mismatch mitigation, kT/C mitigation, and bandwidth boosting. A comprehensive comparison of the state-of-the-art NS-SAR ADCs is provided, and conclusions are derived.
{"title":"An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier","authors":"Lu Jie;Xiyuan Tang;Jiaxin Liu;Linxiao Shen;Shaolan Li;Nan Sun;Michael P. Flynn","doi":"10.1109/OJSSCS.2021.3119910","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3119910","url":null,"abstract":"The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines the advantages of the SAR and the DSM architectures. NS SAR shows excellent potential for high efficiency and low cost, and is highly suited to process scaling. This paper gives an overview of the history of NS-SAR, reviews the fundamentals challenges, and summarizes the latest developments, including advanced loop filtering techniques, DAC mismatch mitigation, kT/C mitigation, and bandwidth boosting. A comprehensive comparison of the state-of-the-art NS-SAR ADCs is provided, and conclusions are derived.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"149-161"},"PeriodicalIF":0.0,"publicationDate":"2021-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09569768.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-11DOI: 10.1109/OJSSCS.2021.3118987
Sarrah M. Patanwala;Istvan Gyongy;Hanning Mai;Andreas Aßmann;Neale A. W. Dutton;Bruce R. Rae;Robert K. Henderson
There has recently been a keen interest in developing Light Detection and Ranging (LiDAR) systems using Single Photon Avalanche Diode (SPAD) sensors. This has led to a variety of implementations in pixel combining techniques and Time to Digital Converter (TDC) architectures for such sensors. This paper presents a comparison of these approaches and demonstrates a technique capable of extending the range of LiDAR systems with improved resilience to background conditions. A LiDAR system emulator using a reconfigurable SPAD array and FPGA interface is used to compare these different techniques. A Monte Carlo simulation model leveraging synthetic 3D data is presented to visualize the sensor performance on realistic automotive LiDAR scenes.
{"title":"A High-Throughput Photon Processing Technique for Range Extension of SPAD-Based LiDAR Receivers","authors":"Sarrah M. Patanwala;Istvan Gyongy;Hanning Mai;Andreas Aßmann;Neale A. W. Dutton;Bruce R. Rae;Robert K. Henderson","doi":"10.1109/OJSSCS.2021.3118987","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118987","url":null,"abstract":"There has recently been a keen interest in developing Light Detection and Ranging (LiDAR) systems using Single Photon Avalanche Diode (SPAD) sensors. This has led to a variety of implementations in pixel combining techniques and Time to Digital Converter (TDC) architectures for such sensors. This paper presents a comparison of these approaches and demonstrates a technique capable of extending the range of LiDAR systems with improved resilience to background conditions. A LiDAR system emulator using a reconfigurable SPAD array and FPGA interface is used to compare these different techniques. A Monte Carlo simulation model leveraging synthetic 3D data is presented to visualize the sensor performance on realistic automotive LiDAR scenes.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"12-25"},"PeriodicalIF":0.0,"publicationDate":"2021-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09566373.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-08DOI: 10.1109/OJSSCS.2021.3118668
Dongyang Jiang;Sai-Weng Sin;Liang Qi;Guoxing Wang;Rui P. Martins
High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range. Although widely used, noise-shaping (NS) in ADCs offers a high-resolution characteristic, but obtaining good power efficiency and compact die area is still challenging. Recent literature showed promising progress by utilizing hybrid Discrete-Time (DT) NS-ADCs with measured silicon results. This paper focuses its analysis and discussion on two important trending classes: hybrid Incremental ADCs (I-ADC) and hybrid Time-interleaved (TI) NS-ADCs. Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures.
{"title":"Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs","authors":"Dongyang Jiang;Sai-Weng Sin;Liang Qi;Guoxing Wang;Rui P. Martins","doi":"10.1109/OJSSCS.2021.3118668","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118668","url":null,"abstract":"High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range. Although widely used, noise-shaping (NS) in ADCs offers a high-resolution characteristic, but obtaining good power efficiency and compact die area is still challenging. Recent literature showed promising progress by utilizing hybrid Discrete-Time (DT) NS-ADCs with measured silicon results. This paper focuses its analysis and discussion on two important trending classes: hybrid Incremental ADCs (I-ADC) and hybrid Time-interleaved (TI) NS-ADCs. Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"129-139"},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09564255.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 240 $times$ 160 single-photon avalanche diode (SPAD) sensor integrated with a 3D-stacked 65nm/65nm CMOS technology is reported for direct time-of-flight (dToF) 3D imaging in mobile devices. The top tier is occupied by backside illuminated SPADs with 16 $mu {mathrm{ m}}$ pitch and 49.7% fill-factor. The SPADS consists of multiple 16 $times$ 16 SPADs top groups, in which each of 8 $times$ 8 SPADs sub-group shares a 10-bit, 97.65ps and 100ns range time-to-digital converter (TDC) in a quad-partition rolling shutter mode. During the exposure of each rolling stage, partial histogramming readout (PHR) approach is implemented to compress photon events to in-pixel histograms. Since the fine histograms is incomplete, for the first time we propose histogram distortion correction (HDC) algorithm to solve the linearity discontinuity at the coarse bin edges. With this algorithm, depth measurement up to 9.5m achieves an accuracy of 1cm and precision of 9mm in office lighting condition. Outdoor measurement with 10 klux sunlight achieves a maximum distance detection of 4m at 20 fps, using a VCSEL laser with the average power of 90 mW and peak power of 15 W.
{"title":"A 240 × 160 3D-Stacked SPAD dToF Image Sensor With Rolling Shutter and In-Pixel Histogram for Mobile Devices","authors":"Chao Zhang;Ning Zhang;Zhijie Ma;Letian Wang;Yu Qin;Jieyang Jia;Kai Zang","doi":"10.1109/OJSSCS.2021.3118332","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118332","url":null,"abstract":"A 240 \u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u0000 160 single-photon avalanche diode (SPAD) sensor integrated with a 3D-stacked 65nm/65nm CMOS technology is reported for direct time-of-flight (dToF) 3D imaging in mobile devices. The top tier is occupied by backside illuminated SPADs with 16 \u0000<inline-formula> <tex-math>$mu {mathrm{ m}}$ </tex-math></inline-formula>\u0000 pitch and 49.7% fill-factor. The SPADS consists of multiple 16\u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u000016 SPADs top groups, in which each of 8 \u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u0000 8 SPADs sub-group shares a 10-bit, 97.65ps and 100ns range time-to-digital converter (TDC) in a quad-partition rolling shutter mode. During the exposure of each rolling stage, partial histogramming readout (PHR) approach is implemented to compress photon events to in-pixel histograms. Since the fine histograms is incomplete, for the first time we propose histogram distortion correction (HDC) algorithm to solve the linearity discontinuity at the coarse bin edges. With this algorithm, depth measurement up to 9.5m achieves an accuracy of 1cm and precision of 9mm in office lighting condition. Outdoor measurement with 10 klux sunlight achieves a maximum distance detection of 4m at 20 fps, using a VCSEL laser with the average power of 90 mW and peak power of 15 W.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"3-11"},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09565145.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The recent pandemic has shown that accurate and on-demand information on various infections requires highly versatile, Point-of-Care (PoC) platforms providing diagnostic and prognostic multiparametric information, personalized to each patient. Despite the significant progress made over the last years in various biosensing technologies, existing solutions fail to meet the power and area requirements needed for highly scalable and portable next-generation PoC devices. This work presents a solution based on a first of its kind fully integrated electronic-photonic platform in a zero-change high volume CMOS-SOI process, tailored towards molecular and ultrasound sensing applications. Leveraging co-integration of $10mu text{m}$ micro-ring resonators (MRRs) with on-chip electronics, we address the current needs of scalability, power and area by providing nanophotonic sensing and readout processing on a monolithic electronic-photonic system-on-chip (EPSoC). This work unlocks the door towards complete and self-contained Lab-on-Chip (LoC) systems, capable of providing multiparametric biosensing information.
{"title":"Lab-on-Chip for Everyone: Introducing an Electronic-Photonic Platform for Multiparametric Biosensing Using Standard CMOS Processes","authors":"Christos Adamopoulos;Panagiotis Zarkos;Sidney Buchbinder;Pavan Bhargava;Ali Niknejad;Mekhail Anwar;Vladimir Stojanović","doi":"10.1109/OJSSCS.2021.3118336","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118336","url":null,"abstract":"The recent pandemic has shown that accurate and on-demand information on various infections requires highly versatile, Point-of-Care (PoC) platforms providing diagnostic and prognostic multiparametric information, personalized to each patient. Despite the significant progress made over the last years in various biosensing technologies, existing solutions fail to meet the power and area requirements needed for highly scalable and portable next-generation PoC devices. This work presents a solution based on a first of its kind fully integrated electronic-photonic platform in a zero-change high volume CMOS-SOI process, tailored towards molecular and ultrasound sensing applications. Leveraging co-integration of \u0000<inline-formula> <tex-math>$10mu text{m}$ </tex-math></inline-formula>\u0000 micro-ring resonators (MRRs) with on-chip electronics, we address the current needs of scalability, power and area by providing nanophotonic sensing and readout processing on a monolithic electronic-photonic system-on-chip (EPSoC). This work unlocks the door towards complete and self-contained Lab-on-Chip (LoC) systems, capable of providing multiparametric biosensing information.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"198-208"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563081.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-07DOI: 10.1109/OJSSCS.2021.3118339
Yongping Fan;Ian A. Young
The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.
{"title":"Low Power Clock Generator Design With CMOS Signaling","authors":"Yongping Fan;Ian A. Young","doi":"10.1109/OJSSCS.2021.3118339","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118339","url":null,"abstract":"The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"162-170"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563068.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-05DOI: 10.1109/OJSSCS.2021.3117930
Xunjun Mo;Jiaqi Wu;Nijwm Wary;Tony Chan Carusone
Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, it is important to understand their limitations and explore design tradeoffs. This tutorial provides quantitative analyses of the main sources of jitter in CMOS clock distribution: power supply induced jitter, jitter generation, and jitter amplification. Minimizing the number of buffers along the clock distribution network while still maintaining fast rise-fall times and ensuring proper settling of all clock waveforms will minimize the impact of all jitter sources. Following these guidelines can simultaneously reduce power supply noise sensitivity and power consumption of the clock distribution circuits. These conclusions are backed up by simulation and measurement results of two 16-nm FinFET clock distribution networks.
{"title":"Design Methodologies for Low-Jitter CMOS Clock Distribution","authors":"Xunjun Mo;Jiaqi Wu;Nijwm Wary;Tony Chan Carusone","doi":"10.1109/OJSSCS.2021.3117930","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3117930","url":null,"abstract":"Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, it is important to understand their limitations and explore design tradeoffs. This tutorial provides quantitative analyses of the main sources of jitter in CMOS clock distribution: power supply induced jitter, jitter generation, and jitter amplification. Minimizing the number of buffers along the clock distribution network while still maintaining fast rise-fall times and ensuring proper settling of all clock waveforms will minimize the impact of all jitter sources. Following these guidelines can simultaneously reduce power supply noise sensitivity and power consumption of the clock distribution circuits. These conclusions are backed up by simulation and measurement results of two 16-nm FinFET clock distribution networks.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"94-103"},"PeriodicalIF":0.0,"publicationDate":"2021-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09559395.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/OJSSCS.2021.3116920
Vincenzo Sesta;Klaus Pasquinelli;Renato Federico;Franco Zappa;Federica Villa
We present the design and experimental characterization of a CMOS sensor based on Single-Photon Avalanche Diodes for direct Time-Of-Flight single-point distance ranging, under high background illumination for short-range applications. The sensing area has a rectangular shape ( $40,,mathbf {mathrm {times }},,10$ SPADs) to deal with the backscattered light spot displacement across the detector, dependent on target distance, due to the non-confocal optical setup. Since only few SPADs are illuminated by the laser spot, we implemented a smart laser-spot tracking within the active area, so to define the specific Region-Of-Interest (ROI) with only SPADs hit by signal photons and a smart sharing of the timing electronics, so to significantly improve Signal-to-Noise Ratio (SNR) of TOF measurements and to reduce overall chip area and power consumption. The timing electronics consists of 80 Time-to-Digital Converter (TDC) shared among the 400 SPADs with a self-reconfigurable routing, which dynamically connects the SPADs within the ROI to the available TDCs. The latter have 78 ps resolution and 20 ns Full-Scale Range (FSR), i.e., up to 2 m maximum distance range. An on-chip histogram builder block accumulates TDC conversions so to provide the final TOF histogram. We achieve a precision better than 2.3 mm at 1 m distance and 80% target reflectivity, with 3 klux halogen lamp background illumination and 2 kHz measurement rate. The sensor rejects 10 klux of background light, still with a precision better than 20 mm at 2 m.
{"title":"Range-Finding SPAD Array With Smart Laser-Spot Tracking and TDC Sharing for Background Suppression","authors":"Vincenzo Sesta;Klaus Pasquinelli;Renato Federico;Franco Zappa;Federica Villa","doi":"10.1109/OJSSCS.2021.3116920","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116920","url":null,"abstract":"We present the design and experimental characterization of a CMOS sensor based on Single-Photon Avalanche Diodes for direct Time-Of-Flight single-point distance ranging, under high background illumination for short-range applications. The sensing area has a rectangular shape (\u0000<inline-formula> <tex-math>$40,,mathbf {mathrm {times }},,10$ </tex-math></inline-formula>\u0000 SPADs) to deal with the backscattered light spot displacement across the detector, dependent on target distance, due to the non-confocal optical setup. Since only few SPADs are illuminated by the laser spot, we implemented a smart laser-spot tracking within the active area, so to define the specific Region-Of-Interest (ROI) with only SPADs hit by signal photons and a smart sharing of the timing electronics, so to significantly improve Signal-to-Noise Ratio (SNR) of TOF measurements and to reduce overall chip area and power consumption. The timing electronics consists of 80 Time-to-Digital Converter (TDC) shared among the 400 SPADs with a self-reconfigurable routing, which dynamically connects the SPADs within the ROI to the available TDCs. The latter have 78 ps resolution and 20 ns Full-Scale Range (FSR), i.e., up to 2 m maximum distance range. An on-chip histogram builder block accumulates TDC conversions so to provide the final TOF histogram. We achieve a precision better than 2.3 mm at 1 m distance and 80% target reflectivity, with 3 klux halogen lamp background illumination and 2 kHz measurement rate. The sensor rejects 10 klux of background light, still with a precision better than 20 mm at 2 m.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"26-37"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09555913.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-30DOI: 10.1109/OJSSCS.2021.3116563
Kaushik Sengupta;Lingyu Hong;Chengjie Zhu;Xuyang Lu
Integration of complex optical systems operating in the visible and near-IR range (VIS/NIR), realized in a CMOS fabrication process in an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR range, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are non-integrated, bulky and expensive, severely limiting their application domains. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplexed fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can lead to a new class of millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.
{"title":"Visible and Near-IR Nano-Optical Components and Systems in CMOS","authors":"Kaushik Sengupta;Lingyu Hong;Chengjie Zhu;Xuyang Lu","doi":"10.1109/OJSSCS.2021.3116563","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116563","url":null,"abstract":"Integration of complex optical systems operating in the visible and near-IR range (VIS/NIR), realized in a CMOS fabrication process in an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR range, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are non-integrated, bulky and expensive, severely limiting their application domains. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplexed fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can lead to a new class of millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"247-262"},"PeriodicalIF":0.0,"publicationDate":"2021-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09552953.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.1109/OJSSCS.2021.3116125
Alice Lanniel;Tobias Boeser;Thomas Alpert;Maurits Ortmanns
This paper presents a charge-balanced readout circuit for MEMS capacitive accelerometers. The focus of this work is a design with a low-noise and low area consumption while ensuring the essential linearity and electromagnetic compatibility (EMC) for automotive applications. The readout circuit is composed of a charge-balanced single-ended input C/V stage followed by a second order sigma-delta modulator. The C/V stage uses a Gm stage combined with an integrator to reduce its noise contribution. The measurement results of the readout circuit show a noise floor of 62 $mu g/{sqrt {mathrm{ Hz}}}$ and a temperature dependent offset smaller than ±0.6 mg after compensation. The measured dynamic range of the complete interface, including readout circuit and sensor, is 95.5 dB. The measured EMC is below 2 mg. The accelerometer readout circuit has been designed in a 130nm technology. Its power and area consumption is 1.4 mW and 0.26mm 2 .
{"title":"Low-Noise Readout Circuit for an Automotive MEMS Accelerometer","authors":"Alice Lanniel;Tobias Boeser;Thomas Alpert;Maurits Ortmanns","doi":"10.1109/OJSSCS.2021.3116125","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116125","url":null,"abstract":"This paper presents a charge-balanced readout circuit for MEMS capacitive accelerometers. The focus of this work is a design with a low-noise and low area consumption while ensuring the essential linearity and electromagnetic compatibility (EMC) for automotive applications. The readout circuit is composed of a charge-balanced single-ended input C/V stage followed by a second order sigma-delta modulator. The C/V stage uses a Gm stage combined with an integrator to reduce its noise contribution. The measurement results of the readout circuit show a noise floor of 62\u0000<inline-formula> <tex-math>$mu g/{sqrt {mathrm{ Hz}}}$ </tex-math></inline-formula>\u0000 and a temperature dependent offset smaller than ±0.6 mg after compensation. The measured dynamic range of the complete interface, including readout circuit and sensor, is 95.5 dB. The measured EMC is below 2 mg. The accelerometer readout circuit has been designed in a 130nm technology. Its power and area consumption is 1.4 mW and 0.26mm\u0000<sup>2</sup>\u0000.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"140-148"},"PeriodicalIF":0.0,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09551692.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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