Pub Date : 2024-11-19DOI: 10.1109/OJSSCS.2024.3502315
Liping Zhong;Quan Pan
The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of < $10{^{-}10 }$ and < $10{^{-}12 }$ with a single-ended channel loss of 24 and 25 dB, respectively.
{"title":"Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s","authors":"Liping Zhong;Quan Pan","doi":"10.1109/OJSSCS.2024.3502315","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3502315","url":null,"abstract":"The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <\u0000<inline-formula> <tex-math>$10{^{-}10 }$ </tex-math></inline-formula>\u0000 and <\u0000<inline-formula> <tex-math>$10{^{-}12 }$ </tex-math></inline-formula>\u0000 with a single-ended channel loss of 24 and 25 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"318-327"},"PeriodicalIF":0.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10757331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142870210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/OJSSCS.2024.3499967
Makoto Nagata;Takuji Miki
Semiconductor integrated circuit (IC) chips are regularly exposed to physical attacks and faced to the compromise of information security. An attacker leverages Si substrate backside as the open surface of an IC chip in flip-chip packaging and explores the points of information leakage over the entire backside without being hampered by physical obstacles as well as applying invasive treatments. Physical side channels (SCs), e.g., voltage potentials, current flows, electromagnetic (EM) waves, and photons, are transparent through Si substrate and attributed to the operation of security ICs. An attacker measures SCs using probes as well as antennas and correlates them with secret information, such as secret key bytes, used in a cryptographic processor or analog quantities at the frontend of Internet of Things (IoT) gadgets. This article defines and elucidates the emerging threats of Si-substrate backside attacks on flipped IC chips, demonstrates attacks and proposes countermeasures.
{"title":"Si Substrate Backside—An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging","authors":"Makoto Nagata;Takuji Miki","doi":"10.1109/OJSSCS.2024.3499967","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3499967","url":null,"abstract":"Semiconductor integrated circuit (IC) chips are regularly exposed to physical attacks and faced to the compromise of information security. An attacker leverages Si substrate backside as the open surface of an IC chip in flip-chip packaging and explores the points of information leakage over the entire backside without being hampered by physical obstacles as well as applying invasive treatments. Physical side channels (SCs), e.g., voltage potentials, current flows, electromagnetic (EM) waves, and photons, are transparent through Si substrate and attributed to the operation of security ICs. An attacker measures SCs using probes as well as antennas and correlates them with secret information, such as secret key bytes, used in a cryptographic processor or analog quantities at the frontend of Internet of Things (IoT) gadgets. This article defines and elucidates the emerging threats of Si-substrate backside attacks on flipped IC chips, demonstrates attacks and proposes countermeasures.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"365-375"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10755152","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/OJSSCS.2024.3501975
Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen
System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.
{"title":"Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications","authors":"Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen","doi":"10.1109/OJSSCS.2024.3501975","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3501975","url":null,"abstract":"System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"265-276"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10756610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL ${mathrm {FoM}}_{text {jitter-N}}$ of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.
{"title":"Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques","authors":"Teerachot Siriburanon;Chunxiao Liu;Jianglin Du;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3493803","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3493803","url":null,"abstract":"This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL \u0000<inline-formula> <tex-math>${mathrm {FoM}}_{text {jitter-N}}$ </tex-math></inline-formula>\u0000 of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"212-225"},"PeriodicalIF":0.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10746550","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/OJSSCS.2024.3488654
Henry Park;Mohammed Abdullatif;Ehung Chen;Tamer Ali
As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.
{"title":"112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems","authors":"Henry Park;Mohammed Abdullatif;Ehung Chen;Tamer Ali","doi":"10.1109/OJSSCS.2024.3488654","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3488654","url":null,"abstract":"As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"277-289"},"PeriodicalIF":0.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738450","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.
无线频谱是一种共享资源。发射机只能在其分配的频率范围内发射，而不能在其他频率上发射。发射机并非十全十美，因此有规定限制预定发射频率以外的发射能量。在本文中，我们将概述 5G FR2 的发射掩模要求，以及造成不必要发射的主要因素。然后，我们将介绍一些关键的无线电架构和电路设计注意事项，以帮助满足这些发射要求。由于本地振荡器 (LO) 漏电杂散是最严重的问题之一，我们还在上混频器中引入了 LO 消除技术。我们引入了两个执行器电路来控制上混频器输出端的两个独立 LO 信号，一个是从直流到 LO 的上变频信号，另一个是从 2 LO 到 LO 的下变频信号。这两个独立的 LO 输出可提供二维相位和振幅控制，并可在上混频器输出端组合成一个相等且相反的 LO 信号。LO 取消后，所有候选频率的 LO 泄漏均优于-57-dBc。最后，我们对不同频率、信号电平和 60 波束转向范围内的 64 元波束转向的 LO 抑制进行了广泛的空中 (OTA) 测量验证。
{"title":"The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation","authors":"Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu","doi":"10.1109/OJSSCS.2024.3487548","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3487548","url":null,"abstract":"The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"193-211"},"PeriodicalIF":0.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10737135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142679264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/OJSSCS.2024.3476035
Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms,> $(Delta Sigma )$ quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order $Delta Sigma $ modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.
{"title":"Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation","authors":"Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3476035","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3476035","url":null,"abstract":"A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms,> <tex-math>$(Delta Sigma )$ </tex-math></inline-formula>\u0000 quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"226-237"},"PeriodicalIF":0.0,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10707313","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/OJSSCS.2024.3472000
Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.
SAR ADC 具有功耗低、硬件结构紧凑等显著优势，因此在按比例 CMOS 技术中尤其具有吸引力，备受关注。SAR ADC 在转换后会在电容数模转换器 (CDAC) 上留下残留物，因此无需复杂的残留物提取电路。这一关键特性激发了众多 SAR 辅助架构的变化，并被应用于从高分辨率到高速度的一系列应用中。本文介绍了几种将 SAR ADC 作为子模块的高能效混合 ADC 架构，包括以下几种：SAR 辅助亚量程 SAR，可节省 DAC 开关电源，并能检测时间交错 ADC 的偏斜误差；SAR-闪存混合，可实现高能效高速转换；SAR 辅助双残差流水线 ADC，可消除对残差增益精度的严格要求；以及 SAR 辅助三角积分调制器 (DSM)，具有数域噪声耦合功能，可减少所需的模拟积分器数量。
{"title":"SAR-Assisted Energy-Efficient Hybrid ADCs","authors":"Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu","doi":"10.1109/OJSSCS.2024.3472000","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3472000","url":null,"abstract":"The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"163-175"},"PeriodicalIF":0.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702510","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/OJSSCS.2024.3469109
Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi
A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.
{"title":"Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth","authors":"Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi","doi":"10.1109/OJSSCS.2024.3469109","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3469109","url":null,"abstract":"A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"147-162"},"PeriodicalIF":0.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-20DOI: 10.1109/OJSSCS.2024.3464551
Yuncheng Zhang;Dingxin Xu;Kenichi Okada
This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.
{"title":"Digital Phase-Locked Loops: Exploring Different Boundaries","authors":"Yuncheng Zhang;Dingxin Xu;Kenichi Okada","doi":"10.1109/OJSSCS.2024.3464551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3464551","url":null,"abstract":"This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"176-192"},"PeriodicalIF":0.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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