Pub Date : 2024-12-19DOI: 10.1109/OJSSCS.2024.3520525
Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx
This work presents a $2times $ time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.
{"title":"A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS","authors":"Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx","doi":"10.1109/OJSSCS.2024.3520525","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3520525","url":null,"abstract":"This work presents a \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"11-20"},"PeriodicalIF":0.0,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10807254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJSSCS.2024.3519486
Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun
Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.
{"title":"Timing-Skew Calibration Techniques in Time-Interleaved ADCs","authors":"Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun","doi":"10.1109/OJSSCS.2024.3519486","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519486","url":null,"abstract":"Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJSSCS.2024.3517600
Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan
Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.
{"title":"Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator","authors":"Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan","doi":"10.1109/OJSSCS.2024.3517600","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3517600","url":null,"abstract":"Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"157-166"},"PeriodicalIF":0.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10803003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJSSCS.2024.3519054
Minoru Fujishima
The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.
{"title":"Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication","authors":"Minoru Fujishima","doi":"10.1109/OJSSCS.2024.3519054","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519054","url":null,"abstract":"The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"21-32"},"PeriodicalIF":0.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/OJSSCS.2024.3513255
Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn
This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.
{"title":"A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C","authors":"Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn","doi":"10.1109/OJSSCS.2024.3513255","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3513255","url":null,"abstract":"This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"145-156"},"PeriodicalIF":0.0,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783016","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78- $mu $ A rms, an averaged INRC density of 6.4 pA/ $sqrt {text {Hz}}$ , consumes 11.4 mW of power, and provides 87-dB $Omega $ transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.
{"title":"A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology","authors":"Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu","doi":"10.1109/OJSSCS.2024.3510478","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3510478","url":null,"abstract":"This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 A rms, an averaged INRC density of 6.4 pA/\u0000<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>\u0000, consumes 11.4 mW of power, and provides 87-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"328-339"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/OJSSCS.2024.3507754
Ali Sadr;Anthony Chan Carusone
This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing $4.7~{V}_{text {pp}}$ digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating $1.7~text {pJ/b}$ at $40~text {Gb/s}$ . With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of $540~mu text {W}$ (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.
本文提出了一种多目标热控制器，用于稳定硅光子微环调制器（MRMs）在不同温度条件和激光功率波动下的谐振波长。当实时数据流动时，控制器在后台运行，调整MRM共振波长以达到最佳的特定应用性能指标，包括消光比（ER），光调制幅度（OMA）或电平分离不匹配比（RLM）中的任何一个。这种通用偏置辅助光电流控制器能够选择性地调谐任何这些发射器指标，而不需要宽带电路。值得注意的是，这是第一个提出调整MRM以优化RLM的控制器，这一点尤其重要，因为MRM现在越来越多地用于4-PAM调制。控制器功能在单片集成于硅光子45纳米CMOS SOI工艺的MRM上进行验证，该MRM采用高摆幅4.7~{V}_{text {pp}}$数模转换器（DAC）的5.5位分辨率驱动程序，在$40~text {Gb/s}$时耗散$1.7~text {pJ/b}$。通过对控制器进行不同目标优化，在不采用非线性前馈均衡器（FFE）或预失真的情况下，实现了10.3 dB的ER、$540~mu text {W}$的OMA（归一化OMA为−3.2 dB）、0.67 dB的发射机色散闭眼四元（TDECQ）和0.96的RLM。
{"title":"A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller","authors":"Ali Sadr;Anthony Chan Carusone","doi":"10.1109/OJSSCS.2024.3507754","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3507754","url":null,"abstract":"This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing \u0000<inline-formula> <tex-math>$4.7~{V}_{text {pp}}$ </tex-math></inline-formula>\u0000 digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating \u0000<inline-formula> <tex-math>$1.7~text {pJ/b}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$40~text {Gb/s}$ </tex-math></inline-formula>\u0000. With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of \u0000<inline-formula> <tex-math>$540~mu text {W}$ </tex-math></inline-formula>\u0000 (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"340-350"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1109/OJSSCS.2024.3506692
Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim
High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.
{"title":"Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers","authors":"Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim","doi":"10.1109/OJSSCS.2024.3506692","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506692","url":null,"abstract":"High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"290-304"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.
{"title":"High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions","authors":"Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai","doi":"10.1109/OJSSCS.2024.3506694","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506694","url":null,"abstract":"The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"351-364"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1109/OJSSCS.2024.3503546
Changjae Moon;Minsoo Choi;Myungguk Lee;Byungsub Kim
From the perspective of channel behaviors, we review several design techniques of resistive termination for wireline applications. Termination impedances strongly affect the channel behaviors. Their impacts vary a lot depending on the types of interconnects and the circuits. Therefore, termination impedances must be appropriately designed for the target applications. In this article, first, we explain an intuitive analytical transfer function model of wireline channels. The model allows designers to easily and intuitively understand the impacts of the termination resistances on the channel behaviors. Second, we review various resistive termination techniques for LC-dominant channels and discuss their design tradeoffs. Especially, we theoretically explain the relaxed impedance matching technique, which allows designers to violate impedance matching for design improvements at the cost of a negligible penalty in signal integrity. Third, we review various resistive termination techniques for RC-dominant channels and their design tradeoffs. We especially emphasize and theoretically explain why and how the design tradeoffs by resistive terminations in RC-dominant channels are different from the ones in LC-dominant channels.
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