Pub Date : 2025-01-06DOI: 10.1109/OJSSCS.2025.3526132
Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue
The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.
{"title":"Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers","authors":"Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue","doi":"10.1109/OJSSCS.2025.3526132","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526132","url":null,"abstract":"The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"86-100"},"PeriodicalIF":0.0,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10824885","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-31DOI: 10.1109/OJSSCS.2024.3524493
Asad A. Abidi;David Murphy
CMOS oscillators that produce high frequencies with good spectral purity or low jitter are almost always realized as differential LC oscillators. This article gives a comprehensive treatment of this circuit for the practitioner who must make design choices and tradeoffs, and for the newcomer who wants to learn to do so. Phase noise is presented in the form of transfer functions from various noise sources, leading to compact, accurate expressions that guide design. Best practices for IC layout and operation at low voltages are given.
{"title":"How to Design a Differential CMOS LC Oscillator","authors":"Asad A. Abidi;David Murphy","doi":"10.1109/OJSSCS.2024.3524493","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524493","url":null,"abstract":"CMOS oscillators that produce high frequencies with good spectral purity or low jitter are almost always realized as differential LC oscillators. This article gives a comprehensive treatment of this circuit for the practitioner who must make design choices and tradeoffs, and for the newcomer who wants to learn to do so. Phase noise is presented in the form of transfer functions from various noise sources, leading to compact, accurate expressions that guide design. Best practices for IC layout and operation at low voltages are given.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"45-59"},"PeriodicalIF":0.0,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-26DOI: 10.1109/OJSSCS.2024.3523245
Sumukh Prashant Bhanushali;Arindam Sanyal
This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and $4times $ –$36times $ lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves the SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65-nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0.12 mW with SNDR/SFDR of 74.3/89.1 dB at 13.2 fJ/step for OSR of 9.
{"title":"A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC","authors":"Sumukh Prashant Bhanushali;Arindam Sanyal","doi":"10.1109/OJSSCS.2024.3523245","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3523245","url":null,"abstract":"This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and <inline-formula> <tex-math>$4times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$36times $ </tex-math></inline-formula> lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves the SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65-nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0.12 mW with SNDR/SFDR of 74.3/89.1 dB at 13.2 fJ/step for OSR of 9.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"75-85"},"PeriodicalIF":0.0,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816503","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-19DOI: 10.1109/OJSSCS.2024.3520525
Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx
This work presents a $2times $ time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.
{"title":"A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS","authors":"Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx","doi":"10.1109/OJSSCS.2024.3520525","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3520525","url":null,"abstract":"This work presents a \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"11-20"},"PeriodicalIF":0.0,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10807254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJSSCS.2024.3519486
Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun
Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.
{"title":"Timing-Skew Calibration Techniques in Time-Interleaved ADCs","authors":"Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun","doi":"10.1109/OJSSCS.2024.3519486","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519486","url":null,"abstract":"Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJSSCS.2024.3517600
Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan
Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.
{"title":"Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator","authors":"Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan","doi":"10.1109/OJSSCS.2024.3517600","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3517600","url":null,"abstract":"Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"157-166"},"PeriodicalIF":0.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10803003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJSSCS.2024.3519054
Minoru Fujishima
The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.
{"title":"Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication","authors":"Minoru Fujishima","doi":"10.1109/OJSSCS.2024.3519054","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519054","url":null,"abstract":"The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"21-32"},"PeriodicalIF":0.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/OJSSCS.2024.3513255
Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn
This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.
{"title":"A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C","authors":"Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn","doi":"10.1109/OJSSCS.2024.3513255","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3513255","url":null,"abstract":"This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"145-156"},"PeriodicalIF":0.0,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783016","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78- $mu $ A rms, an averaged INRC density of 6.4 pA/ $sqrt {text {Hz}}$ , consumes 11.4 mW of power, and provides 87-dB $Omega $ transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.
{"title":"A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology","authors":"Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu","doi":"10.1109/OJSSCS.2024.3510478","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3510478","url":null,"abstract":"This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 A rms, an averaged INRC density of 6.4 pA/\u0000<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>\u0000, consumes 11.4 mW of power, and provides 87-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"328-339"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/OJSSCS.2024.3507754
Ali Sadr;Anthony Chan Carusone
This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing $4.7~{V}_{text {pp}}$ digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating $1.7~text {pJ/b}$ at $40~text {Gb/s}$ . With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of $540~mu text {W}$ (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.
本文提出了一种多目标热控制器，用于稳定硅光子微环调制器（MRMs）在不同温度条件和激光功率波动下的谐振波长。当实时数据流动时，控制器在后台运行，调整MRM共振波长以达到最佳的特定应用性能指标，包括消光比（ER），光调制幅度（OMA）或电平分离不匹配比（RLM）中的任何一个。这种通用偏置辅助光电流控制器能够选择性地调谐任何这些发射器指标，而不需要宽带电路。值得注意的是，这是第一个提出调整MRM以优化RLM的控制器，这一点尤其重要，因为MRM现在越来越多地用于4-PAM调制。控制器功能在单片集成于硅光子45纳米CMOS SOI工艺的MRM上进行验证，该MRM采用高摆幅4.7~{V}_{text {pp}}$数模转换器（DAC）的5.5位分辨率驱动程序，在$40~text {Gb/s}$时耗散$1.7~text {pJ/b}$。通过对控制器进行不同目标优化，在不采用非线性前馈均衡器（FFE）或预失真的情况下，实现了10.3 dB的ER、$540~mu text {W}$的OMA（归一化OMA为−3.2 dB）、0.67 dB的发射机色散闭眼四元（TDECQ）和0.96的RLM。
{"title":"A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller","authors":"Ali Sadr;Anthony Chan Carusone","doi":"10.1109/OJSSCS.2024.3507754","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3507754","url":null,"abstract":"This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing \u0000<inline-formula> <tex-math>$4.7~{V}_{text {pp}}$ </tex-math></inline-formula>\u0000 digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating \u0000<inline-formula> <tex-math>$1.7~text {pJ/b}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$40~text {Gb/s}$ </tex-math></inline-formula>\u0000. With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of \u0000<inline-formula> <tex-math>$540~mu text {W}$ </tex-math></inline-formula>\u0000 (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"340-350"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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