Pub Date : 2022-12-16DOI: 10.1109/OJSSCS.2022.3230000
Mohamed R. Abdelhamid;Unsoo Ha;Utsav Banerjee;Fadel Adib;Anantha P. Chandrakasan
The past few years have witnessed a growing interest in wireless and batteryless implants, due to their potential in long-term biomedical monitoring of in-body conditions, such as internal organ movements, bladder pressure, and gastrointestinal health. Early proposals for batteryless implants relied on inductive near-field coupling and ultrasound harvesting, which require direct contact between the external power source and the human body. To overcome this near-field challenge, recent research has investigated the use of RF backscatter in wireless micro-implants because of its ability to communicate with wireless receivers that are placed at a distance outside the body $(sim 0.5$ m), allowing a more seamless user experience. Unfortunately, existing far-field backscatter designs remain limited in their functionality: they cannot perform biometric sensing or secure data transmission; they also suffer from degraded harvesting efficiency and backscatter range due to the impact of variations in the surrounding tissues. In this article, we present the design of a batteryless, wireless and secure system-on-chip (SoC) implant for in-body strain sensing. The SoC relies on four features: 1) employing a reconfigurable in-body rectenna which can operate across tissues adapting its backscatter bandwidth and center frequency; 2) designing an energy efficient 1.37 mmHg strain sensing front-end with an efficiency of 5.9 mmHg $cdot $ nJ/conversion; 3) incorporating an AES-GCM security engine to ensure the authenticity and confidentiality of sensed data while sharing the ADC with the sensor interface for an area-efficient random number generation; 4) implementing an over-the-air closed-loop wireless programming scheme to reprogram the RF front-end to adapt for surrounding tissues and the sensor front-end to achieve faster settling times below 2 s.
{"title":"Batteryless, Wireless, and Secure SoC for Implantable Strain Sensing","authors":"Mohamed R. Abdelhamid;Unsoo Ha;Utsav Banerjee;Fadel Adib;Anantha P. Chandrakasan","doi":"10.1109/OJSSCS.2022.3230000","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3230000","url":null,"abstract":"The past few years have witnessed a growing interest in wireless and batteryless implants, due to their potential in long-term biomedical monitoring of in-body conditions, such as internal organ movements, bladder pressure, and gastrointestinal health. Early proposals for batteryless implants relied on inductive near-field coupling and ultrasound harvesting, which require direct contact between the external power source and the human body. To overcome this near-field challenge, recent research has investigated the use of RF backscatter in wireless micro-implants because of its ability to communicate with wireless receivers that are placed at a distance outside the body \u0000<inline-formula> <tex-math>$(sim 0.5$ </tex-math></inline-formula>\u0000 m), allowing a more seamless user experience. Unfortunately, existing far-field backscatter designs remain limited in their functionality: they cannot perform biometric sensing or secure data transmission; they also suffer from degraded harvesting efficiency and backscatter range due to the impact of variations in the surrounding tissues. In this article, we present the design of a batteryless, wireless and secure system-on-chip (SoC) implant for in-body strain sensing. The SoC relies on four features: 1) employing a reconfigurable in-body rectenna which can operate across tissues adapting its backscatter bandwidth and center frequency; 2) designing an energy efficient 1.37 mmHg strain sensing front-end with an efficiency of 5.9 mmHg\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000nJ/conversion; 3) incorporating an AES-GCM security engine to ensure the authenticity and confidentiality of sensed data while sharing the ADC with the sensor interface for an area-efficient random number generation; 4) implementing an over-the-air closed-loop wireless programming scheme to reprogram the RF front-end to adapt for surrounding tissues and the sensor front-end to achieve faster settling times below 2 s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"41-51"},"PeriodicalIF":0.0,"publicationDate":"2022-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09990593.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-14DOI: 10.1109/OJSSCS.2022.3227060
Kris Myny
Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m $times3.37$ m [1] . This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.
{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Integrated Circuits and Systems Based on Thin-Film Transistors","authors":"Kris Myny","doi":"10.1109/OJSSCS.2022.3227060","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3227060","url":null,"abstract":"Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m \u0000<inline-formula> <tex-math>$times3.37$ </tex-math></inline-formula>\u0000 m \u0000<xref>[1]</xref>\u0000. This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"175-176"},"PeriodicalIF":0.0,"publicationDate":"2022-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09985431.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-14DOI: 10.1109/OJSSCS.2022.3227379
Jae-Sun Seo
Machine learning (ML) and artificial intelligence (AI) have been successful in many practical applications, e.g., image/speech/video recognition, object detection/tracking, natural language processing, etc. To efficiently execute such AI/ML algorithms, there have been large advances in custom hardware accelerator designs, such as digital systolic arrays of processing engines (PEs), and analog or digital circuits for in-/near-memory computing for deep neural networks (DNNs) [1] , [2] .
{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Custom Circuits and Architectures for Energy-Efficient Machine Learning","authors":"Jae-Sun Seo","doi":"10.1109/OJSSCS.2022.3227379","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3227379","url":null,"abstract":"Machine learning (ML) and artificial intelligence (AI) have been successful in many practical applications, e.g., image/speech/video recognition, object detection/tracking, natural language processing, etc. To efficiently execute such AI/ML algorithms, there have been large advances in custom hardware accelerator designs, such as digital systolic arrays of processing engines (PEs), and analog or digital circuits for in-/near-memory computing for deep neural networks (DNNs) \u0000<xref>[1]</xref>\u0000, \u0000<xref>[2]</xref>\u0000.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"217-218"},"PeriodicalIF":0.0,"publicationDate":"2022-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09985421.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-08DOI: 10.1109/OJSSCS.2022.3210152
Naresh R. Shanbhag;Saion K. Roy
In-memory computing (IMC) architectures have emerged as a compelling platform to implement energy-efficient machine learning (ML) systems. However, today, the energy efficiency gains provided by IMC designs seem to be leveling off and it is not clear what the limiting factors are. The conceptual complexity of IMCs combined with the absence of a rigorous benchmarking methodology makes it difficult to gauge progress and identify bottlenecks in this exciting field. This article presents a benchmarking methodology for IMCs comprising: 1) a compositional view of IMCs that enables one to parse an IMC design into its canonical components; 2) a set of benchmarking metrics to quantify the performance, efficiency, and accuracy of IMCs; and 3) a strategy for analyzing the reported IMC data and metrics. We apply the proposed benchmarking methodology on an extensive database of IMC metrics extracted from > 70 IC designs published since 2018, in order to infer and comprehend trends in this area. Our benchmarking effort indicates: 1) SRAM-based IMCs show a clear win in terms of energy efficiency and compute density over digital accelerators at the bank level but the energy efficiency gap reduces dramatically when comparing at the processor level; 2) eNVM-based IMCs lag behind SRAM-based IMCs in terms of both energy efficiency and compute density, and surprisingly lag digital accelerators in terms of compute density; 3) the compute (bank-level) accuracy of IMCs, though a critical metric, is pervasively neglected in publications as is the energy versus accuracy tradeoff inherent to IMCs.
{"title":"Benchmarking In-Memory Computing Architectures","authors":"Naresh R. Shanbhag;Saion K. Roy","doi":"10.1109/OJSSCS.2022.3210152","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3210152","url":null,"abstract":"In-memory computing (IMC) architectures have emerged as a compelling platform to implement energy-efficient machine learning (ML) systems. However, today, the energy efficiency gains provided by IMC designs seem to be leveling off and it is not clear what the limiting factors are. The conceptual complexity of IMCs combined with the absence of a rigorous benchmarking methodology makes it difficult to gauge progress and identify bottlenecks in this exciting field. This article presents a benchmarking methodology for IMCs comprising: 1) a compositional view of IMCs that enables one to parse an IMC design into its canonical components; 2) a set of benchmarking metrics to quantify the performance, efficiency, and accuracy of IMCs; and 3) a strategy for analyzing the reported IMC data and metrics. We apply the proposed benchmarking methodology on an extensive database of IMC metrics extracted from > 70 IC designs published since 2018, in order to infer and comprehend trends in this area. Our benchmarking effort indicates: 1) SRAM-based IMCs show a clear win in terms of energy efficiency and compute density over digital accelerators at the bank level but the energy efficiency gap reduces dramatically when comparing at the processor level; 2) eNVM-based IMCs lag behind SRAM-based IMCs in terms of both energy efficiency and compute density, and surprisingly lag digital accelerators in terms of compute density; 3) the compute (bank-level) accuracy of IMCs, though a critical metric, is pervasively neglected in publications as is the energy versus accuracy tradeoff inherent to IMCs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"288-300"},"PeriodicalIF":0.0,"publicationDate":"2022-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09976888.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50327146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Physically unclonable functions (PUFs) are being proposed as a low-cost alternative to permanently store secret keys or provide device authentication without requiring nonvolatile memory, large e-fuses, or other dedicated processing steps. In the literature, PUFs are split into two main categories. The so-called strong PUFs are mainly used for authentication purposes; hence, also called authentication PUFs. They promise to be lightweight by avoiding extensive digital post-processing and cryptography. The so-called weak PUFs, also called key generation PUFs, can only provide authentication when combined with a cryptographic authentication protocol. Over the years, multiple research results have demonstrated that Strong PUFs can be modeled and attacked by machine learning (ML) techniques. Hence, the general assumption is that the security of a strong PUF is solely dependent on its security against ML attacks. The goal of this article is to debunk this myth, by analyzing and breaking three recently published Strong PUFs (Suresh et al., VLSI Circuits 2020; Liu et al., ISSCC 2021; and Jeloka et al., VLSI Circuits 2017). The attacks presented in this article have practical complexities and use generic symmetric key cryptanalysis techniques.
物理上不可克隆的功能（PUF）被提出作为一种低成本的替代方案，用于永久存储密钥或提供设备认证，而不需要非易失性存储器、大型电子熔丝或其他专用处理步骤。在文献中，PUF分为两大类。所谓的强PUF主要用于身份验证目的；因此也称为认证PUF。它们承诺通过避免大量的数字后处理和加密来实现轻量级。所谓的弱PUF，也称为密钥生成PUF，只能在与加密身份验证协议结合时提供身份验证。多年来，多项研究结果表明，强PUF可以通过机器学习（ML）技术进行建模和攻击。因此，一般的假设是，强PUF的安全性完全取决于其对ML攻击的安全性。本文的目的是通过分析和打破最近发表的三个强PUF（Suresh et al.，VLSI Circuits 2020；Liu et al.，ISSCC 2021；以及Jeloka et al.，超大规模集成电路2017）来揭穿这个神话。本文提出的攻击具有实际的复杂性，并且使用通用的对称密钥密码分析技术。
{"title":"Cryptanalysis of Strong Physically Unclonable Functions","authors":"Liliya Kraleva;Mohammad Mahzoun;Raluca Posteuca;Dilara Toprakhisar;Tomer Ashur;Ingrid Verbauwhede","doi":"10.1109/OJSSCS.2022.3227009","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3227009","url":null,"abstract":"Physically unclonable functions (PUFs) are being proposed as a low-cost alternative to permanently store secret keys or provide device authentication without requiring nonvolatile memory, large e-fuses, or other dedicated processing steps. In the literature, PUFs are split into two main categories. The so-called strong PUFs are mainly used for authentication purposes; hence, also called authentication PUFs. They promise to be lightweight by avoiding extensive digital post-processing and cryptography. The so-called weak PUFs, also called key generation PUFs, can only provide authentication when combined with a cryptographic authentication protocol. Over the years, multiple research results have demonstrated that Strong PUFs can be modeled and attacked by machine learning (ML) techniques. Hence, the general assumption is that the security of a strong PUF is solely dependent on its security against ML attacks. The goal of this article is to debunk this myth, by analyzing and breaking three recently published Strong PUFs (Suresh et al., VLSI Circuits 2020; Liu et al., ISSCC 2021; and Jeloka et al., VLSI Circuits 2017). The attacks presented in this article have practical complexities and use generic symmetric key cryptanalysis techniques.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"32-40"},"PeriodicalIF":0.0,"publicationDate":"2022-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09971721.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-18DOI: 10.1109/OJSSCS.2022.3223274
Massimo Alioto
This work presents an overview of challenges and solid pathways toward ubiquitous and sustainable hardware security in next-generation silicon chips at the edge of distributed and connected systems (e.g., IoT and AIoT). As the first challenge, the increasingly connected nature and the exponential proliferation of edge devices are unabatingly increasing the overall attack surface, making attacks easier and mandating ubiquitous security down to each edge node. At the same time, the necessity to incorporate zero-trust policies in large-scale distributed systems requires a complete set of security primitives for hardware-backed authentication, and a higher degree of physical context awareness (including primitives detecting the onset of physical attacks). Thus, making the inclusion of such security primitives economically sustainable even in low-end devices is a second key challenge. As third challenge, the ever-changing vulnerability landscape and the need for increased chip longevity in distributed systems require security assurance methods that are sustainable and adaptive across the entire chip lifecycle. In this work, design principles and promising directions to enable ubiquitous and sustainable security capabilities along with physical awareness are discussed. Such achievements require a fundamental rethinking of design methodologies to enable aggressive design and resource reuse (e.g., area, power, and design effort), along with low-cost on-chip sensorization and intelligence for physical attack detection. Such rethinking inevitably crosses over the traditional design abstractions, and requires innovation from the physical to the algorithmic level. At the physical and circuit levels, design and resource reuse is enabled by immersed-in-logic and in-memory security approaches. At the algorithm level, “hardware patching” is introduced and exemplified to show that runtime intelligence (machine learning) allows security capabilities to adapt and improve over time, as typical of security patching in software. Sensing techniques to detect attacks in situ from noninvasive to invasive are illustrated while still preserving fully automated design approaches. Overall, the above design principles are expected to push security capabilities in distributed systems to a new level, ultimately making the edge more intelligent and self-reliant, and security measures more distributed.
{"title":"Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching","authors":"Massimo Alioto","doi":"10.1109/OJSSCS.2022.3223274","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3223274","url":null,"abstract":"This work presents an overview of challenges and solid pathways toward ubiquitous and sustainable hardware security in next-generation silicon chips at the edge of distributed and connected systems (e.g., IoT and AIoT). As the first challenge, the increasingly connected nature and the exponential proliferation of edge devices are unabatingly increasing the overall attack surface, making attacks easier and mandating ubiquitous security down to each edge node. At the same time, the necessity to incorporate zero-trust policies in large-scale distributed systems requires a complete set of security primitives for hardware-backed authentication, and a higher degree of physical context awareness (including primitives detecting the onset of physical attacks). Thus, making the inclusion of such security primitives economically sustainable even in low-end devices is a second key challenge. As third challenge, the ever-changing vulnerability landscape and the need for increased chip longevity in distributed systems require security assurance methods that are sustainable and adaptive across the entire chip lifecycle. In this work, design principles and promising directions to enable ubiquitous and sustainable security capabilities along with physical awareness are discussed. Such achievements require a fundamental rethinking of design methodologies to enable aggressive design and resource reuse (e.g., area, power, and design effort), along with low-cost on-chip sensorization and intelligence for physical attack detection. Such rethinking inevitably crosses over the traditional design abstractions, and requires innovation from the physical to the algorithmic level. At the physical and circuit levels, design and resource reuse is enabled by immersed-in-logic and in-memory security approaches. At the algorithm level, “hardware patching” is introduced and exemplified to show that runtime intelligence (machine learning) allows security capabilities to adapt and improve over time, as typical of security patching in software. Sensing techniques to detect attacks in situ from noninvasive to invasive are illustrated while still preserving fully automated design approaches. Overall, the above design principles are expected to push security capabilities in distributed systems to a new level, ultimately making the edge more intelligent and self-reliant, and security measures more distributed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"1-16"},"PeriodicalIF":0.0,"publicationDate":"2022-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09955388.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-15DOI: 10.1109/OJSSCS.2022.3222121
Kenneth K. O;Wooyeol Choi;Yukun Zhu;Haidong Guo
Complementary Oxide Semiconductor (CMOS) integrated circuits (IC’s) technology is emerging as a means for realization of capable and affordable systems that operate at frequencies near 300 GHz and higher. This is lowering a key barrier for utilizing the submillimeter electromagnetic waves in everyday applications. Despite the fact that the unity maximum available gain frequency, f max of $N$ -channel MOS (nMOS) transistors (with connections to the top metal layer) has peaked at ~320 GHz, signal generation up to 1.33 THz, coherent detection up to 1.2 THz, and incoherent detection up to ~10 THz have been demonstrated using CMOS IC’s. Furthermore, highly integrated rotational spectroscopy transceivers operating at frequencies up to near 300 GHz, and 400-GHz concurrent transceiver pixels and arrays for high-resolution radar imaging, and 300 and 390-GHz transmitters, and 300-GHz receivers for high data-rate communication have been demonstrated in CMOS. The performances of these CMOS circuits are sufficient or close to being sufficient to support electronic smelling using rotational spectroscopy that can detect and quantify concentrations of a wide variety of gases; imaging that can enable operation in a wide range of visually impaired conditions; and high-bandwidth communication. Finally, techniques for affordable packaging and testing submillimeter-wave systems are suggested based on experimental demonstrations.
{"title":"CMOS Platform for Everyday Applications Using Submillimeter Electromagnetic Waves","authors":"Kenneth K. O;Wooyeol Choi;Yukun Zhu;Haidong Guo","doi":"10.1109/OJSSCS.2022.3222121","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3222121","url":null,"abstract":"Complementary Oxide Semiconductor (CMOS) integrated circuits (IC’s) technology is emerging as a means for realization of capable and affordable systems that operate at frequencies near 300 GHz and higher. This is lowering a key barrier for utilizing the submillimeter electromagnetic waves in everyday applications. Despite the fact that the unity maximum available gain frequency, f max of \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-channel MOS (nMOS) transistors (with connections to the top metal layer) has peaked at ~320 GHz, signal generation up to 1.33 THz, coherent detection up to 1.2 THz, and incoherent detection up to ~10 THz have been demonstrated using CMOS IC’s. Furthermore, highly integrated rotational spectroscopy transceivers operating at frequencies up to near 300 GHz, and 400-GHz concurrent transceiver pixels and arrays for high-resolution radar imaging, and 300 and 390-GHz transmitters, and 300-GHz receivers for high data-rate communication have been demonstrated in CMOS. The performances of these CMOS circuits are sufficient or close to being sufficient to support electronic smelling using rotational spectroscopy that can detect and quantify concentrations of a wide variety of gases; imaging that can enable operation in a wide range of visually impaired conditions; and high-bandwidth communication. Finally, techniques for affordable packaging and testing submillimeter-wave systems are suggested based on experimental demonstrations.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"17-31"},"PeriodicalIF":0.0,"publicationDate":"2022-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09951399.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-14DOI: 10.1109/OJSSCS.2022.3221924
Yuan Ma;Yuping Deng;Chao Xie;Bingjing Zhang;Boyu Shen;Milin Zhang;Lan Yin;Xilin Liu;Jan van der Spiegel
Electrochemical detection is widely used in biosensing fields, such as medical diagnosis and health monitoring due to its real-time response and high accuracy. Both passive and active electrodes and the corresponding readout circuits have been continuously improved over the past decades. This article summarizes the redox reaction method, state-of-the-art electrode materials, and readout circuits based on the passive three-electrode. The redox-current-based readout circuits are widely used and developed toward multichannel high precision and low power consumption. In terms of active electrodes, this article reviews the development of field-effect transistors (FETs)-based electrochemical detection and readout circuits. In the past decade, the development of organic electrochemical transistors (OECTs) has also enabled more precise electrochemical detection.
{"title":"A Review of Electrochemical Electrodes and Readout Interface Designs for Biosensors","authors":"Yuan Ma;Yuping Deng;Chao Xie;Bingjing Zhang;Boyu Shen;Milin Zhang;Lan Yin;Xilin Liu;Jan van der Spiegel","doi":"10.1109/OJSSCS.2022.3221924","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3221924","url":null,"abstract":"Electrochemical detection is widely used in biosensing fields, such as medical diagnosis and health monitoring due to its real-time response and high accuracy. Both passive and active electrodes and the corresponding readout circuits have been continuously improved over the past decades. This article summarizes the redox reaction method, state-of-the-art electrode materials, and readout circuits based on the passive three-electrode. The redox-current-based readout circuits are widely used and developed toward multichannel high precision and low power consumption. In terms of active electrodes, this article reviews the development of field-effect transistors (FETs)-based electrochemical detection and readout circuits. In the past decade, the development of organic electrochemical transistors (OECTs) has also enabled more precise electrochemical detection.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"76-88"},"PeriodicalIF":0.0,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09950234.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-07DOI: 10.1109/OJSSCS.2022.3217231
Enrico Genco;Marco Fattori;Pieter J. A. Harpe;Francesco Modena;Fabrizio Antonio Viola;Mario Caironi;May Wheeler;Guillaume Fichet;Fabrizio Torricelli;Lucia Sarcina;Eleonora Macchia;Luisa Torsi;Eugenio Cantatore
This article presents a multiplexed current sensitive readout for label-free zeptomolar-sensitive detectors realized with large-area electrolyte-gated organic thin-film transistors (EGOFETs). These highly capacitive biosensors are multiplexed using an organic thin-film transistor (OTFT) line driver and OTFT switches and interfaced to a 65-nm Si CMOS, low-power, pA-sensitive front-end. The Si chip performs analog-to-digital conversion and data transmission to a microcontroller too. A current domain interface is used to transmit the signals coming from multiple biosensors to the 1.2-V supply CMOS Si-IC via the 30-V supply OTFT electronics. Exploiting an analog module implemented in the Si-IC, the EGOFETs are precisely biased, even in the presence of a large OTFT multiplexer resistance. The CMOS current sensitive front-end achieves a dynamic range (DR) of 137 dB and a power consumption of 42- $mu text{W}$ per channel reaching a state-of-the-art DR-power-bandwidth FOM of 208 dB. The front-end has been designed with a first-stage programmable-gain, active-feedback transimpedance amplifier topology that, contrary to common current-sensitive front-end solutions, is not affected by the sensor capacitance. The system has been validated with different concentrations of human IgG and IgM proteins using both a single sensor and a 4 $times $ 4 array of EGOFETs. Thanks to the multiplexing strategy and the low costs of its modules, the system here presented has the potential to enable widespread use of precision diagnostic with extreme sensitivity even in point-of-care and low-resource settings.
本文提出了一种用于无标记zeptomol-敏感探测器的多路电流敏感读出，该探测器由大面积电解质门控有机薄膜晶体管（EGOFET）实现。这些高电容性生物传感器使用有机薄膜晶体管（OTFT）线路驱动器和OTFT开关进行多路复用，并与65nm硅CMOS、低功耗、pA敏感前端接口。硅芯片还执行模数转换和向微控制器的数据传输。电流域接口用于通过30-V电源OTFT电子器件将来自多个生物传感器的信号传输到1.2V电源CMOS Si IC。利用在Si IC中实现的模拟模块，即使在存在大的OTFT多路复用器电阻的情况下，EGOFET也能精确偏置。CMOS电流敏感前端实现了137dB的动态范围（DR）和每通道42-$mutext｛W｝$的功耗，达到了208dB的最先进的DR功率带宽FOM。前端采用第一级可编程增益、有源反馈跨阻放大器拓扑结构设计，与常见的电流敏感前端解决方案相反，该拓扑结构不受传感器电容的影响。该系统已使用单个传感器和4$times$4的EGOFET阵列，用不同浓度的人IgG和IgM蛋白进行了验证。由于多路复用策略及其模块的低成本，这里介绍的系统有可能以极高的灵敏度广泛使用精确诊断，即使在护理点和低资源设置中也是如此。
{"title":"A 4 × 4 Biosensor Array With a 42-μW/Channel Multiplexed Current Sensitive Front-End Featuring 137-dB DR and Zeptomolar Sensitivity","authors":"Enrico Genco;Marco Fattori;Pieter J. A. Harpe;Francesco Modena;Fabrizio Antonio Viola;Mario Caironi;May Wheeler;Guillaume Fichet;Fabrizio Torricelli;Lucia Sarcina;Eleonora Macchia;Luisa Torsi;Eugenio Cantatore","doi":"10.1109/OJSSCS.2022.3217231","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3217231","url":null,"abstract":"This article presents a multiplexed current sensitive readout for label-free zeptomolar-sensitive detectors realized with large-area electrolyte-gated organic thin-film transistors (EGOFETs). These highly capacitive biosensors are multiplexed using an organic thin-film transistor (OTFT) line driver and OTFT switches and interfaced to a 65-nm Si CMOS, low-power, pA-sensitive front-end. The Si chip performs analog-to-digital conversion and data transmission to a microcontroller too. A current domain interface is used to transmit the signals coming from multiple biosensors to the 1.2-V supply CMOS Si-IC via the 30-V supply OTFT electronics. Exploiting an analog module implemented in the Si-IC, the EGOFETs are precisely biased, even in the presence of a large OTFT multiplexer resistance. The CMOS current sensitive front-end achieves a dynamic range (DR) of 137 dB and a power consumption of 42-\u0000<inline-formula> <tex-math>$mu text{W}$ </tex-math></inline-formula>\u0000 per channel reaching a state-of-the-art DR-power-bandwidth FOM of 208 dB. The front-end has been designed with a first-stage programmable-gain, active-feedback transimpedance amplifier topology that, contrary to common current-sensitive front-end solutions, is not affected by the sensor capacitance. The system has been validated with different concentrations of human IgG and IgM proteins using both a single sensor and a 4 \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 4 array of EGOFETs. Thanks to the multiplexing strategy and the low costs of its modules, the system here presented has the potential to enable widespread use of precision diagnostic with extreme sensitivity even in point-of-care and low-resource settings.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"193-207"},"PeriodicalIF":0.0,"publicationDate":"2022-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09940322.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many edge/mobile devices are now able to utilize deep neural networks (DNNs) thanks to the development of mobile DNN accelerators. Mobile DNN accelerators overcame the problems of limited computing resources and battery capacity by realizing energy-efficient inference. However, its passive behavior makes it difficult for DNN to provide active customization for individual users or its service environment. The importance of on-chip training is rising more and more to provide active interaction between DNN processors and ever-changing surroundings or conditions. Despite its advantages, the DNN training has more constraints than the inference such that it was considered impractical to be realized on mobile/edge devices. Recently, there are many trials to realize mobile DNN training, and a number of prior works will be summarized. First, it arranges the new challenges of the DNN accelerator induced by training functionality and discusses new hardware features related to the challenges. Second, it explains algorithm-hardware co-optimization methods and explains why it becomes mainstream in mobile DNN training research. Third, it compares the main differences between the conventional inference accelerators and recent training processors. Finally, the conclusion is made by proposing the future directions of the DNN training processor in micro-AI systems.
{"title":"Energy-Efficient DNN Training Processors on Micro-AI Systems","authors":"Donghyeon Han;Sanghoon Kang;Sangyeob Kim;Juhyoung Lee;Hoi-Jun Yoo","doi":"10.1109/OJSSCS.2022.3219034","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3219034","url":null,"abstract":"Many edge/mobile devices are now able to utilize deep neural networks (DNNs) thanks to the development of mobile DNN accelerators. Mobile DNN accelerators overcame the problems of limited computing resources and battery capacity by realizing energy-efficient inference. However, its passive behavior makes it difficult for DNN to provide active customization for individual users or its service environment. The importance of on-chip training is rising more and more to provide active interaction between DNN processors and ever-changing surroundings or conditions. Despite its advantages, the DNN training has more constraints than the inference such that it was considered impractical to be realized on mobile/edge devices. Recently, there are many trials to realize mobile DNN training, and a number of prior works will be summarized. First, it arranges the new challenges of the DNN accelerator induced by training functionality and discusses new hardware features related to the challenges. Second, it explains algorithm-hardware co-optimization methods and explains why it becomes mainstream in mobile DNN training research. Third, it compares the main differences between the conventional inference accelerators and recent training processors. Finally, the conclusion is made by proposing the future directions of the DNN training processor in micro-AI systems.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"259-275"},"PeriodicalIF":0.0,"publicationDate":"2022-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09935273.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50415865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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