Pub Date : 2025-08-11DOI: 10.1109/OJSSCS.2025.3597909
Nicolás Wainstein;Eran Avitay;Eugene Avner
This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ$cdot $ ns2.
{"title":"Fast-Locking and High-Resolution DLL With Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS","authors":"Nicolás Wainstein;Eran Avitay;Eugene Avner","doi":"10.1109/OJSSCS.2025.3597909","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3597909","url":null,"abstract":"This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>ns2.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"229-239"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11122556","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/OJSSCS.2025.3595832
Wen Chen;Yiyang Shu;Xun Luo
In this article, a wideband millimeter-wave (mm-wave) fractional-N subsampling phase-locked loop (SSPLL) with low jitter and low power consumption is proposed. A dividerless unequal-REF-delay frequency-tracking loop (URD-FTL) is introduced to ensure frequency locking over a wide mm-wave frequency range. By running the URD-FTL at the reference frequency instead of the oscillation frequency, the proposed design eliminates the need for high-power mm-wave frequency dividers. The URD-FTL is disabled while phase locking without sacrificing the jitter performance. Besides, the mm-wave quad-mode oscillator and digital-to-time converter are integrated in the SSPLL to achieve a wideband fractional operation. The proposed fractional-N SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.17 mm2. Measurements exhibit an output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The total power consumption is 11.6–14.8 mW, while the URD-FTL consumes only $680~mu $ W. The SSPLL achieves a 135.4–167.5-fs jitter within the output frequency range, which leads to an FoM$rm _{textbf {j}}$ from −246.7 to −243.9 dB. Meanwhile, the proposed SSPLL features a frequency locking acquisition.
{"title":"A 21.8–41.6-GHz Fractional-N Subsampling PLL With Dividerless Unequal-REF-Delay Frequency Tracking","authors":"Wen Chen;Yiyang Shu;Xun Luo","doi":"10.1109/OJSSCS.2025.3595832","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3595832","url":null,"abstract":"In this article, a wideband millimeter-wave (mm-wave) fractional-N subsampling phase-locked loop (SSPLL) with low jitter and low power consumption is proposed. A dividerless unequal-REF-delay frequency-tracking loop (URD-FTL) is introduced to ensure frequency locking over a wide mm-wave frequency range. By running the URD-FTL at the reference frequency instead of the oscillation frequency, the proposed design eliminates the need for high-power mm-wave frequency dividers. The URD-FTL is disabled while phase locking without sacrificing the jitter performance. Besides, the mm-wave quad-mode oscillator and digital-to-time converter are integrated in the SSPLL to achieve a wideband fractional operation. The proposed fractional-N SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.17 mm2. Measurements exhibit an output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The total power consumption is 11.6–14.8 mW, while the URD-FTL consumes only <inline-formula> <tex-math>$680~mu $ </tex-math></inline-formula>W. The SSPLL achieves a 135.4–167.5-fs jitter within the output frequency range, which leads to an FoM<inline-formula> <tex-math>$rm _{textbf {j}}$ </tex-math></inline-formula> from −246.7 to −243.9 dB. Meanwhile, the proposed SSPLL features a frequency locking acquisition.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"271-283"},"PeriodicalIF":3.2,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112717","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-18DOI: 10.1109/OJSSCS.2025.3561812
Youngcheol Chae;Mike Shuo-Wei Chen
{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Data Converters","authors":"Youngcheol Chae;Mike Shuo-Wei Chen","doi":"10.1109/OJSSCS.2025.3561812","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3561812","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"144-144"},"PeriodicalIF":0.0,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-05DOI: 10.1109/OJSSCS.2025.3577110
Dongseok Im;Gwangtae Park;Junha Ryu;Hoi-Jun Yoo
As artificial intelligence (AI) advances, 3-D spatial computing has emerged as a key application in various fields. It interprets the 3-D space surrounding users and provides them with useful information. This article presents a survey of AI hardware architectures and silicon solutions for 3-D spatial computing systems. The survey categorizes five domains: 1) 3-D data capturing; 2) 3-D data analysis; 3) 3-D hand motion analysis; 4) simultaneous localization and mapping (SLAM); and 5) 3-D rendering. Each session analyzes design considerations for domain-specific accelerators. Finally, this article discusses a next-generation 3-D spatial computing platform that integrates various functions of 3-D spatial computing systems using AI technologies.
{"title":"An Overview of AI Hardware Architectures and Silicon for 3-D Spatial Computing Systems","authors":"Dongseok Im;Gwangtae Park;Junha Ryu;Hoi-Jun Yoo","doi":"10.1109/OJSSCS.2025.3577110","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3577110","url":null,"abstract":"As artificial intelligence (AI) advances, 3-D spatial computing has emerged as a key application in various fields. It interprets the 3-D space surrounding users and provides them with useful information. This article presents a survey of AI hardware architectures and silicon solutions for 3-D spatial computing systems. The survey categorizes five domains: 1) 3-D data capturing; 2) 3-D data analysis; 3) 3-D hand motion analysis; 4) simultaneous localization and mapping (SLAM); and 5) 3-D rendering. Each session analyzes design considerations for domain-specific accelerators. Finally, this article discusses a next-generation 3-D spatial computing platform that integrates various functions of 3-D spatial computing systems using AI technologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"212-228"},"PeriodicalIF":0.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026096","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-18DOI: 10.1109/OJSSCS.2025.3534449
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2025.3534449","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3534449","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143848774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-11DOI: 10.1109/OJSSCS.2025.3560242
Jui-Hung Chang;Cheng-Han Ke;Chia-Lun Lee;Po-Cheng Lai;Chi-Hsuan Huang;Li-Wei Shih;Chih-Lung Lin
This work proposes a new pixel circuit using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for use in variable-frame-rate active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit, including seven TFTs and two capacitors, can compensate for threshold voltage ($V_{mathrm { TH}}$ ) variations of the driving TFTs (DTFTs), the turn-on voltages of the OLEDs ($V_{mathrm { OLED}}$ ), and $V_{mathrm { SS}}$ IR rises; it is immune to $V_{mathrm { DD}}$ IR drops. It employs amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs, which exhibit low leakage currents, suppressing distortion in the gate voltage of the DTFT at low frame rates and enabling a stable OLED current ($I_{mathrm { OLED}}$ ) to maintain consistent display luminance. A 1.28-In LTPO AMOLED panel with a $416times 416$ resolution and the proposed pixel circuit are fabricated to verify the circuit’s performance. The experimental results thus obtained confirm that red, green, blue, and white images at frame rates from 45 to 1 Hz exhibit uniformity without visible spot or line defects and a luminance error rate below 2.34%. Measured luminance values remain stable at gray levels of 32, 64, 128, and 255 during an extended emission period of 1 s, revealing no perceived image flicker at 1 Hz (with a Japan Electronics and Information Technology Industries Association flicker value below −54.747 dB). Therefore, the proposed circuit, with its highly uniform and stable currents at various frame rates, is promising for use in AMOLED smartwatch displays.
{"title":"LTPO-TFT-Based Pixel Circuit With TFT, OLED, and Supply Voltage Compensation for Enhanced Luminance Uniformity in Variable-Frame-Rate AMOLED Smartwatch Displays","authors":"Jui-Hung Chang;Cheng-Han Ke;Chia-Lun Lee;Po-Cheng Lai;Chi-Hsuan Huang;Li-Wei Shih;Chih-Lung Lin","doi":"10.1109/OJSSCS.2025.3560242","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3560242","url":null,"abstract":"This work proposes a new pixel circuit using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for use in variable-frame-rate active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit, including seven TFTs and two capacitors, can compensate for threshold voltage (<inline-formula> <tex-math>$V_{mathrm { TH}}$ </tex-math></inline-formula>) variations of the driving TFTs (DTFTs), the turn-on voltages of the OLEDs (<inline-formula> <tex-math>$V_{mathrm { OLED}}$ </tex-math></inline-formula>), and <inline-formula> <tex-math>$V_{mathrm { SS}}$ </tex-math></inline-formula> IR rises; it is immune to <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> IR drops. It employs amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs, which exhibit low leakage currents, suppressing distortion in the gate voltage of the DTFT at low frame rates and enabling a stable OLED current (<inline-formula> <tex-math>$I_{mathrm { OLED}}$ </tex-math></inline-formula>) to maintain consistent display luminance. A 1.28-In LTPO AMOLED panel with a <inline-formula> <tex-math>$416times 416$ </tex-math></inline-formula> resolution and the proposed pixel circuit are fabricated to verify the circuit’s performance. The experimental results thus obtained confirm that red, green, blue, and white images at frame rates from 45 to 1 Hz exhibit uniformity without visible spot or line defects and a luminance error rate below 2.34%. Measured luminance values remain stable at gray levels of 32, 64, 128, and 255 during an extended emission period of 1 s, revealing no perceived image flicker at 1 Hz (with a Japan Electronics and Information Technology Industries Association flicker value below −54.747 dB). Therefore, the proposed circuit, with its highly uniform and stable currents at various frame rates, is promising for use in AMOLED smartwatch displays.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"130-143"},"PeriodicalIF":0.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963900","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1109/OJSSCS.2025.3573904
Rui Xu;Jaroslav Bán;Sarthak Kalani;Chen-Kai Hsu;Subhajit Ray;Brian Kirby;Gabriel Matos;Julia Gonski;Andrew C. Smith;Daniel M. Williams;Kiley E. Kennedy;Alan Kahn;Michelle Contreras-Cossio;Lauren Larson;Michael Himmelsbach;Devanshu Panchal;Michael Unanian;Xiangxing Yang;Nan Sun;John Parsons;Timothy R. Andeen;Peter R. Kinget
The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.
{"title":"A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout","authors":"Rui Xu;Jaroslav Bán;Sarthak Kalani;Chen-Kai Hsu;Subhajit Ray;Brian Kirby;Gabriel Matos;Julia Gonski;Andrew C. Smith;Daniel M. Williams;Kiley E. Kennedy;Alan Kahn;Michelle Contreras-Cossio;Lauren Larson;Michael Himmelsbach;Devanshu Panchal;Michael Unanian;Xiangxing Yang;Nan Sun;John Parsons;Timothy R. Andeen;Peter R. Kinget","doi":"10.1109/OJSSCS.2025.3573904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3573904","url":null,"abstract":"The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"180-199"},"PeriodicalIF":0.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017335","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-27DOI: 10.1109/OJSSCS.2025.3573905
Wenyu Peng;Xinling Yue;Willem D. van Driel;Guoqi Zhang;Sijun Du
Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage ac output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-$mu $ m BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.
{"title":"A Dual-SSHC Rectifier With Digital-DCB MPPT for Triboelectric Energy Harvesting","authors":"Wenyu Peng;Xinling Yue;Willem D. van Driel;Guoqi Zhang;Sijun Du","doi":"10.1109/OJSSCS.2025.3573905","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3573905","url":null,"abstract":"Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage ac output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"200-211"},"PeriodicalIF":0.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11016074","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-21DOI: 10.1109/OJSSCS.2025.3540393
Woogeun Rhee
{"title":"New Associate Editors","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3540393","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3540393","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"101-103"},"PeriodicalIF":0.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/OJSSCS.2025.3571334
Archisman Ghosh;Dong-Hyun Seo;Debayan Das;Santosh Ghosh;Shreyas Sen
Side-channel attacks (SCAs) remain a significant threat to the security of cryptographic systems in modern embedded devices. Even mathematically secure cryptographic algorithms, when implemented in hardware, inadvertently leak information through physical side-channel signatures, such as power consumption, electromagnetic (EM) radiation, light emissions, and acoustic emanations. Exploiting these side channels significantly reduces the attacker’s search space. In recent years, physical countermeasures have significantly increased the minimum traces-to-disclosure (MTD) to 1 billion. Among them, signature attenuation is the first method to achieve this mark. Signature attenuation often relies on analog techniques, and digital signature attenuation reduces MTD to 20 million, requiring additional methods for high resilience. We focus on improving the digital signature attenuation by an order of magnitude (MTD 200M). Additionally, we explore possible attacks against signature attenuation countermeasure. We introduce a voltage-drop linear-region biasing (VLB) attack technique that reduces the MTD to over 2000 times less than the previous threshold. This is the first known attack against a physical SCA countermeasure. We have implemented an attack detector with a response time of 0.8 ms to detect such attacks, limiting the SCA leakage window to sub-ms, which is insufficient for a successful attack.
{"title":"R-STELLAR: A Resilient Synthesizable Signature Attenuation SCA Protection on AES-256 With Built-In Attack-on-Countermeasure Detection","authors":"Archisman Ghosh;Dong-Hyun Seo;Debayan Das;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3571334","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3571334","url":null,"abstract":"Side-channel attacks (SCAs) remain a significant threat to the security of cryptographic systems in modern embedded devices. Even mathematically secure cryptographic algorithms, when implemented in hardware, inadvertently leak information through physical side-channel signatures, such as power consumption, electromagnetic (EM) radiation, light emissions, and acoustic emanations. Exploiting these side channels significantly reduces the attacker’s search space. In recent years, physical countermeasures have significantly increased the minimum traces-to-disclosure (MTD) to 1 billion. Among them, signature attenuation is the first method to achieve this mark. Signature attenuation often relies on analog techniques, and digital signature attenuation reduces MTD to 20 million, requiring additional methods for high resilience. We focus on improving the digital signature attenuation by an order of magnitude (MTD 200M). Additionally, we explore possible attacks against signature attenuation countermeasure. We introduce a voltage-drop linear-region biasing (VLB) attack technique that reduces the MTD to over 2000 times less than the previous threshold. This is the first known attack against a physical SCA countermeasure. We have implemented an attack detector with a response time of 0.8 ms to detect such attacks, limiting the SCA leakage window to sub-ms, which is insufficient for a successful attack.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"167-179"},"PeriodicalIF":0.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006887","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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