Microprocessing and Microprogramming最新文献

An algorithm for multicast connection setup based on the distributed Takahashi-Matsuyama algorithm is reviewed. Additional level of unexplored parallelism that allows better time performance has been identified. The described improvement is based on the adaptive balancing of the growing Steiner tree during the connection construction process. A simulation study on the time complexity indicates a speedup with regard to the original algorithm as well as to our earlier improvement.

Predictable performance is crucial for real-time computing systems. We propose a buffered threaded prefetch scheme as a predictable and high performance instruction memory hierarchy. We also give extensions to the timing schema[3] to analyze the timing effects of the proposed scheme. In the extended timing schema, we associate with each program construct what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of the program construct. By defining a concatenation operation on WCTAs, our revised timing schema accurately accounts for the timing effects of the buffered threaded prefetching not only within but also across program constructs. This paper shows, through analysis using a timing tool based on the extended timing schema, the buffered prefetch scheme significantly improves the worst case execution times of tasks.

In this paper, we introduce a new image compression scheme that it involves three steps: First a multiresolution decomposition of the images is performed using the Wavelet Transform (WT). A thresholding algorithm is then used for the wavelet coefficients. Finally, the coefficients derived from the second step are vector quantized using a multiresoltuion codebook. The LGB algorithm is used for the Vector Quantization (VQ). Our experimental results showed that the Lena image can be coded by a two-level system at the rate of 0.24 bpp having a PSNR of 30.40 db.

This paper presents an effort to define a method for evaluation of parallel architectures dedicated to vision. A definition of the benchmark concept, and a characterisation of a standard set of general-purpose vision algorithms which could constitue a benchmark are proposed. These algorithms are independent of machine architecture, environments, programming models and parallelisation techniques supported. A detailed example illustrating the proposed approach is given.

This submission describes a system of data entry and acquisition for monitoring and diagnostics of aircraft. We shall discuss a four processor system in which single processors communicate with each other via serial links. All important parts will be described in following paragraphs.

We are seeking to find measures of risk that can be used by management and the developers. We will show which characteristics and constraints could be assessed directly from the requirements specification document in the form of numeric values. These numeric must be normalised and used in a comparative manner with other events in the software development process. The required characteristics — the specific risks — will be expressed by the proposed metrics. The construction of a database with requirements analysis process data is emphasised as a testbed for metrics evaluation. In summary our approach is as follows: First decide what the important areas of risk are, then identify attributes available in a CASE (Computer Aided Software engineering) repository that may give an insight into these risks and then combine these attributes to provide risk measures.

In this paper, we present a dynamic replication algorithm, DYVO, which could provide an optimal cost for operating replicas according to a read/write pattern of transactions. Unlike previous algorithms for dynamic replication, in which read one and write all available approach is used for preserving consistency of replicas, DYVO basically uses quorum approach for managing replicas. The quorum approach is basically able to encompass a large class of failures. Moreover, the quorum approach simplifies considerably the task maintaining the consistency of replicated data. As a result, DYVO is fault-tolerant to all kinds of failures and gives a way that minimizes overload for managing a replication algorithm.

In this paper a low complexity procedure for precedence analysis and cycle detection in DFGs, representing abstract architectures during the high level synthesis process, is presented. The proposed approach aims to reduce the computational overhead required to take topological constraints into consideration during the scheduling process.

Several timing verification algorithms for combinational circuits have been proposed in the last few years. However, similar algorithms do not exist for sequential circuits. Existing algorithms have difficulty in performing timing verification even for combinational circuits due to the excessive computation time and memory requirement for identifying the critical path. This paper presents a critical path analysis algorithm for sequential circuits. The algorithm can be used to identify the critical path of a sequential circuit while considering exact operation of the circuit without assuming the use of scan techniques. The input sequence which sensitizes the critical path is determined as well.