Microprocessing and Microprogramming最新文献

In this paper, a VLSI architecture for the computation of the 2-D N × N-point Discrete Cosine Transform (DCT) is presented, where N is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 Mpixels/sec.

Predictable performance is crucial for real-time computing systems. We propose a buffered threaded prefetch scheme as a predictable and high performance instruction memory hierarchy. We also give extensions to the timing schema[3] to analyze the timing effects of the proposed scheme. In the extended timing schema, we associate with each program construct what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of the program construct. By defining a concatenation operation on WCTAs, our revised timing schema accurately accounts for the timing effects of the buffered threaded prefetching not only within but also across program constructs. This paper shows, through analysis using a timing tool based on the extended timing schema, the buffered prefetch scheme significantly improves the worst case execution times of tasks.

In this paper, we introduce a new image compression scheme that it involves three steps: First a multiresolution decomposition of the images is performed using the Wavelet Transform (WT). A thresholding algorithm is then used for the wavelet coefficients. Finally, the coefficients derived from the second step are vector quantized using a multiresoltuion codebook. The LGB algorithm is used for the Vector Quantization (VQ). Our experimental results showed that the Lena image can be coded by a two-level system at the rate of 0.24 bpp having a PSNR of 30.40 db.

This submission describes a system of data entry and acquisition for monitoring and diagnostics of aircraft. We shall discuss a four processor system in which single processors communicate with each other via serial links. All important parts will be described in following paragraphs.

This paper presents an effort to define a method for evaluation of parallel architectures dedicated to vision. A definition of the benchmark concept, and a characterisation of a standard set of general-purpose vision algorithms which could constitue a benchmark are proposed. These algorithms are independent of machine architecture, environments, programming models and parallelisation techniques supported. A detailed example illustrating the proposed approach is given.

Several timing verification algorithms for combinational circuits have been proposed in the last few years. However, similar algorithms do not exist for sequential circuits. Existing algorithms have difficulty in performing timing verification even for combinational circuits due to the excessive computation time and memory requirement for identifying the critical path. This paper presents a critical path analysis algorithm for sequential circuits. The algorithm can be used to identify the critical path of a sequential circuit while considering exact operation of the circuit without assuming the use of scan techniques. The input sequence which sensitizes the critical path is determined as well.

Once a fuzzy controller is specified by a rule-set, it can be implemented in dedicated hardware or as a software program. For industrial applications, an inexpensive micro-controller with limited resources is often selected. The implementation (or mapping) issue then leads to a tradeoff between operation speed and memory usage. This paper presents a set of basic transformation rules that allows the designer to optimize such a mapping.

Frame Synchronized Ring (FSR-bus) is a new high speed interconnection network, developed for a wide range of real time applications. The medium access control (MAC) algorithm of the FSR has been analyzed with analytical models and simulations. However, these methods have not been powerful enough for proving some interesting properties of the algorithm. In this paper we explain, how predicate/transition (Pr/T) nets can be used in the modeling of the FSR-bus. In addition, we prove the deadlock freeness and the fairness of the MAC by analyzing the Pr/T-net model of the FSR.

The problem of accessing object versions from object-oriented programming language is discussed. Different approaches to consistency checking are discussed and compared. Some extensions to object-oriented languages are proposed to make it possible to version objects both at the compilation time and the application run-time.