Microprocessing and Microprogramming最新文献

The query language OVAL which is intended for the integration with the database programming language based on C++ is proposed in this paper. The work addresses the impedance mismatch problem [1] between the syntax and the semantics of the programming and query language. The query language OVAL is based on the functional query language FQL [3] extending it for the manipulation of complex objects. The salient features of the OVAL query language are: (i) functional nature of the query language, which makes the language suitable for the integration with the procedural programming languages and provides modular style of query definition, (ii) the use of schema information for expressing queries and (iii) recursive evaluation of the algebraic operations on set structured complex objects.

Several timing verification algorithms for combinational circuits have been proposed in the last few years. However, similar algorithms do not exist for sequential circuits. Existing algorithms have difficulty in performing timing verification even for combinational circuits due to the excessive computation time and memory requirement for identifying the critical path. This paper presents a critical path analysis algorithm for sequential circuits. The algorithm can be used to identify the critical path of a sequential circuit while considering exact operation of the circuit without assuming the use of scan techniques. The input sequence which sensitizes the critical path is determined as well.

Once a fuzzy controller is specified by a rule-set, it can be implemented in dedicated hardware or as a software program. For industrial applications, an inexpensive micro-controller with limited resources is often selected. The implementation (or mapping) issue then leads to a tradeoff between operation speed and memory usage. This paper presents a set of basic transformation rules that allows the designer to optimize such a mapping.

The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results.

Frame Synchronized Ring (FSR-bus) is a new high speed interconnection network, developed for a wide range of real time applications. The medium access control (MAC) algorithm of the FSR has been analyzed with analytical models and simulations. However, these methods have not been powerful enough for proving some interesting properties of the algorithm. In this paper we explain, how predicate/transition (Pr/T) nets can be used in the modeling of the FSR-bus. In addition, we prove the deadlock freeness and the fairness of the MAC by analyzing the Pr/T-net model of the FSR.

The problem of accessing object versions from object-oriented programming language is discussed. Different approaches to consistency checking are discussed and compared. Some extensions to object-oriented languages are proposed to make it possible to version objects both at the compilation time and the application run-time.

A pragmatic way is shown to calculate database cache sizes for a given desired level of cache performance, without use of application information. Treating applications as black boxes allows focusing on higher order structures of database accesses to classify applications. Online tracing of all database accesses allows a near-line simulation of cache performance for various cache sizes. These simulations result in typical patterns for application groups which point to areas with strong gradients in the relation between cache size and cache efficiency which can be exploited. The near-line-ness of this calculation lends itself to automatic adaptive cache size regulation.

The most critical problem associated with implementing in multi-level secure database management systems (MLS/DBMSs) is a correct concurrency control under the constraints of multilevel security. This paper provides two concurrency control schemes, one based on multiversion scheme and the other based on the two-phase locking scheme.

Stack machines, or stack based processors, have long been pigeon-holed as FORTH processors; specialised devices with little relevance for high level language applications. The failure of stack machines to address the issue of high level language support, and C in particular, has prevented wider acceptance of this promising technology despite the potential benefits of simpler hardware and low gate counts. Our research has centred upon eliminating cache and memory dependence, reducing the limits imposed by external bandwidths^◊. Having previously introduced a compact multiple-instruction-per-word stack-based encoding strategy in [Bailey93a], we now present a revised model, assessing its performance with compiled C benchmarks^⧫, and stressing minimisation of memory dependence.

This paper presents a method to estimate the clock cycle, taking into account the dead times of the operators, that influences the total execution time, and the number of control steps, that settles the control unit size. It accepts a module library and it considers the area importance versus time importance depending on user constraints.