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Architecture of resistive RAM with write driver 带写驱动的电阻式RAM结构
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.01.001
S. Dubey, A. Reddy, Rashi Patel, Master Abz, Avireni Srinivasulu, A. Islam
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引用次数: 6
A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators 一个5位500MS/s闪存ADC与温度补偿的基于逆变器的比较器
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.01.007
Jiangpeng Wang, Wing-Shan Tam, C. Kok, K. Pun
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引用次数: 7
Impacts of Indirect Wider Bandgap of Non-Toxic AlxGa1-xAs Buffer in Copper-Indium-Gallium-Diselenide Photovoltaic Cell 无毒AlxGa1-xAs缓冲液间接增宽带隙对铜铟镓二硒化物光伏电池的影响
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.09.001
Sadia Islam Shachi, N. Jahan, A. Bahar, M. Asaduzzaman
{"title":"Impacts of Indirect Wider Bandgap of Non-Toxic AlxGa1-xAs Buffer in Copper-Indium-Gallium-Diselenide Photovoltaic Cell","authors":"Sadia Islam Shachi, N. Jahan, A. Bahar, M. Asaduzzaman","doi":"10.1016/j.ssel.2020.09.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.09.001","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"26 1","pages":"103-108"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90839007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deep-subthreshold Schottky barrier IGZO TFT for ultra low-power applications 超低功耗应用的深亚阈值肖特基势垒IGZO TFT
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.10.001
A. Barua, K. Leedy, R. Jha
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引用次数: 7
Simulation and analysis of the forward bias current–voltage–temperature characteristics of W/4H-SiC Schottky barrier diodes for temperature-sensing applications 温度传感用W/4H-SiC肖特基势垒二极管正向偏置电流-电压-温度特性的仿真与分析
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.08.001
K. Zeghdar, Hichem Bencherif, L. Dehimi, F. Pezzimenti, Francesco G. DellaCorte
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引用次数: 3
SnO2 and Ni doped SnO2 /polythiophene nanocomposites for gas sensing applications SnO2和Ni掺杂SnO2 /聚噻吩纳米复合材料的气敏应用
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.11.003
P. Pascariu, I. V. Tudose, D. Vernardou, E. Koudoumas, O. Ionescu, S. Bucur, Mirela Petruta Suchea
{"title":"SnO2 and Ni doped SnO2 /polythiophene nanocomposites for gas sensing applications","authors":"P. Pascariu, I. V. Tudose, D. Vernardou, E. Koudoumas, O. Ionescu, S. Bucur, Mirela Petruta Suchea","doi":"10.1016/j.ssel.2020.11.003","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.003","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 1","pages":"85-91"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88123954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Ultrashallow defects in SiC MOS capacitors SiC MOS电容器的超浅缺陷
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.11.001
R. Pascu
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引用次数: 2
Structural optimization and miniaturization for Split-Gate Trench MOSFETs with 60 V breakdown voltage 60 V击穿电压的分栅沟槽mosfet结构优化与小型化
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.01.004
Yuji Lee, Jyh-Ling Lin
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引用次数: 1
Simulation on the electric field effect of Bi thin film Bi薄膜电场效应的模拟
Solid State Electronics Letters
Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.04.001
L. Hong, Chieh Chou, Hao-Hsiung Lin
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引用次数: 0
Design and optimization of 30 V fully isolated nLDMOS with low specific on-resistance for HVIC applications HVIC应用中低比导通电阻30v全隔离nLDMOS的设计与优化
Solid State Electronics Letters
Pub Date : 2019-07-01 DOI: 10.1016/j.ssel.2020.01.008
Vivek Ningaraju , Horng-Chih Lin , Po-An Chen , Kuang-Lun Lin

In this paper, a novel 30 V fully isolated n-channel lateral DMOS (nLDMOS) with low specific on-resistance (RON,sp) is proposed and experimentally realized using 0.35 µm Bipolar-CMOS-DMOS (BCD) process. We optimized the process parameters, such as doping concentration of the high-voltage drift n-well (HVNW) layer, P-buried layer (PBL) and pre deep n-well (Pre-DNW) layer, for achieving a superior tradeoff between high breakdown voltage (BV) and the low RON,sp. The proposed nLDMOS is fully isolated from the substrate to support negative bias to drain and has a very lower RON,sp than other competitors in the similar technology, which is critical for devices used in high-voltage, high-current switching applications such as HVIC's. The fabricated device exhibits a BV of 42 V with RON,sp as low as 15 mohm-mm2 . Besides, the new structure is fully compatible with standard 0.35 µm BCD technology, with a margin of up to 15% in process variation, which is large enough to meet the industrial requirement for mass production. Hence, it is not only high performance but also a low-cost solution.

本文提出了一种新颖的30 V全隔离n沟道横向DMOS (nLDMOS)，具有低比导通电阻(RON,sp)，并采用0.35µm双极cmos -DMOS (BCD)工艺进行了实验实现。为了在高击穿电压(BV)和低RON之间取得更好的平衡，我们优化了工艺参数，如高压漂移n-井(HVNW)层、p -埋层(PBL)和预深n-井(pre - dnw)层的掺杂浓度。所提出的nLDMOS与衬底完全隔离，以支持负偏置漏极，并且与同类技术的其他竞争对手相比，其RON,sp非常低，这对于HVIC等高压，大电流开关应用中使用的器件至关重要。制备的器件显示出42 V的BV与RON,sp低至15 mohm-mm2。此外，新结构完全兼容标准0.35µm BCD技术，工艺变化幅度高达15%，足以满足大规模生产的工业要求。因此，它不仅具有高性能，而且是一种低成本的解决方案。
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引用次数: 2
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