Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.01.004
Yu-Chin Lee, Jyh-Ling Lin
Power loss has long been a problem that humans continue to explore, especially in this high-performance era, in which the question of how to reduce the power loss of electronic products is an important issue. In this paper, Split-Gate MOSFETs were studied for parameter optimization and cell pitch miniaturization. The size of cell pitch is reduced to 1.45 um and specific on-resistance reduced to 79.81 mΩ-um2 when the breakdown voltage is kept higher than 60 V. The power loss is reduced by almost 70% comparison to commercial Split-Gate Trench MOSFETs.
{"title":"Structural optimization and miniaturization for Split-Gate Trench MOSFETs with 60 V breakdown voltage","authors":"Yu-Chin Lee, Jyh-Ling Lin","doi":"10.1016/j.ssel.2020.01.004","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.01.004","url":null,"abstract":"<div><p>Power loss has long been a problem that humans continue to explore, especially in this high-performance era, in which the question of how to reduce the power loss of electronic products is an important issue. In this paper, Split-Gate MOSFETs were studied for parameter optimization and cell pitch miniaturization. The size of cell pitch is reduced to 1.45 um and specific on-resistance reduced to 79.81 mΩ-um<sup>2</sup> when the breakdown voltage is kept higher than 60 V. The power loss is reduced by almost 70% comparison to commercial Split-Gate Trench MOSFETs.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 23-27"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.01.004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2021.02.001
Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok
This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.
{"title":"An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization","authors":"Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok","doi":"10.1016/j.ssel.2021.02.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2021.02.001","url":null,"abstract":"<div><p>This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 140-145"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2021.02.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.05.001
Samuel Husin Surya Mandala, M. Januar, Bei Liu, Kou-Chen Liu
{"title":"Designing the Topology of a Unipolar Pulsed-DC Power Supply using the Open-source Scilab/Xcos Software for a Low-cost Plasma Etcher","authors":"Samuel Husin Surya Mandala, M. Januar, Bei Liu, Kou-Chen Liu","doi":"10.1016/j.ssel.2020.05.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.05.001","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78848193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (VDD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (DCNT) and threshold voltage (Vth) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.
{"title":"Fast and energy efficient full adder circuit using 14 CNFETs","authors":"Jitendra Kumar Saini , Avireni Srinivasulu , Renu Kumawat","doi":"10.1016/j.ssel.2020.09.002","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.09.002","url":null,"abstract":"<div><p>With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (V<sub>DD</sub>) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (D<sub>CNT</sub>) and threshold voltage (V<sub>th</sub>) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 67-78"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.09.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91761617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.12.001
{"title":"Corrigendum to ’An Integrator Circuit Using Voltage Difference Transconductance Amplifier’ [Solid State Electronics Letters 1 (2019) 10-14]","authors":"","doi":"10.1016/j.ssel.2020.12.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.12.001","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"42 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84982924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/J.SSEL.2020.12.005
A. Basak, A. Sarkar
{"title":"Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET","authors":"A. Basak, A. Sarkar","doi":"10.1016/J.SSEL.2020.12.005","DOIUrl":"https://doi.org/10.1016/J.SSEL.2020.12.005","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"66 1","pages":"117-123"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83057238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/J.SSEL.2020.12.002
K. M. Santhoshini, Sarada Musala, Avireni Srinivasulu
{"title":"Corrigendum to: An Integrator Circuit Using Voltage Difference Transconductance Amplifier","authors":"K. M. Santhoshini, Sarada Musala, Avireni Srinivasulu","doi":"10.1016/J.SSEL.2020.12.002","DOIUrl":"https://doi.org/10.1016/J.SSEL.2020.12.002","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"52 1","pages":"109-114"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88045005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.12.004
Dr. Satyanarayana R․V․S․, Subramanyam Avvaru
An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.
{"title":"Design and Optimization of Double Balanced Gilbert Cell Mixer in 130 nm CMOS Process","authors":"Dr. Satyanarayana R․V․S․, Subramanyam Avvaru","doi":"10.1016/j.ssel.2020.12.004","DOIUrl":"10.1016/j.ssel.2020.12.004","url":null,"abstract":"<div><p>An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 129-139"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.12.004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76116415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.11.002
Roxana Tomescu, Cristian Kusko, Dana Cristea, Ramona Calinoiu, Catalin Parvulescu
In this article we propose a specifically tailored plasmonic metasurface structure which has the possibility to achieve perfect absorption at specific narrow wavelength intervals in infrared spectral domain. Our metasurface is composed of rectangular lattice of cylindrically shaped gold resonators with diameters in the range of hundreds of nanometres patterned on an amorphous silicon substrate. In order to attain absorption selectivity, we performed numerical 3D FDTD studies concerning geometrical parameters of the resonators such as diameter and periodicity of the square lattice. We numerically explored the geometrical space parameters consisting in the diameter and lattice constant for optimizing the absorption spectral characteristics for specific infrared wavelengths. The designed structures can be employed in developing infrared selective emission sources, perfect absorbent metamaterials or gas sensors.
{"title":"Nano-pillars metasurface modelled for perfect absorption at specific wavelengths in infrared spectral regime","authors":"Roxana Tomescu, Cristian Kusko, Dana Cristea, Ramona Calinoiu, Catalin Parvulescu","doi":"10.1016/j.ssel.2020.11.002","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.002","url":null,"abstract":"<div><p>In this article we propose a specifically tailored plasmonic metasurface structure which has the possibility to achieve perfect absorption at specific narrow wavelength intervals in infrared spectral domain. Our metasurface is composed of rectangular lattice of cylindrically shaped gold resonators with diameters in the range of hundreds of nanometres patterned on an amorphous silicon substrate. In order to attain absorption selectivity, we performed numerical 3D FDTD studies concerning geometrical parameters of the resonators such as diameter and periodicity of the square lattice. We numerically explored the geometrical space parameters consisting in the diameter and lattice constant for optimizing the absorption spectral characteristics for specific infrared wavelengths. The designed structures can be employed in developing infrared selective emission sources, perfect absorbent metamaterials or gas sensors.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 146-150"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.11.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91761616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}