Solid State Electronics Letters最新文献

Power loss has long been a problem that humans continue to explore, especially in this high-performance era, in which the question of how to reduce the power loss of electronic products is an important issue. In this paper, Split-Gate MOSFETs were studied for parameter optimization and cell pitch miniaturization. The size of cell pitch is reduced to 1.45 um and specific on-resistance reduced to 79.81 mΩ-um² when the breakdown voltage is kept higher than 60 V. The power loss is reduced by almost 70% comparison to commercial Split-Gate Trench MOSFETs.

This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.

With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (V_DD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (D_CNT) and threshold voltage (V_th) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.

An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.

As technological advancements are increasing in the world at a faster rate, the need of miniaturization is also growing parallelly. The scaling of existing MOS technology in nanometre regime has caused some limitations such as drastically increase in leakage current, power consumption and some quantum mechanical effects. This paper provides an insight of an alternative technology which makes use of new circuit element called memristor which can be successfully scaled at a lower nanometre regime. This paper proposes a new READ and WRITE circuitry to facilitate an easier read and write operation. The paper illustrates a transmission gate based 2T1M RRAM bit cell which uses memristor as a memory element and subjects it to process, voltage and temperature (PVT) variations with the aim of reflecting the improvement in performance metrices read and write delay along with the read current variability. The SPICE simulation results reflect that the proposed memory cell has a better stability due to its less read current variability against process variation (such as varying oxide thickness) and is robust with minimal variation in read/write delay with respect to the variations in voltage and temperature. The cell depicts shorter read and write delay compared to NAND and NOR CMOS based flash memories and it has 98.72%,94.53% lesser write time when compared to ambipolar transistor-based memory cell and memristor based content addressable memory (MCAM) respectively. The proposed cell also has 72.5% lesser read time compared to MCAM.