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Structural optimization and miniaturization for Split-Gate Trench MOSFETs with 60 V breakdown voltage 60 V击穿电压的分栅沟槽mosfet结构优化与小型化
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.01.004
Yu-Chin Lee, Jyh-Ling Lin

Power loss has long been a problem that humans continue to explore, especially in this high-performance era, in which the question of how to reduce the power loss of electronic products is an important issue. In this paper, Split-Gate MOSFETs were studied for parameter optimization and cell pitch miniaturization. The size of cell pitch is reduced to 1.45 um and specific on-resistance reduced to 79.81 mΩ-um2 when the breakdown voltage is kept higher than 60 V. The power loss is reduced by almost 70% comparison to commercial Split-Gate Trench MOSFETs.

功率损耗一直是人类不断探索的问题,特别是在这个高性能的时代,如何降低电子产品的功率损耗是一个重要的问题。本文对分栅mosfet进行了参数优化和单元间距小型化的研究。当击穿电压高于60 V时,电池间距减小到1.45 um,比导通电阻减小到79.81 mΩ-um2。与商用分栅沟槽mosfet相比,功率损耗降低了近70%。
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引用次数: 1
An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization 一种n通道带对带隧道式闪存设计优化
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2021.02.001
Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok

This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.

本文描述了一种使用源诱导带对带热电子(SIBE)注入编程方法的闪存单元的设计优化。编程效率由浮栅的隧穿电流决定,该电流与栅极长度覆盖宽度有关。本文通过仿真对最佳栅极长度覆盖宽度进行了实证研究,结果表明编程效率提高了一个数量级以上,大大降低了闪存的总功耗。
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引用次数: 0
Designing the Topology of a Unipolar Pulsed-DC Power Supply using the Open-source Scilab/Xcos Software for a Low-cost Plasma Etcher 基于开源Scilab/Xcos软件的低成本等离子体蚀刻器单极脉冲直流电源拓扑设计
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.05.001
Samuel Husin Surya Mandala, M. Januar, Bei Liu, Kou-Chen Liu
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引用次数: 0
Fast and energy efficient full adder circuit using 14 CNFETs 使用14个cnfet的快速节能全加法器电路
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.09.002
Jitendra Kumar Saini , Avireni Srinivasulu , Renu Kumawat

With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (VDD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (DCNT) and threshold voltage (Vth) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.

随着对更快,高效和强大的计算设备的需求不断增加,电路设计的工业研究面临着尺寸,功率,效率和可扩展性等挑战。设计师有一系列的选择,利用不同的设计方法,材料或技术来满足这些需求。近年来,碳纳米管场效应晶体管(CNFET)已成为设计高速、低功耗和低成本电路的一种临时替代方案。本文提出了一种使用14个cnfet的1位全加法器电路(1b-FA),以改进上述特性。采用32 nm CNFET技术,在电源电压(VDD)为+0.9V的条件下,利用Cadence Virtuoso CAD工具对该设计进行了仿真。从功率、延迟和功率延迟积(PDP)的角度对各种现有全加法器设计进行了性能分析。通过对CNFET直径(DCNT)和阈值电压(Vth)的参数变化来分析输出稳定性。此外,采用1b-FA实现了(n = 4,8,16,32)的n位纹波进位加法器(nb-RCA),并与现有的nb-RCA进行了比较,分析了性能和效率。后来加入了1b-FA输出自动纠错等功能。
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引用次数: 2
An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization 一种n通道带对带隧道式闪存设计优化
Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2021.02.001
Wing-Kong Ng, Wing-Shan Tam, C. Kok
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引用次数: 0
Corrigendum to ’An Integrator Circuit Using Voltage Difference Transconductance Amplifier’ [Solid State Electronics Letters 1 (2019) 10-14] “使用电压差跨导放大器的积分器电路”的勘误表[固态电子快报1 (2019)10-14]
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.001
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引用次数: 0
Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET 后门功函数对提高AJDMDG堆叠MOSFET模拟/射频性能的影响
Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2020.12.005
A. Basak, A. Sarkar
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引用次数: 5
Corrigendum to: An Integrator Circuit Using Voltage Difference Transconductance Amplifier 使用电压差跨导放大器的积分器电路的勘误表
Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2020.12.002
K. M. Santhoshini, Sarada Musala, Avireni Srinivasulu
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引用次数: 1
Design and Optimization of Double Balanced Gilbert Cell Mixer in 130 nm CMOS Process 130 nm CMOS双平衡Gilbert Cell混频器的设计与优化
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.004
Dr. Satyanarayana R․V․S․, Subramanyam Avvaru

An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.

针对印度各种无线设备在各种许可豁免频率范围内的特定增益和功率要求,提出了一种改进的双平衡吉尔伯特小区混频器设计程序。下变频混频器设计的目标是在130纳米CMOS工艺下实现。在2.5 mW直流功率下,在混频器的跨导和开关级的最小超速驱动下,转换增益超过10 dB,噪声系数低于10 dB。提出了几种优化技术,以提高所设计混频器的增益、线性度和噪声性能。针对1 db增益压缩和三阶截距点,将线性度提高约10 dBm,引入一个独特的标准,在保留混频器增益和噪声性能的同时,整合并详尽地探索增强技术。
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引用次数: 3
Nano-pillars metasurface modelled for perfect absorption at specific wavelengths in infrared spectral regime 纳米柱超表面模型的完美吸收在特定波长的红外光谱制度
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.002
Roxana Tomescu, Cristian Kusko, Dana Cristea, Ramona Calinoiu, Catalin Parvulescu

In this article we propose a specifically tailored plasmonic metasurface structure which has the possibility to achieve perfect absorption at specific narrow wavelength intervals in infrared spectral domain. Our metasurface is composed of rectangular lattice of cylindrically shaped gold resonators with diameters in the range of hundreds of nanometres patterned on an amorphous silicon substrate. In order to attain absorption selectivity, we performed numerical 3D FDTD studies concerning geometrical parameters of the resonators such as diameter and periodicity of the square lattice. We numerically explored the geometrical space parameters consisting in the diameter and lattice constant for optimizing the absorption spectral characteristics for specific infrared wavelengths. The designed structures can be employed in developing infrared selective emission sources, perfect absorbent metamaterials or gas sensors.

在本文中,我们提出了一种特殊定制的等离子体超表面结构,它有可能在红外光谱域的特定窄波长间隔内实现完美的吸收。我们的超表面是由直径在数百纳米范围内的圆柱形金谐振器的矩形晶格组成的,这些谐振器图案在非晶硅衬底上。为了获得吸收选择性,我们对谐振器的几何参数(如直径和方形晶格的周期性)进行了数值三维时域有限差分研究。为了优化特定红外波长的吸收光谱特性,我们用数值方法探索了由直径和晶格常数组成的几何空间参数。所设计的结构可用于开发红外选择性发射源、完美吸收材料或气体传感器。
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引用次数: 5
期刊
Solid State Electronics Letters
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