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Impacts of Indirect Wider Bandgap of Non-Toxic AlxGa1-xAs Buffer in Copper-Indium-Gallium-Diselenide Photovoltaic Cell 无毒AlxGa1-xAs缓冲液间接增宽带隙对铜铟镓二硒化物光伏电池的影响
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.09.001
Sadia Islam Shachi , Nusrat Jahan , Ali Newaz Bahar , Md. Asaduzzaman

A numerical simulation and substantiation have been accomplished to analyze the impact of Al0.9Ga0.1As alloy composite buffer layer band gap and thickness, absorber layer thickness on a ZnO:Al/i-ZnO/Al0.9Ga0.1As/CIGS/Mo/SLG structured non-toxic Cd-free CIGS photovoltaic cell. In this study, the cell output attributes including efficiency (η) and collection efficiency (ηc) have been optimized through short circuit current density (Jsc), open-circuit voltage (Voc) and fill factor (FF) optimization. Our study has been concluded with the maximum efficiency of 24.32% with Voc = 839.76 mV, Jsc = 36.21mA/cm2 and FF=76.96%, ηc = 83.16%. This enhanced efficiency is optimized by determining the bandgap of the buffer through altering the Al concentration to transit it from direct bandgap material to an indirect one. The thickness of the absorber on system performance is also investigated, and its extent is found in between 2 µm to 3 µm.

通过数值模拟和验证,分析了Al0.9Ga0.1As合金复合缓冲层带隙、厚度、吸收层厚度对ZnO:Al/i-ZnO/Al0.9Ga0.1As/CIGS/Mo/SLG结构无毒无cd CIGS光伏电池的影响。本研究通过优化短路电流密度(Jsc)、开路电压(Voc)和填充因子(FF),优化电池输出属性,包括效率(η)和收集效率(ηc)。结果表明:Voc = 839.76 mV, Jsc = 36.21mA/cm2, FF=76.96%, ηc = 83.16%,效率最高,为24.32%。通过改变Al浓度使其从直接带隙材料过渡到间接带隙材料来确定缓冲带的带隙,从而优化了这种增强的效率。研究了吸波器厚度对系统性能的影响,发现其影响范围在2µm到3µm之间。
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引用次数: 1
Optical field concentrator with low absorption metasurfaces based on planar silicon nanoantennas on silica 基于平面硅纳米天线的低吸收超表面光场聚光器
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.08.002
M. Obradov, Z. Jakšić, D. Tanasković, O. Jakšić, D. Vasiljević Radović

Plasmonic metamaterials open a pathway to a multitude of different applications, from ultrasensitive sensors to merging the packaging density of electronics and the speed of photonics in a single all-optical device. A severe limitation to their wider use is high absorption due to the mandatory presence of free electron-containing conductive parts which are lossy by definition. In this contribution we consider an alternative solution in the form of ultrathin silicon films deposited on a silica substrate. The films are patterned as arrays of elongated rhombuses acting as bowtie nanoantennas. We consider the effect of sharp tips and the proximity effect on the electromagnetic field concentration in such low-loss metasurfaces. Our structures have the advantage of very low absorption losses with an order of magnitude field enhancement and the virtue of full compatibility with the standard planar technologies. This makes them convenient for various practical applications which integrate high field concentration with e.g. waveguiding properties, for instance microreactors, labs-on-a-chip, photocatalytic systems and various other Micro-Opto-Electro-Mechanical System (MOEMS) devices integrating optical, microfluidic and other functionalities.

等离子体超材料为许多不同的应用开辟了一条道路,从超灵敏的传感器到将电子器件的封装密度和光子学的速度融合在一个单一的全光器件中。它们广泛使用的一个严重限制是由于含有自由电子的导电部分的强制性存在而产生的高吸收,这些部分根据定义是有损耗的。在这篇文章中,我们考虑了在硅衬底上沉积超薄硅膜的替代解决方案。薄膜的图案是细长的菱形阵列,充当领结纳米天线。在这种低损耗的超表面中,我们考虑了尖尖和邻近效应对电磁场浓度的影响。我们的结构具有非常低的吸收损耗和一个数量级的场增强以及与标准平面技术完全兼容的优点。这使得它们方便于各种实际应用,这些应用集成了高场浓度,例如波导特性,例如微反应器,芯片实验室,光催化系统和各种其他集成光学,微流体和其他功能的微光电机械系统(MOEMS)设备。
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引用次数: 0
The Simulation Study on Internal Stress in Multilayer Thermistors during Soldering Process 多层热敏电阻焊接过程内应力的模拟研究
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.003
NamChol Yu , JuSong Kim , Yong Ho Li , Song Chol Pak

A new 3D finite element model to characterize the residual stress distribution in multilayer NTC thermistor during soldering process has been developed. During the soldering process, the effects of inner silver electrode number and lateral margin length on mechanical residual stress are studied. Throughout the weldbonding and heating process, the maximum and minimum principal stresses in the active region of the thermistor ceramic are not zero, which implies that most of the thermistor ceramic is not stress-free. Numerical results show that the increasing of the lateral margin length could effectively decrese the maximum tensile stress.

建立了表征多层NTC热敏电阻焊接过程中残余应力分布的三维有限元模型。在焊接过程中,研究了内银电极数量和侧缘长度对机械残余应力的影响。在整个焊接和加热过程中,热敏电阻陶瓷有源区的最大和最小主应力不为零,这意味着大部分热敏电阻陶瓷不是无应力的。数值结果表明,增大侧缘长度可以有效降低最大拉应力。
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引用次数: 0
Deep-subthreshold Schottky barrier IGZO TFT for ultra low-power applications 超低功耗应用的深亚阈值肖特基势垒IGZO TFT
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.10.001
Abhijeet Barua , Kevin D. Leedy , Rashmi Jha

This study reports the deep subthreshold characteristics (≤1 V) of low thermal budget Indium Gallium Zinc Oxide (IGZO) thin film transistors (TFTs) with Schottky barrier source/drain contacts. The Schottky barrier was analyzed and a consistent ideality factor was observed across the devices. A deep subthreshold region was extracted from the nominal characteristics and barrier influence was observed in the low voltage region. This operation led to high output impedance (~1012Ω) and excellent trans-conductance leading to a high voltage gain (>100) due to hard saturation of the output characteristics. Positive bias stress and stability tests were conducted within this region that showed minimal drift in the transfer characteristics. Such characteristics make these devices an excellent choice for low-power deep subthreshold and weak signal applications.

本研究报道了具有肖特基势垒源/漏触点的低热收支铟镓锌氧化物(IGZO)薄膜晶体管(TFTs)的深亚阈值特性(≤1 V)。对肖特基势垒进行了分析,并在器件之间观察到一致的理想因子。从标称特征中提取了深亚阈值区域,并在低压区域观察了势垒影响。这种操作导致高输出阻抗(~1012Ω)和优异的跨导,导致高电压增益(>100),由于输出特性的硬饱和。正偏压应力和稳定性测试在这个区域内进行,显示最小漂移的转移特性。这些特性使这些器件成为低功耗深亚阈值和弱信号应用的绝佳选择。
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引用次数: 7
Designing the Topology of a Unipolar Pulsed-DC Power Supply using the Open-source Scilab/Xcos Software for a Low-cost Plasma Etcher 基于开源Scilab/Xcos软件的低成本等离子体蚀刻器单极脉冲直流电源拓扑设计
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.05.001
Samuel Husin Surya Mandala , Mochamad Januar , Bei Liu , Kou-Chen Liu

We proposed a design topology for a unipolar pulsed direct-current power supply to produce low-cost reactive plasma etcher system. The design was simulated by a block diagram method using the open-source software Scilab/Xcos, and the results were validated by prototyping the power supply. In the topology, the snubber circuit and the RLC circuit play a critical role in producing a smoother pulse waveform and regulating the characteristics of the plasma current. Their optimized parameters can provide well-controllable duty cycles in the voltage output of the power supply. Moreover, the effect of the duty cycles on the performance of the power supply is analyzed. We found that the duty cycle can adjust the transient response of the plasma current as well as the density of the plasma ions. This aspect is useful not only for reducing the arcing effect but also for modifying the surface wettability of the treated substrates. As a result, the glass substrates treated with a 100% duty cycle becomes more hydrophilic, while those treated with a 20% duty cycle tend to be more hydrophobic.

我们提出了一种单极脉冲直流电源的设计拓扑,用于生产低成本的反应等离子体蚀刻系统。利用开源软件Scilab/Xcos对设计进行了方框图仿真,并通过电源样机验证了设计结果。在拓扑结构中,缓冲电路和RLC电路对产生更平滑的脉冲波形和调节等离子体电流特性起着至关重要的作用。它们的优化参数可以在电源输出电压中提供良好的可控占空比。此外,还分析了占空比对电源性能的影响。我们发现占空比可以调节等离子体电流的瞬态响应以及等离子体离子的密度。这一方面不仅可用于减少电弧效应,而且可用于修饰处理过的基材的表面润湿性。因此,100%占空比处理的玻璃基板变得更亲水,而20%占空比处理的玻璃基板往往更疏水。
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引用次数: 0
Ultrashallow defects in SiC MOS capacitors SiC MOS电容器的超浅缺陷
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.001
Razvan Pascu

Capacitance-voltage measurements performed at cryogenic temperatures (14 – 500 K) have been used to determine the ultrashallow interface states in SiC MOS capacitors. These states occupies energy levels in SiC band gap on different energy levels up to 27 meV below the conduction band. Moreover, the capacitance-voltage characteristics are moving to lower voltages with temperature increasing, indicating a reduction in flat band voltage from 14.65 (14 K) to 2.77 V (500 K). It was demonstrated that a complete ionization of the nitrogen donors from the epitaxial layer occurs at 420 K. From these analysis, an activation energy of around 26.79 meV was determined. In order to determine the energy levels distribution of the interface states in SiC band gap, the Fermi level variation with temperature was calculated, starting from a value of around 27.1 meV at 14 K and reaching a value of 321 meV at 500 K under SiC conduction band. Six peaks (D1 – D6) have been identified in interface states density distribution at different levels of energy in SiC band gap, which could correspond to different defects at the SiO2/SiC interface.

在低温(14 - 500 K)下进行的电容电压测量已被用于确定SiC MOS电容器的超浅界面状态。这些态占据了SiC带隙中不同能级的能级,最高可达传导带以下27 meV。此外,随着温度的升高,电容电压特性向更低的电压移动,表明平带电压从14.65 (14 K)降低到2.77 V (500 K)。结果表明,在420 K时,外延层的氮供体发生完全电离。从这些分析中,确定了活化能约为26.79 meV。为了确定SiC带隙中界面态的能级分布,计算了费米能级随温度的变化,在SiC导带下,从14 K时的27.1 meV左右开始,到500 K时达到321 meV。在SiC带隙中不同能级的界面态密度分布中发现了6个峰(D1 - D6),这可能对应了SiO2/SiC界面上不同的缺陷。
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引用次数: 2
SnO2 and Ni doped SnO2 /polythiophene nanocomposites for gas sensing applications SnO2和Ni掺杂SnO2 /聚噻吩纳米复合材料的气敏应用
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.003
P. Pascariu , I.V. Tudose , D. Vernardou , E. Koudoumas , O.N. Ionescu , S. Bucur , M. Suchea

This short letter reports the achievement of promising sensing properties by using pure and Ni doped SnO2-Polythiophene nanostructured materials. These nanocomposites of SnO2 (undoped and doped with Ni) and polythiophene (PTh) were synthesized by electrochemical oxidative polymerization of thiophene in the presence of the two types of nanoparticles obtained by co‐precipitation. The as obtained materials were used as active layer in sensing devices. The nanocomposites were structurally characterized and their electrochemical properties were evaluated by cyclic voltammetry. The nanocomposites conductivity variation with temperature was studied in air and then were exposed to different pollutant gases to investigate the composites suitability for gas sensing applications, which prove to be promising materials.

这篇短文报道了使用纯和Ni掺杂的sno2 -聚噻吩纳米结构材料取得的有前途的传感性能。在共沉淀法得到的两种纳米粒子存在的情况下,通过电化学氧化聚合,合成了SnO2(未掺杂和掺杂Ni)和多噻吩(PTh)的纳米复合材料。所得材料用作传感器件的有源层。对纳米复合材料进行了结构表征,并用循环伏安法对其电化学性能进行了评价。研究了纳米复合材料在空气中电导率随温度的变化规律,并将其暴露于不同的污染气体中,考察了纳米复合材料在气敏应用中的适用性。
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引用次数: 9
Corrigendum to: An Integrator Circuit Using Voltage Difference Transconductance Amplifier 使用电压差跨导放大器的积分器电路的勘误表
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.002
Kaza Malathi Santhoshini , Sarada Musala , Avireni Srinivasulu

This paper illustrates a novel design of voltage-mode integrator using the active element, namely voltage difference transconductance amplifier (VDTA). The proposed circuit only requires one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 μA. And also, the transconductance (gm) is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are functionally verified through experiment with the commercially available ICs LM13700. The proposed VDTA based integrator is highly useful in the dual slope/integrating type analogue to digital converters for higher resolutions.

本文介绍了一种利用有源元件——电压差跨导放大器(VDTA)的电压型积分器的新设计。所提出的电路只需要一个VDTA元件和一个电容。这为超大规模集成电路设计中集成电路的制作提供了更有利的条件。设计的电路工作在±0.9 V电源电压下,使用150 μA数量级的偏置电流。此外,跨导(gm)是电子调谐与偏置电流。该电路采用gpdk 180 nm CMOS工艺,使用Cadence Virtuoso工具设计,功耗为270 μ W。通过LM13700商用集成电路的实验验证了仿真结果的功能。所提出的基于VDTA的积分器在高分辨率的双斜率/积分型模拟数字转换器中非常有用。
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引用次数: 1
Low power frequency doubler 低功率倍频器
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.004
Wing-Kong Ng, Wing-Shan Tam, C. Kok
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引用次数: 2
Low power frequency doubler 低功率倍频器
Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.004
Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok

A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply voltage variations with excellent frequency and phase performance on high frequency clock generation.

提出了一种只需要标准CMOS逻辑门和片上无源元件的低工频倍频电路。该电路结构紧凑,并通过FPGA实现进行了验证。结果表明,该电路对较宽的频率范围和电源电压变化具有较强的鲁棒性,在高频时钟产生方面具有良好的频率和相位性能。
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引用次数: 2
期刊
Solid State Electronics Letters
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