Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.09.001
Sadia Islam Shachi , Nusrat Jahan , Ali Newaz Bahar , Md. Asaduzzaman
A numerical simulation and substantiation have been accomplished to analyze the impact of Al0.9Ga0.1As alloy composite buffer layer band gap and thickness, absorber layer thickness on a ZnO:Al/i-ZnO/Al0.9Ga0.1As/CIGS/Mo/SLG structured non-toxic Cd-free CIGS photovoltaic cell. In this study, the cell output attributes including efficiency (η) and collection efficiency (ηc) have been optimized through short circuit current density (Jsc), open-circuit voltage (Voc) and fill factor (FF) optimization. Our study has been concluded with the maximum efficiency of 24.32% with Voc = 839.76 mV, Jsc = 36.21mA/cm2 and FF=76.96%, ηc = 83.16%. This enhanced efficiency is optimized by determining the bandgap of the buffer through altering the Al concentration to transit it from direct bandgap material to an indirect one. The thickness of the absorber on system performance is also investigated, and its extent is found in between 2 µm to 3 µm.
{"title":"Impacts of Indirect Wider Bandgap of Non-Toxic AlxGa1-xAs Buffer in Copper-Indium-Gallium-Diselenide Photovoltaic Cell","authors":"Sadia Islam Shachi , Nusrat Jahan , Ali Newaz Bahar , Md. Asaduzzaman","doi":"10.1016/j.ssel.2020.09.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.09.001","url":null,"abstract":"<div><p>A numerical simulation and substantiation have been accomplished to analyze the impact of Al<sub>0.9</sub>Ga<sub>0.1</sub>As alloy composite buffer layer band gap and thickness, absorber layer thickness on a ZnO:Al/i-ZnO/Al<sub>0.9</sub>Ga<sub>0.1</sub>As/CIGS/Mo/SLG structured non-toxic Cd-free CIGS photovoltaic cell. In this study, the cell output attributes including efficiency (η) and collection efficiency (η<sub>c</sub>) have been optimized through short circuit current density (J<sub>sc</sub>), open-circuit voltage (V<sub>oc</sub>) and fill factor (FF) optimization. Our study has been concluded with the maximum efficiency of 24.32% with <em>V</em><sub><em>oc</em></sub> = 839.76 mV, <em>J<sub>sc</sub></em> = 36.21mA/cm<sup>2</sup> and <em>FF</em>=76.96%, η<sub><em>c</em></sub> = 83.16%. This enhanced efficiency is optimized by determining the bandgap of the buffer through altering the Al concentration to transit it from direct bandgap material to an indirect one. The thickness of the absorber on system performance is also investigated, and its extent is found in between 2 µm to 3 µm.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 103-108"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.09.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.08.002
M. Obradov, Z. Jakšić, D. Tanasković, O. Jakšić, D. Vasiljević Radović
Plasmonic metamaterials open a pathway to a multitude of different applications, from ultrasensitive sensors to merging the packaging density of electronics and the speed of photonics in a single all-optical device. A severe limitation to their wider use is high absorption due to the mandatory presence of free electron-containing conductive parts which are lossy by definition. In this contribution we consider an alternative solution in the form of ultrathin silicon films deposited on a silica substrate. The films are patterned as arrays of elongated rhombuses acting as bowtie nanoantennas. We consider the effect of sharp tips and the proximity effect on the electromagnetic field concentration in such low-loss metasurfaces. Our structures have the advantage of very low absorption losses with an order of magnitude field enhancement and the virtue of full compatibility with the standard planar technologies. This makes them convenient for various practical applications which integrate high field concentration with e.g. waveguiding properties, for instance microreactors, labs-on-a-chip, photocatalytic systems and various other Micro-Opto-Electro-Mechanical System (MOEMS) devices integrating optical, microfluidic and other functionalities.
{"title":"Optical field concentrator with low absorption metasurfaces based on planar silicon nanoantennas on silica","authors":"M. Obradov, Z. Jakšić, D. Tanasković, O. Jakšić, D. Vasiljević Radović","doi":"10.1016/j.ssel.2020.08.002","DOIUrl":"10.1016/j.ssel.2020.08.002","url":null,"abstract":"<div><p>Plasmonic metamaterials open a pathway to a multitude of different applications, from ultrasensitive sensors to merging the packaging density of electronics and the speed of photonics in a single all-optical device. A severe limitation to their wider use is high absorption due to the mandatory presence of free electron-containing conductive parts which are lossy by definition. In this contribution we consider an alternative solution in the form of ultrathin silicon films deposited on a silica substrate. The films are patterned as arrays of elongated rhombuses acting as bowtie nanoantennas. We consider the effect of sharp tips and the proximity effect on the electromagnetic field concentration in such low-loss metasurfaces. Our structures have the advantage of very low absorption losses with an order of magnitude field enhancement and the virtue of full compatibility with the standard planar technologies. This makes them convenient for various practical applications which integrate high field concentration with e.g. waveguiding properties, for instance microreactors, labs-on-a-chip, photocatalytic systems and various other Micro-Opto-Electro-Mechanical System (MOEMS) devices integrating optical, microfluidic and other functionalities.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 55-58"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.08.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79174599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.12.003
NamChol Yu , JuSong Kim , Yong Ho Li , Song Chol Pak
A new 3D finite element model to characterize the residual stress distribution in multilayer NTC thermistor during soldering process has been developed. During the soldering process, the effects of inner silver electrode number and lateral margin length on mechanical residual stress are studied. Throughout the weldbonding and heating process, the maximum and minimum principal stresses in the active region of the thermistor ceramic are not zero, which implies that most of the thermistor ceramic is not stress-free. Numerical results show that the increasing of the lateral margin length could effectively decrese the maximum tensile stress.
{"title":"The Simulation Study on Internal Stress in Multilayer Thermistors during Soldering Process","authors":"NamChol Yu , JuSong Kim , Yong Ho Li , Song Chol Pak","doi":"10.1016/j.ssel.2020.12.003","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.12.003","url":null,"abstract":"<div><p>A new 3D finite element model to characterize the residual stress distribution in multilayer NTC thermistor during soldering process has been developed. During the soldering process, the effects of inner silver electrode number and lateral margin length on mechanical residual stress are studied. Throughout the weldbonding and heating process, the maximum and minimum principal stresses in the active region of the thermistor ceramic are not zero, which implies that most of the thermistor ceramic is not stress-free. Numerical results show that the increasing of the lateral margin length could effectively decrese the maximum tensile stress.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 124-128"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.12.003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90131482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.10.001
Abhijeet Barua , Kevin D. Leedy , Rashmi Jha
This study reports the deep subthreshold characteristics (≤1 V) of low thermal budget Indium Gallium Zinc Oxide (IGZO) thin film transistors (TFTs) with Schottky barrier source/drain contacts. The Schottky barrier was analyzed and a consistent ideality factor was observed across the devices. A deep subthreshold region was extracted from the nominal characteristics and barrier influence was observed in the low voltage region. This operation led to high output impedance (~1012Ω) and excellent trans-conductance leading to a high voltage gain (>100) due to hard saturation of the output characteristics. Positive bias stress and stability tests were conducted within this region that showed minimal drift in the transfer characteristics. Such characteristics make these devices an excellent choice for low-power deep subthreshold and weak signal applications.
{"title":"Deep-subthreshold Schottky barrier IGZO TFT for ultra low-power applications","authors":"Abhijeet Barua , Kevin D. Leedy , Rashmi Jha","doi":"10.1016/j.ssel.2020.10.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.10.001","url":null,"abstract":"<div><p>This study reports the deep subthreshold characteristics (≤1 V) of low thermal budget Indium Gallium Zinc Oxide (IGZO) thin film transistors (TFTs) with Schottky barrier source/drain contacts. The Schottky barrier was analyzed and a consistent ideality factor was observed across the devices. A deep subthreshold region was extracted from the nominal characteristics and barrier influence was observed in the low voltage region. This operation led to high output impedance (~10<sup>12</sup>Ω) and excellent trans-conductance leading to a high voltage gain (>100) due to hard saturation of the output characteristics. Positive bias stress and stability tests were conducted within this region that showed minimal drift in the transfer characteristics. Such characteristics make these devices an excellent choice for low-power deep subthreshold and weak signal applications.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 59-66"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.10.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90131484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.05.001
Samuel Husin Surya Mandala , Mochamad Januar , Bei Liu , Kou-Chen Liu
We proposed a design topology for a unipolar pulsed direct-current power supply to produce low-cost reactive plasma etcher system. The design was simulated by a block diagram method using the open-source software Scilab/Xcos, and the results were validated by prototyping the power supply. In the topology, the snubber circuit and the RLC circuit play a critical role in producing a smoother pulse waveform and regulating the characteristics of the plasma current. Their optimized parameters can provide well-controllable duty cycles in the voltage output of the power supply. Moreover, the effect of the duty cycles on the performance of the power supply is analyzed. We found that the duty cycle can adjust the transient response of the plasma current as well as the density of the plasma ions. This aspect is useful not only for reducing the arcing effect but also for modifying the surface wettability of the treated substrates. As a result, the glass substrates treated with a 100% duty cycle becomes more hydrophilic, while those treated with a 20% duty cycle tend to be more hydrophobic.
{"title":"Designing the Topology of a Unipolar Pulsed-DC Power Supply using the Open-source Scilab/Xcos Software for a Low-cost Plasma Etcher","authors":"Samuel Husin Surya Mandala , Mochamad Januar , Bei Liu , Kou-Chen Liu","doi":"10.1016/j.ssel.2020.05.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.05.001","url":null,"abstract":"<div><p>We proposed a design topology for a unipolar pulsed direct-current power supply to produce low-cost reactive plasma etcher system. The design was simulated by a block diagram method using the open-source software Scilab/Xcos, and the results were validated by prototyping the power supply. In the topology, the snubber circuit and the RLC circuit play a critical role in producing a smoother pulse waveform and regulating the characteristics of the plasma current. Their optimized parameters can provide well-controllable duty cycles in the voltage output of the power supply. Moreover, the effect of the duty cycles on the performance of the power supply is analyzed. We found that the duty cycle can adjust the transient response of the plasma current as well as the density of the plasma ions. This aspect is useful not only for reducing the arcing effect but also for modifying the surface wettability of the treated substrates. As a result, the glass substrates treated with a 100% duty cycle becomes more hydrophilic, while those treated with a 20% duty cycle tend to be more hydrophobic.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 35-43"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.05.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91761621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.11.001
Razvan Pascu
Capacitance-voltage measurements performed at cryogenic temperatures (14 – 500 K) have been used to determine the ultrashallow interface states in SiC MOS capacitors. These states occupies energy levels in SiC band gap on different energy levels up to 27 meV below the conduction band. Moreover, the capacitance-voltage characteristics are moving to lower voltages with temperature increasing, indicating a reduction in flat band voltage from 14.65 (14 K) to 2.77 V (500 K). It was demonstrated that a complete ionization of the nitrogen donors from the epitaxial layer occurs at 420 K. From these analysis, an activation energy of around 26.79 meV was determined. In order to determine the energy levels distribution of the interface states in SiC band gap, the Fermi level variation with temperature was calculated, starting from a value of around 27.1 meV at 14 K and reaching a value of 321 meV at 500 K under SiC conduction band. Six peaks (D1 – D6) have been identified in interface states density distribution at different levels of energy in SiC band gap, which could correspond to different defects at the SiO2/SiC interface.
{"title":"Ultrashallow defects in SiC MOS capacitors","authors":"Razvan Pascu","doi":"10.1016/j.ssel.2020.11.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.001","url":null,"abstract":"<div><p>Capacitance-voltage measurements performed at cryogenic temperatures (14 – 500 K) have been used to determine the ultrashallow interface states in SiC MOS capacitors. These states occupies energy levels in SiC band gap on different energy levels up to 27 meV below the conduction band. Moreover, the capacitance-voltage characteristics are moving to lower voltages with temperature increasing, indicating a reduction in flat band voltage from 14.65 (14 K) to 2.77 V (500 K). It was demonstrated that a complete ionization of the nitrogen donors from the epitaxial layer occurs at 420 K. From these analysis, an activation energy of around 26.79 meV was determined. In order to determine the energy levels distribution of the interface states in SiC band gap, the Fermi level variation with temperature was calculated, starting from a value of around 27.1 meV at 14 K and reaching a value of 321 meV at 500 K under SiC conduction band. Six peaks (D<sub>1</sub> – D<sub>6</sub>) have been identified in interface states density distribution at different levels of energy in SiC band gap, which could correspond to different defects at the SiO<sub>2</sub>/SiC interface.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 79-84"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.11.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.11.003
P. Pascariu , I.V. Tudose , D. Vernardou , E. Koudoumas , O.N. Ionescu , S. Bucur , M. Suchea
This short letter reports the achievement of promising sensing properties by using pure and Ni doped SnO2-Polythiophene nanostructured materials. These nanocomposites of SnO2 (undoped and doped with Ni) and polythiophene (PTh) were synthesized by electrochemical oxidative polymerization of thiophene in the presence of the two types of nanoparticles obtained by co‐precipitation. The as obtained materials were used as active layer in sensing devices. The nanocomposites were structurally characterized and their electrochemical properties were evaluated by cyclic voltammetry. The nanocomposites conductivity variation with temperature was studied in air and then were exposed to different pollutant gases to investigate the composites suitability for gas sensing applications, which prove to be promising materials.
{"title":"SnO2 and Ni doped SnO2 /polythiophene nanocomposites for gas sensing applications","authors":"P. Pascariu , I.V. Tudose , D. Vernardou , E. Koudoumas , O.N. Ionescu , S. Bucur , M. Suchea","doi":"10.1016/j.ssel.2020.11.003","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.003","url":null,"abstract":"<div><p>This short letter reports the achievement of promising sensing properties by using pure and Ni doped SnO<sub>2</sub>-Polythiophene nanostructured materials. These nanocomposites of SnO<sub>2</sub> (undoped and doped with Ni) and polythiophene (PTh) were synthesized by electrochemical oxidative polymerization of thiophene in the presence of the two types of nanoparticles obtained by co‐precipitation. The as obtained materials were used as active layer in sensing devices. The nanocomposites were structurally characterized and their electrochemical properties were evaluated by cyclic voltammetry. The nanocomposites conductivity variation with temperature was studied in air and then were exposed to different pollutant gases to investigate the composites suitability for gas sensing applications, which prove to be promising materials.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 85-91"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.11.003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper illustrates a novel design of voltage-mode integrator using the active element, namely voltage difference transconductance amplifier (VDTA). The proposed circuit only requires one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 μA. And also, the transconductance (gm) is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are functionally verified through experiment with the commercially available ICs LM13700. The proposed VDTA based integrator is highly useful in the dual slope/integrating type analogue to digital converters for higher resolutions.
{"title":"Corrigendum to: An Integrator Circuit Using Voltage Difference Transconductance Amplifier","authors":"Kaza Malathi Santhoshini , Sarada Musala , Avireni Srinivasulu","doi":"10.1016/j.ssel.2020.12.002","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.12.002","url":null,"abstract":"<div><p>This paper illustrates a novel design of voltage-mode integrator using the active element, namely voltage difference transconductance amplifier (VDTA). The proposed circuit only requires one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 μA. And also, the transconductance (g<sub>m</sub>) is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are functionally verified through experiment with the commercially available ICs LM13700. The proposed VDTA based integrator is highly useful in the dual slope/integrating type analogue to digital converters for higher resolutions.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 109-114"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.12.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.11.004
Wing-Kong Ng, Wing-Shan Tam, C. Kok
{"title":"Low power frequency doubler","authors":"Wing-Kong Ng, Wing-Shan Tam, C. Kok","doi":"10.1016/j.ssel.2020.11.004","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.004","url":null,"abstract":"","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"36 1","pages":"98-102"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81148558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-01DOI: 10.1016/j.ssel.2020.11.004
Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok
A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply voltage variations with excellent frequency and phase performance on high frequency clock generation.
{"title":"Low power frequency doubler","authors":"Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok","doi":"10.1016/j.ssel.2020.11.004","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.11.004","url":null,"abstract":"<div><p>A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply voltage variations with excellent frequency and phase performance on high frequency clock generation.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 98-102"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.11.004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}