Solid State Electronics Letters最新文献

Resistive RAM (Random Access Memory) has good scalability with high switching speed and low operating voltage making it one of the promising emerging nonvolatile memory technologies. Interfacial layer between the electrode and metal-oxide interface in a Resistive RAM (ReRAM) could either enhance or deteriorate the switching performance of the device. In this study, we investigate the role of aluminum (Al) as an interfacial layer under the top electrode (TE) layer in a niobium oxide (Nb₂O₅) based ReRAM. We compare the Current-Voltage (I-V), Capacitance-Voltage (C-V) characteristics and endurance of the Nb₂O₅ based ReRAM with an Al interfacial layer below the tungsten (W) TE and a control sample without the Al interfacial layer to contrast the performance of each type. Additionally, we connect the tested device behavior with the enthalpy, entropy, and Gibb's free energy to illustrate that aluminum is an inefficient interfacial layer in the niobium oxide ReRAM.

Presently, computer scientists and researchers show greater interest in one of the ancient techniques, namely, Residue Number System (RNS) to use in different fields. In this paper, an introduction to RNS and Modular adders, their overview and detailed explanation are presented. In the RNS system, conventional data is encoded to RNS data in the first stage referred to as forward conversion. Later the reverse conversion is needed which decodes RNS data to conventional data. Among the conversions, the reverse conversion is more complex over the forward conversion. The decoding process can however be performed by availing the Chinese Remainder Theorem (CRT) or Mixed Radix Conversion (MRC) technique. In RNS applications such as modular multipliers, digital signal processing (DSP) applications, residue to binary converters, etc. The crucial component was modular adders, so that some of the modular adders are presented at the end of this paper.

Understanding the failure mechanisms is essential to ensure reliability for a new technology of semiconductors. Amongst various existing tools dedicated to silicon-based devices, there is no consensual method for silicon carbide (SiC) devices. This semiconductor offers very interesting properties for power electronics in comparison with Si, but these failures are different and need to be studied. This paper will compare different methods applied to failures, focusing on lock-in thermography and micro-Raman analysis. Three devices will be evaluated, a vertical diode, a lateral diode and a MESFET. A methodology will finally be recommended as a valuable and robust solution for failures mechanisms further studies.

Power dissipation obstacle in electronic devices is strongly related to their internal breakdown mechanism. The Static Induction Transistor optimization imposes to reach p-gate regions as deep as vertical as possible. These objectives can be achieved using Selective Epitaxial Growth technology, so that the final structure between Gate and Drain becomes Silicon On Insulator. In addition the insulator is thin enough, it allows the vertical Gate–Drain breakdown, by a parasite planar variant of the Nothing On Insulator structure. Other papers have been presented Nothing On Insulator alternative structures alone for useful or non-parasitic applications. At this movement, the Nothing On Insulator structure has another role to play. It is the main parasitic device prevailing inside the Static Induction Transistor that must be avoided. The paper presents analytical models and simulation results for the potential distribution in a Gate–Drain cross-section. A breakdown regime is established for the Static Induction Transistor, with breakdown voltages between 313 V and 430 V, based on the planar-Nothing On Insulator theory.

In this paper, we proposed a 2 dimensional model of tripple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-junction formed by germanium and silicon materials in the source-channel junction and heterodielectric gate stack is used with Silicon Dioxide (SiO₂) and Hafnium Dioxide (HfO₂) as dielectric materials. The electrical characteristics like surface potential, electric field, drain current and transconductance are demonstrated for the device by using commercially available 2D numerical device simulator Silvaco TCAD ATLAS. The variation of the drain currnet or ON current with the varying channel length (L), doping concentration of drain and source (N_A and N_D), thickness of device (t_si) and effective oxide layer thickness (t_ox) of the device is evaluated and presented. It is demonstrated that the proposed TM-DG TFET structure has better performance than single material and double material TFET. The proposed model shows a lower ambipolar current and a better I_ON/I_OFF ratio. Moreover, the influence of Germanium/Silicon hetero-junction has reduces the tunneling barrier width is exactly depicted. Hence the ON current (10⁻³A) of the proposed device is improved at the level of CMOS transistors.

The conventional first order piezoresistance model has commonly been used to describe carrier mobility enhancement for low levels of process induced stress in Complementary Metal-Oxide-Semiconductor Field Effect Transistor (CMOS) technology. However, many reports show it failing to describe the nonlinear behavior observed at high levels of stress. In this paper, mobility model based on the modified piezoresistance model with nine stress-independent piezoresistance coefficients is proposed such that a mobility model can be applied correctly to calculate the strain-induced carrier mobility changes. Hence, the overall accuracy is improved compared to the conventional piezoresistance (PR) model. Its validation is confirmed with the results from TCAD simulations of carrier mobility for Ge Fin Field Effect Transistors (FinFET) and nanowire transistors.

In this paper Z-Copy Current Differencing Buffered Amplifier (ZCCDBA) based new Schmitt trigger is introduced without passive components. This ZCCDBA is a newly introduced active element. It consists of three blocks, namely, Current Differencing Unit (CDU), Voltage Buffer and Third Generation Current Conveyor (CCIII+). The CCIII purpose is to copy the Z terminal voltage and current. The proposed Schmitt trigger consists of a single ZCCDBA block without passive components. This type of configuration helps and suits for IC implementation. The proposed circuit was simulated under ±0.8 V supply voltage with the bias currents such as I_B1 = I_B2 = 60 µA and I_B3 = 10 µA using Cadence tool and with model parameters of gpdk 180 nm technology.

Carrier dynamics in GaAs_1-xSb_x/GaAs single quantum well (SQW) is investigated in this report. With Sb incorporation (x = 0.352, 0.405), the photoluminescence (PL) emission peaks exhibit characteristics of GaAs_1-xSb_x in low temperature and GaAs above 200 K. In power dependent PL, the intensities reveal sublinear power relationship as localized and free excitons are involved at 10 K. The power exponent is in agreement with the degree of localization energy present in SQW and carrier kinetics for various recombination mechanisms are also discussed by deriving respective rate equations.

An improved digital open drain output buffer is designed in a 0.18µm CMOS process. The circuit can operate in a wide range of power supply voltages, from 1.5V to 5.6V. This output buffer is used in an I²C High Speed Interface, allowing for a transmission rate of 3.4 Mbps, with a data hold time of 39.4ns at 1.5V, and 30.4ns at 5.6V. This interface is implemented in a digital temperature sensor. These performances were achieved through topology changes to a classic digital output buffer. The proposed circuit achieves a two times faster response time when transmitting data from the sensor, compared to the standard topology.

In this paper a Voltage Differencing Transconductance Amplifier (VDTA) based Voltage Mode (VM) Multi Input Single Output (MISO) Fractional Order filter (FOF) providing all five filter responses is presented. The proposed FOF is designed using single VDTA and two fractional Capacitors (FC). The FC is implemented using RC ladder network; component values of which are computed using Carlson rational approximation. For illustration, FC of 0.5 order has been implemented using first, second and third iterations of Carlson approximation, which results in different integer order approximation functions. The ladder component values for all iterations are computed using MATLAB. The effect of different iterations on FOF behavior is also studied. The proposed FOF is verified through Cadence Virtuoso simulations using 0.18 µm CMOS technology.