Solid State Electronics Letters最新文献

650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (R_on,sp) of 2.06 mΩ · cm² (further reducible through tighter layout design) while having a narrow JFET region for device reliability.

A double edge-triggered D-type flip flop includes a half-static clock gating circuit is presented in this paper. Two dynamic latches that each responses to the rising and falling edges of the gated clock are connected in parallel to a half-static latch, which captures the data signal in response to both rising and falling edges of the clock signal. This flip flop topology helps to improve the race tolerance, energy efficiency and circuit compactness. The flip flop is simulated with HSPICE using commercially 0.18 µm CMOS technology. The simulation results presented in this paper showed that it can achieve a 4 Gbits/sec data rate with 96% redundant power reduction when compared to other double edge-triggered D-type flip flop in literature.

This letter presents an implementation of a li-ion battery protector circuit making use of purely digital logic and resistive divider only, which results in a compact and energy efficient circuit. The presented design is capable to provide all protections, that is compatible with other commercially available li-ion battery protectors. In particular, a reset clock has been implemented to reset the protector circuit periodically when it enters into one of the hazardous protection state, which serves as an auto-recovery function to restore the battery protector to normal operation without external assistance. Finally, the reset clock can be overridden with an external test clock which helps to reduce the test time of the integrated circuit in wafer level during mass production. The performance of the proposed circuit is validated by implementing the circuit on FPGA with external resistors, which further confirms that the fabrication of the proposed circuit on silicon is feasible.

In this work, a double gate junction-less tunnel FET (DG-JLTFET) has been evaluated for biosensing applications. Tunnelling is the concept in JLTFET which is a heavily doped JL transistor, by decreasing the barrier length between the source and channel of the device which is easily used for switching (ON and OFF) purpose. Based on the research and simulation so far on JLTFET, this has achieved a greater performance when compared to that of MOSFET. JLTFET with more dielectric (k) and low K spacers will give an ON current (0.1 mA/µm) for gate voltage 3V and for off current of (10⁻¹⁵ A/ µm) and performance with I_on/I_off ratio at 10¹² and subthreshold swing with 60 mV/dec is obtained at 20 nm length of the gate at room temperature. So, JLTFET is a better device for switching performance. The evaluation of device performance is also done based on different cavity thicknesses and different dielectric constants. Including these parameters, double gate-pocket-junction-less TFET is highly used in biosensor applications. In the following, we demonstrate high performance based on pocket region which is introduced to implement in JLTFET for biosensor label-free detection

In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) $\Delta \Sigma$ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.

In this paper, we report the Fe doped MoS₂ monolayer to improve the gas sensing properties. We investigated the electronic properties of Fe doped MoS₂ for sensing Urea and Methanol using Density Functional Theory (DFT). Non-Equilibrium Green's Function (NEGF) was used to calculate the transport properties of the aforementioned nanomaterials. The absorption energy, charge transfer, bandstructure, Density of States (DOS), Projected Density of States (PDOS), I-V characteristics, recovery time and sensitivity of urea and methanol gas molecules on Fe doped MoS₂ were all investigated. As a result, we observed the tremendous change in the electrical and chemical activity of Fe doped MoS₂ for the adsorption of urea and methanol. After the substitution of the Fe atom in the MoS₂ monolayer, the magnetic property was observed. In comparison to pristine MoS₂ and Fe doped MoS₂, the bandgap revealed an improvement in conduction property in adsorbed molecules. The outcome was also confirmed by DOS and PDOS. The Fe doped MoS₂ for urea and methanol adsorption, the I-V curve shows a linear increase in current for bias voltage up to 1.9 V, then a quick fall in current after increasing a few volts. The relative resistance state of the Fe doped MoS₂ based sensor is better, indicating that it can be used as a sensor. At 2 V, the sensitivity for methanol and urea was 82 % and 77.5 %, respectively. For the methanol configuration, the quicker desorption time was calculated to be 0.00015 µs. Our results demonstrate that Fe doped MoS₂ is a promising candidate for a low-cost, stable gas sensor.

This article presents a tutorial on the design of CMOS Class AB bridged audio amplifier. High power efficiency is achieved by using a bridged output stage. An added advantage of the bridged amplifier is that the output stage can operate without the use of any capacitor, which supports the circuit to be operated under single rail power supply. An example of 3 ${\text{W}}_{RMS}$ audio amplifier with $3\Omega$ load is presented in this tutorial together with detail analytical analysis to demonstrate how to design a similar CMOS audio amplifier. The design example is simulated with a commercial 0.5 $\mu$m CMOS process together with measurement results from fabricated silicon to sustain the presented design methodology. The fabricated amplifiers can achieve low quiescent power at 33 mW, and a wide peak-to-peak output voltage swing of 8.5 Vpp subject to a 5 V supply. The THD of the amplifier is measured to be smaller than 10$\%$.

It is expensive if not impossible to fabricate embedded resistors to the correct resistance value. Therefore, embedded resistor is often fabricated with a typical value and then use a post-fabrication trimming process to trim it to the desired value. This tutorial discusses how to set up the resistor network appropriately to achieve the desired resistance through trimming. The trimming strategy is studied analytically, with a number of variations in the trimming topologies. A voltage reference circuit is applied as the underneath application in this tutorial such as to provide more concrete discussions on the physical meaning of trimming accuracy.