Solid State Electronics Letters最新文献

As technological advancements are increasing in the world at a faster rate, the need of miniaturization is also growing parallelly. The scaling of existing MOS technology in nanometre regime has caused some limitations such as drastically increase in leakage current, power consumption and some quantum mechanical effects. This paper provides an insight of an alternative technology which makes use of new circuit element called memristor which can be successfully scaled at a lower nanometre regime. This paper proposes a new READ and WRITE circuitry to facilitate an easier read and write operation. The paper illustrates a transmission gate based 2T1M RRAM bit cell which uses memristor as a memory element and subjects it to process, voltage and temperature (PVT) variations with the aim of reflecting the improvement in performance metrices read and write delay along with the read current variability. The SPICE simulation results reflect that the proposed memory cell has a better stability due to its less read current variability against process variation (such as varying oxide thickness) and is robust with minimal variation in read/write delay with respect to the variations in voltage and temperature. The cell depicts shorter read and write delay compared to NAND and NOR CMOS based flash memories and it has 98.72%,94.53% lesser write time when compared to ambipolar transistor-based memory cell and memristor based content addressable memory (MCAM) respectively. The proposed cell also has 72.5% lesser read time compared to MCAM.

In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (I_D), transconductance (g_m), transconductance generation factor (TGF), intrinsic gain, output resistance (r_out), cut-off frequency, maximum frequency of oscillation (f_max) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.

The off-state breakdown voltage of a double-channel AlGaN/GaN HEMT is improved by employing an air-bridge field plate (AFP) and a slant field plate at the gate electrode. It has been observed that using the AFP only can reduce the peak electric field under the gate edge to a certain extent, and a slant field plate can be added to obtain an even better result. The breakdown voltage is increased from 19 V of the initial structure to 200 V of the optimized structure.

We report our simulation on the electric field effect of Bi thin film. Band diagram and carrier concentrations of the Bi channel at different surface potentials have been obtained by numerically solving Poisson's equation. In the calculation, the anisotropic characteristic of effective mass for carrier concentration and conductivity have been considered. The carrier densities were calculated from Fermi-Dirac integral. The conductivity effective mass ratio of electron and hole have been calculated to verify how the gate bias voltage affects the conductance of the Bi channel. The result shows that the Debye length in Bi is ~10 nm and nearly independent of the bias voltage. The dependency of conductance on gate bias is also discussed.

The current-voltage (I_D-V_D) characteristics of W/4H-SiC Schottky barrier diodes (SBDs) are investigated in the 303–448 K temperature range by means of a numerical simulation study. Results showed a good agreement with measurements for a bias current ranging from 100 nA up to 10 mA. The main device parameters, such as the barrier height and ideality factor are found strongly temperature-dependent. The observed behaviours are interpreted by using the thermionic emission (TE) theory with a single Gaussian distribution of the barrier height (BH). The corresponding Richardson constant is A* = 148.8 Acm⁻²K⁻². This value is close to the theoretical one of 146 Acm⁻²K⁻² for n-type 4H-SiC.

In this paper, a 5-bit 500MS/s flash analog-to-digital converter (ADC) with temperature-compensated inverter-based comparators is proposed. In the proposed ADC, a complementary-average system structure is adopted. Based on this structure, inverter-based comparators are used to reduce the power consumption. However, conventional inverter-based comparators suffer from switching threshold variation when the temperature changes, which degrades the SNDR performance of the whole ADC. To tackle this problem, a temperature-compensated inverter-based comparator is proposed. Furthermore, an encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors. To verify the proposed design, a prototype ADC is implemented in a 0.18 µm process. Measurements at room temperature show that the SNDR and SFDR of the proposed prototype are 29.6 dB and 34.92 dB, with a resulting ENOB of 4.62 bits. It achieves an DNL and INL of +0.33 LSB /−0.54 LSB and +0.27 LSB/−0.33 LSB, respectively, and consumes 6 mW from a 1.8-V supply. At 0 °C and 60 °C, the ADC maintains a close performance.

In this paper we simulated and investigated the device characteristics of a novel device structure derived from the junctionless (JL) gate-all-around (GAA) nanowire (NW) transistor, variable barrier transistor (VBT). Basically, VBT is accomplished by the local constrictions at both ends of the channel region of the JL GAA NW transistor. The device simulation is performed based on the non-equilibrium Green's function (NEGF) approach provided by the 3D TCAD device simulator, Atlas. The simulation results suggest the JL VBT can have larger ON/OFF current ratio than that of the JL GAA NW transistor as long as the constriction (or barrier) is properly designed.