Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931580
K. Fukuda, M. Nishizawa, T. Tada, L. Bolotov, Kaina Suzuki, Shigeo Sato, H. Arimoto, T. Kanayama
A three dimensional simulation system for light-illuminated STM measurements is proposed for the first time combining semiconductor process and device simulators with an FDTD solver. Photo-generation rates estimated from light intensity obtained from the FDTD solver are incorporated into a semiconductor device simulation of a device structure including a semiconductor sample and an STM probe tip. Tunneling currents between the STM probe and the sample are solved consistently with current continuity equations in the semiconductor sample. The usefulness of the proposed method is demonstrated through a case of UV-laser-illuminated STM measurement of a silicon nanowire.
{"title":"Simulation of light-illuminated STM measurements","authors":"K. Fukuda, M. Nishizawa, T. Tada, L. Bolotov, Kaina Suzuki, Shigeo Sato, H. Arimoto, T. Kanayama","doi":"10.1109/SISPAD.2014.6931580","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931580","url":null,"abstract":"A three dimensional simulation system for light-illuminated STM measurements is proposed for the first time combining semiconductor process and device simulators with an FDTD solver. Photo-generation rates estimated from light intensity obtained from the FDTD solver are incorporated into a semiconductor device simulation of a device structure including a semiconductor sample and an STM probe tip. Tunneling currents between the STM probe and the sample are solved consistently with current continuity equations in the semiconductor sample. The usefulness of the proposed method is demonstrated through a case of UV-laser-illuminated STM measurement of a silicon nanowire.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931550
K. Hamada
Due to the mass consumption of fossil fuels since the 20th century, the automotive industry is facing various issues, such as the depletion of fuel resources and worsening air quality. Power semiconductor devices can help to resolve these issues by facilitating the development of technologies to save energy and diversify fuel usage. This paper describes the requirements and outlook for power semiconductor devices. It also introduces an example of the adoption of technology computer aided design (TCAD) in power semiconductor device development.
{"title":"Challenge of adopting TCAD in the development of power semiconductor devices for automotive applications","authors":"K. Hamada","doi":"10.1109/SISPAD.2014.6931550","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931550","url":null,"abstract":"Due to the mass consumption of fossil fuels since the 20th century, the automotive industry is facing various issues, such as the depletion of fuel resources and worsening air quality. Power semiconductor devices can help to resolve these issues by facilitating the development of technologies to save energy and diversify fuel usage. This paper describes the requirements and outlook for power semiconductor devices. It also introduces an example of the adoption of technology computer aided design (TCAD) in power semiconductor device development.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931553
C. Sampedro, L. Donetti, F. Gámiz, A. Godoy, F. J. García-Ruiz, V. Georgiev, S. Amoroso, C. Riddet, E. Towie, A. Asenov
In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB-EMC transport engine for a 1D electron gas with a 3DPoisson-2DSchrödinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the applicability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Green's Functions (NEGFs) in the ballistic limit is used to verify and validate our approach.
{"title":"3D multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors","authors":"C. Sampedro, L. Donetti, F. Gámiz, A. Godoy, F. J. García-Ruiz, V. Georgiev, S. Amoroso, C. Riddet, E. Towie, A. Asenov","doi":"10.1109/SISPAD.2014.6931553","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931553","url":null,"abstract":"In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB-EMC transport engine for a 1D electron gas with a 3DPoisson-2DSchrödinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the applicability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Green's Functions (NEGFs) in the ballistic limit is used to verify and validate our approach.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116045418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931636
F. Pittino, L. Selmi
We describe a technique to overcome the numerical difficulties in the accurate description of the small signal AC response of the thin electrical double layers at the surface of impedimetric biosensor electrodes. The technique significantly reduces the computational burden of the calculation, thus enabling the fast simulation of many analyte configurations.
{"title":"A technique to model the AC response of diffuse layers at electrode/electrolyte interfaces and to efficiently simulate impedimetric biosensor arrays for many analyte configurations","authors":"F. Pittino, L. Selmi","doi":"10.1109/SISPAD.2014.6931636","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931636","url":null,"abstract":"We describe a technique to overcome the numerical difficulties in the accurate description of the small signal AC response of the thin electrical double layers at the surface of impedimetric biosensor electrodes. The technique significantly reduces the computational burden of the calculation, thus enabling the fast simulation of many analyte configurations.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122169841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931551
M. Stettler
Embedding TCAD engineers in technology working groups has been an integral part of Intel's process development strategy since the company's inception. While this strategy remains the same, the challenges faced and the tools used by TCAD has undergone dramatic change over the last 20 years. This talk will discuss three recent trends in process and device TCAD: the rise in the use of “atomistic” scale simulations, the focus on modeling defects, and the continuing need to bridge new, more physically rigorous approaches to older, more computationally efficient methods. These trends will be illustrated with recent TCAD studies conducted at Intel.
{"title":"Device and process modeling: 20 Years at Intel's other fab","authors":"M. Stettler","doi":"10.1109/SISPAD.2014.6931551","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931551","url":null,"abstract":"Embedding TCAD engineers in technology working groups has been an integral part of Intel's process development strategy since the company's inception. While this strategy remains the same, the challenges faced and the tools used by TCAD has undergone dramatic change over the last 20 years. This talk will discuss three recent trends in process and device TCAD: the rise in the use of “atomistic” scale simulations, the focus on modeling defects, and the continuing need to bridge new, more physically rigorous approaches to older, more computationally efficient methods. These trends will be illustrated with recent TCAD studies conducted at Intel.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115645598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931559
O. Cueto, A. Payet, T. Cabout
An electro-thermal resistive switching model based on O-Frenkel pairs is presented. This model relies on partial differential equations and is used to simulate reset and set mechanisms for HfO2-based RRAM devices starting from an existing conductive filament. First simulations indicate that the model can fairly reproduce experimental ON and OFF resistances.
{"title":"Development of an electro-thermal resistive switching model based on O-Frenkel pairs to study reset and set mechanisms in HfO2-based RRAM cells","authors":"O. Cueto, A. Payet, T. Cabout","doi":"10.1109/SISPAD.2014.6931559","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931559","url":null,"abstract":"An electro-thermal resistive switching model based on O-Frenkel pairs is presented. This model relies on partial differential equations and is used to simulate reset and set mechanisms for HfO2-based RRAM devices starting from an existing conductive filament. First simulations indicate that the model can fairly reproduce experimental ON and OFF resistances.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121266147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931608
P. Lin, Zhe-An Andy Lee, C. Yao, Hsin-Jyun Lin, Hiroshi Watanabe
If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.
{"title":"Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise","authors":"P. Lin, Zhe-An Andy Lee, C. Yao, Hsin-Jyun Lin, Hiroshi Watanabe","doi":"10.1109/SISPAD.2014.6931608","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931608","url":null,"abstract":"If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131020442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931611
N. Seoane, M. Aldegunde, K. Kalna, A. García-Loureiro
The on- and off-current variability due to TiN metal grain workfunction fluctuations in a 10.4 nm gate length In0.53Ga0.47As FinFET is analysed using two in-house simulation tools based on the finite element method: a 3D Drift-Diffusion device simulator and a 3D ensemble Monte Carlo simulator, that include quantum-corrections through the density gradient approach. The Id-Vg characteristics have been compared in the sub-threshold region against ballistic NEGF simulations, showing an excellent agreement. Monte Carlo simulations, considering a 〈100〉 channel orientation, show a larger on-current variability, over a 120% increase, compared with the results from Drift-Diffusion simulations. In this study, three different metal grain sizes (10, 7 and 5 nm) have been analysed. We have observed that the underestimation of the variability when using Drift-Diffusion simulations is increasing with a reduction in the grain size.
{"title":"MC/DD study of metal grain induced current variability in a nanoscale InGaAs FinFET","authors":"N. Seoane, M. Aldegunde, K. Kalna, A. García-Loureiro","doi":"10.1109/SISPAD.2014.6931611","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931611","url":null,"abstract":"The on- and off-current variability due to TiN metal grain workfunction fluctuations in a 10.4 nm gate length In0.53Ga0.47As FinFET is analysed using two in-house simulation tools based on the finite element method: a 3D Drift-Diffusion device simulator and a 3D ensemble Monte Carlo simulator, that include quantum-corrections through the density gradient approach. The Id-Vg characteristics have been compared in the sub-threshold region against ballistic NEGF simulations, showing an excellent agreement. Monte Carlo simulations, considering a 〈100〉 channel orientation, show a larger on-current variability, over a 120% increase, compared with the results from Drift-Diffusion simulations. In this study, three different metal grain sizes (10, 7 and 5 nm) have been analysed. We have observed that the underestimation of the variability when using Drift-Diffusion simulations is increasing with a reduction in the grain size.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132446064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931639
K. Rupp, M. Bina, Y. Wimmer, A. Jungel, T. Crasser
Although the traditional finite volume scheme based on boxes obtained from the dual Voronoi grid has been employed successfully for classical semiconductor device simulation for decades, certain drawbacks such as the required Delaunay property of the underlying mesh limit its applicability for two-and particularly three-dimensional device simulations on unstructured meshes. We propose a discretization based on mesh cells rather than dual boxes around vertices, which circumvents the Delaunay requirement, yet preserves all the important features of the traditional method such as exact current conservation. The applicability of our method is demonstrated for classical and semiclassical models to tackle current engineering problems: We consider three-dimensional drift-diffusion simulations of geometric variations of the fin in a FinFET and present results from spatially two-dimensional simulations of a high-voltage nLDMOS device based on spherical harmonics expansions for direct solutions of the Boltzmann transport equation.
{"title":"Cell-centered finite volume schemes for semiconductor device simulation","authors":"K. Rupp, M. Bina, Y. Wimmer, A. Jungel, T. Crasser","doi":"10.1109/SISPAD.2014.6931639","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931639","url":null,"abstract":"Although the traditional finite volume scheme based on boxes obtained from the dual Voronoi grid has been employed successfully for classical semiconductor device simulation for decades, certain drawbacks such as the required Delaunay property of the underlying mesh limit its applicability for two-and particularly three-dimensional device simulations on unstructured meshes. We propose a discretization based on mesh cells rather than dual boxes around vertices, which circumvents the Delaunay requirement, yet preserves all the important features of the traditional method such as exact current conservation. The applicability of our method is demonstrated for classical and semiclassical models to tackle current engineering problems: We consider three-dimensional drift-diffusion simulations of geometric variations of the fin in a FinFET and present results from spatially two-dimensional simulations of a high-voltage nLDMOS device based on spherical harmonics expansions for direct solutions of the Boltzmann transport equation.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"377 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124708956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931632
Min-Chul Park, G. Yang, Joon-Sung Yang, Keun-Ho Lee, Young-Kwan Park
Device and circuit lifetime is investigated for poly silicon gated MOSFET. New findings are: (1) More than 1 order lifetime is increased by quantifying the influence of poly depletion effect (PDE) and accumulated trap charge effect (ATCE). (2) We demonstrate that conventional lifetime model produce an incorrect and reverse lifetime result for each degradation data measured by fast and slow method. (3) We evaluate the impact on circuit parameter, propagation delay time (tPD), degradation in the light of new findings.
{"title":"New perspective on lifetime prediction approach for BTI and HCI stressed device and its impact on circuit lifetime","authors":"Min-Chul Park, G. Yang, Joon-Sung Yang, Keun-Ho Lee, Young-Kwan Park","doi":"10.1109/SISPAD.2014.6931632","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931632","url":null,"abstract":"Device and circuit lifetime is investigated for poly silicon gated MOSFET. New findings are: (1) More than 1 order lifetime is increased by quantifying the influence of poly depletion effect (PDE) and accumulated trap charge effect (ATCE). (2) We demonstrate that conventional lifetime model produce an incorrect and reverse lifetime result for each degradation data measured by fast and slow method. (3) We evaluate the impact on circuit parameter, propagation delay time (tPD), degradation in the light of new findings.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124682538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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