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2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)最新文献

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Simulation of light-illuminated STM measurements 光照STM测量的仿真
K. Fukuda, M. Nishizawa, T. Tada, L. Bolotov, Kaina Suzuki, Shigeo Sato, H. Arimoto, T. Kanayama
A three dimensional simulation system for light-illuminated STM measurements is proposed for the first time combining semiconductor process and device simulators with an FDTD solver. Photo-generation rates estimated from light intensity obtained from the FDTD solver are incorporated into a semiconductor device simulation of a device structure including a semiconductor sample and an STM probe tip. Tunneling currents between the STM probe and the sample are solved consistently with current continuity equations in the semiconductor sample. The usefulness of the proposed method is demonstrated through a case of UV-laser-illuminated STM measurement of a silicon nanowire.
首次提出了一种将半导体工艺和器件模拟器与FDTD求解器相结合的光导STM测量三维仿真系统。从时域有限差分求解器获得的光强度估计的光产生率被合并到包括半导体样品和STM探针尖端的器件结构的半导体器件模拟中。用半导体样品中的电流连续性方程求解了STM探针与样品之间的隧道电流。通过紫外激光照射下硅纳米线的STM测量实例证明了该方法的有效性。
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引用次数: 1
Challenge of adopting TCAD in the development of power semiconductor devices for automotive applications 采用TCAD开发汽车用功率半导体器件所面临的挑战
K. Hamada
Due to the mass consumption of fossil fuels since the 20th century, the automotive industry is facing various issues, such as the depletion of fuel resources and worsening air quality. Power semiconductor devices can help to resolve these issues by facilitating the development of technologies to save energy and diversify fuel usage. This paper describes the requirements and outlook for power semiconductor devices. It also introduces an example of the adoption of technology computer aided design (TCAD) in power semiconductor device development.
由于20世纪以来化石燃料的大量消耗,汽车工业面临着各种问题,如燃料资源的枯竭和空气质量的恶化。功率半导体器件可以帮助解决这些问题,通过促进技术的发展,以节省能源和多样化的燃料使用。本文阐述了对功率半导体器件的要求和展望。并介绍了在功率半导体器件开发中采用计算机辅助设计技术的一个实例。
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引用次数: 1
3D multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors 三维多子带集成蒙特卡罗模拟finfet和纳米线晶体管
C. Sampedro, L. Donetti, F. Gámiz, A. Godoy, F. J. García-Ruiz, V. Georgiev, S. Amoroso, C. Riddet, E. Towie, A. Asenov
In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB-EMC transport engine for a 1D electron gas with a 3DPoisson-2DSchrödinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the applicability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Green's Functions (NEGFs) in the ballistic limit is used to verify and validate our approach.
在本文中,我们提出了一个三维多子带集成蒙特卡罗(3DMSB-EMC)工具的开发,目标是模拟纳米级finfet和纳米线晶体管。为了提高计算效率,我们开发了一个自一致的框架,将用于一维电子气体的MSB-EMC传输引擎与3DPoisson-2DSchrödinger求解器耦合在一起。在这里,我们使用一个物理通道长度为15nm的FinFET作为示例来演示该仿真框架的适用性并突出其优点。用3DMSB-EMC与非平衡格林函数(negf)在弹道极限下的比较验证了我们的方法。
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引用次数: 13
A technique to model the AC response of diffuse layers at electrode/electrolyte interfaces and to efficiently simulate impedimetric biosensor arrays for many analyte configurations 一种模拟电极/电解质界面上扩散层交流响应的技术,并有效地模拟许多分析物配置的阻抗生物传感器阵列
F. Pittino, L. Selmi
We describe a technique to overcome the numerical difficulties in the accurate description of the small signal AC response of the thin electrical double layers at the surface of impedimetric biosensor electrodes. The technique significantly reduces the computational burden of the calculation, thus enabling the fast simulation of many analyte configurations.
我们描述了一种克服精确描述阻抗生物传感器电极表面薄双电层的小信号交流响应的数值困难的技术。该技术大大减少了计算的计算负担,从而能够快速模拟许多分析物结构。
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引用次数: 2
Device and process modeling: 20 Years at Intel's other fab 器件和工艺建模:在英特尔其他工厂工作了20年
M. Stettler
Embedding TCAD engineers in technology working groups has been an integral part of Intel's process development strategy since the company's inception. While this strategy remains the same, the challenges faced and the tools used by TCAD has undergone dramatic change over the last 20 years. This talk will discuss three recent trends in process and device TCAD: the rise in the use of “atomistic” scale simulations, the focus on modeling defects, and the continuing need to bridge new, more physically rigorous approaches to older, more computationally efficient methods. These trends will be illustrated with recent TCAD studies conducted at Intel.
自英特尔公司成立以来,在技术工作组中嵌入TCAD工程师一直是英特尔工艺开发战略的一个组成部分。虽然这一策略保持不变,但在过去20年里,TCAD面临的挑战和使用的工具发生了巨大变化。本次演讲将讨论过程和设备TCAD的三个最新趋势:“原子”尺度模拟的使用增加,对建模缺陷的关注,以及将新的、更严格的物理方法与旧的、更计算高效的方法连接起来的持续需求。这些趋势将在英特尔最近进行的TCAD研究中得到说明。
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引用次数: 2
Development of an electro-thermal resistive switching model based on O-Frenkel pairs to study reset and set mechanisms in HfO2-based RRAM cells 基于O-Frenkel对的电热电阻开关模型的建立,用于研究hfo2基RRAM电池的复位和设置机制
O. Cueto, A. Payet, T. Cabout
An electro-thermal resistive switching model based on O-Frenkel pairs is presented. This model relies on partial differential equations and is used to simulate reset and set mechanisms for HfO2-based RRAM devices starting from an existing conductive filament. First simulations indicate that the model can fairly reproduce experimental ON and OFF resistances.
提出了一种基于O-Frenkel对的电热电阻开关模型。该模型依赖于偏微分方程,并用于模拟从现有导电灯丝开始的基于hfo2的RRAM器件的复位和设置机制。仿真结果表明,该模型能较好地再现实验ON和OFF电阻。
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引用次数: 1
Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise 具有陷阱辅助隧道和随机电报噪声的纳米尺度栅区高k介电体
P. Lin, Zhe-An Andy Lee, C. Yao, Hsin-Jyun Lin, Hiroshi Watanabe
If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.
如果陷阱密度为1012 cm-2,则平均在10nm × 10nm内只有一个陷阱。因此,对单电子运动敏感的三维模拟对于仔细研究未来纳米电子器件中局部陷阱的可靠性问题是必不可少的。为了证明这一点,我们在5nm×5nm栅极区高k电介质(EOT= 0.8nm至0.47nm)中同时研究了随机电报噪声(RTN)和陷阱辅助隧道(TAT)。对各种栅极偏置、高k物理厚度、层间亚氧化物厚度和高k介电常数进行了模拟。建议采用更薄的亚氧化物和更高的介电常数可以抑制TAT引起的泄漏电流的增加。
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引用次数: 0
MC/DD study of metal grain induced current variability in a nanoscale InGaAs FinFET 纳米InGaAs FinFET中金属晶粒诱导电流变异性的MC/DD研究
N. Seoane, M. Aldegunde, K. Kalna, A. García-Loureiro
The on- and off-current variability due to TiN metal grain workfunction fluctuations in a 10.4 nm gate length In0.53Ga0.47As FinFET is analysed using two in-house simulation tools based on the finite element method: a 3D Drift-Diffusion device simulator and a 3D ensemble Monte Carlo simulator, that include quantum-corrections through the density gradient approach. The Id-Vg characteristics have been compared in the sub-threshold region against ballistic NEGF simulations, showing an excellent agreement. Monte Carlo simulations, considering a 〈100〉 channel orientation, show a larger on-current variability, over a 120% increase, compared with the results from Drift-Diffusion simulations. In this study, three different metal grain sizes (10, 7 and 5 nm) have been analysed. We have observed that the underestimation of the variability when using Drift-Diffusion simulations is increasing with a reduction in the grain size.
使用基于有限元方法的两种内部仿真工具:3D漂移扩散器件模拟器和3D集成蒙特卡罗模拟器,包括通过密度梯度方法进行量子校正,分析了10.4 nm栅长In0.53Ga0.47As FinFET中TiN金属颗粒工作函数波动引起的通、关电流变异性。在亚阈值区域将Id-Vg特性与弹道NEGF模拟进行了比较,结果表明两者非常吻合。蒙特卡罗模拟,考虑到< 100 >通道方向,显示出更大的电流变异性,与漂移扩散模拟的结果相比,增加了120%以上。在这项研究中,分析了三种不同的金属晶粒尺寸(10,7和5nm)。我们观察到,当使用漂移扩散模拟时,对可变性的低估随着晶粒尺寸的减小而增加。
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引用次数: 2
Variability-aware compact model strategy for 20-nm bulk MOSFETs 20nm块体mosfet的可变感知紧凑模型策略
Xingsheng Wang, D. Reid, Liping Wang, A. Burenkov, C. Millar, B. Cheng, André Lange, J. Lorenz, E. Baer, A. Asenov
In this paper a variability-aware compact modeling strategy is presented for 20-nm bulk planar technology, taking into account the critical dimension long-range process variation and local statistical variability. Process and device simulations and statistical simulations for a wide range of combinations of L and W are carefully carried out using a design of experiments approach. The variability aware compact model strategy features a comprehensively extracted nominal model and two groups of selected parameters for extractions of the long-range process variation and statistical variability. The unified variability compact modeling method can provide a simulation frame for variability aware technology circuit co-optimization.
本文提出了一种考虑临界尺寸、远程工艺变化和局部统计变化的20纳米体平面工艺的可变感知紧凑建模策略。使用实验设计方法仔细地进行了L和W的广泛组合的过程和设备模拟以及统计模拟。变异性感知的紧凑模型策略具有综合提取标称模型和两组用于提取长期过程变化和统计变异性的选定参数的特点。统一的变异性紧凑建模方法为变异性感知技术电路协同优化提供了仿真框架。
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引用次数: 4
Electromigration in solder bumps: A mean-time-to-failure TCAD study 焊料凸起处的电迁移:平均失效时间TCAD研究
H. Ceric, W. Zisser, M. Rovitto, S. Selberherr
The mechanical and electrical properties of solder bumps influence the overall reliability of 3D ICs. A characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation is enhanced by electromigration and leads to the formation of voids which can cause a complete failure of a solder bump. In this paper we present a compact model for prediction of the mean-time-to-failure of solder bumps under the influence of electromigration.
焊点的机械和电气性能影响着3D集成电路的整体可靠性。焊料凸起的一个特点是在工艺加工和使用过程中,其材料成分发生了变化。这种成分的转变通过电迁移得到加强,并导致空洞的形成,从而导致焊料凸点的完全失效。在本文中,我们提出了一个紧凑的模型来预测在电迁移影响下焊料凸点的平均失效时间。
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2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
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