Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931552
Indra Nur Adisusilo, K. Kukita, Y. Kamakura
A phonon transport simulator using a Monte Carlo method is used to analyze the heat conduction properties in FinFET structure. We compare the simulation results to those obtained from the conventional heat conduction equation based on the Fourier's law, and discuss about the discrepancies attributed to ballistic transport effect. We also analyze the impact of additional heat path through gate contact, and show that it has a less significant but non-negligible contribution which could slightly reduce the hot spot temperature.
{"title":"Analysis of heat conduction property in FinFETs using phonon Monte Carlo simulation","authors":"Indra Nur Adisusilo, K. Kukita, Y. Kamakura","doi":"10.1109/SISPAD.2014.6931552","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931552","url":null,"abstract":"A phonon transport simulator using a Monte Carlo method is used to analyze the heat conduction properties in FinFET structure. We compare the simulation results to those obtained from the conventional heat conduction equation based on the Fourier's law, and discuss about the discrepancies attributed to ballistic transport effect. We also analyze the impact of additional heat path through gate contact, and show that it has a less significant but non-negligible contribution which could slightly reduce the hot spot temperature.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130096588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931616
A. Asenov, S. Amoroso, L. Gerrer
This paper presents an overview of state-of-the-art simulation methodologies to investigate statistical effects associated with charge trapping dynamics and their impact on the reliability projection in decananometer MOSFETs. By means of novel 3-D Kinetic Monte Carlo TCAD reliability simulation technology we tracks the time dependent variability associated with granular charge injection and trapping on pre-existing or stress generated oxide traps. For the first time we take into account the interactions between the statistical variability of the `virgin' transistors introduced by the discreteness of charge and granularity of matter and the stochastic nature of the traps distribution and the trapping process itself. Throughout these 3D statistical TCAD techniques we derive the distribution of threshold voltage shift and degradation time constants in conventional bulk, SOI and FinFET transistors.
{"title":"Progress in the simulation of time dependent statistical variability in nano CMOS transistors","authors":"A. Asenov, S. Amoroso, L. Gerrer","doi":"10.1109/SISPAD.2014.6931616","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931616","url":null,"abstract":"This paper presents an overview of state-of-the-art simulation methodologies to investigate statistical effects associated with charge trapping dynamics and their impact on the reliability projection in decananometer MOSFETs. By means of novel 3-D Kinetic Monte Carlo TCAD reliability simulation technology we tracks the time dependent variability associated with granular charge injection and trapping on pre-existing or stress generated oxide traps. For the first time we take into account the interactions between the statistical variability of the `virgin' transistors introduced by the discreteness of charge and granularity of matter and the stochastic nature of the traps distribution and the trapping process itself. Throughout these 3D statistical TCAD techniques we derive the distribution of threshold voltage shift and degradation time constants in conventional bulk, SOI and FinFET transistors.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114859299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931567
W. Goes, M. Waltl, Y. Wimmer, G. Rzepa, T. Grasser
In the course of years, several models have been put forward to explain noise phenomena, bias temperature instability (BTI), and gate leakage currents amongst other reliability issues. Mostly, these models have been developed independently and without considering that they may be caused by the same physical phenomenon. However, new experimental techniques have emerged, which are capable of studying these reliability issue on a microscopic level. One of them is the time-dependent defect spectroscopy (TDDS). Its intensive use has led to several interesting findings, including the fact that the recoverable component of BTI is due to reaction-limited processes. As a consequence, a quite detailed picture of the processes governing BTI has emerged. Interestingly, this picture has also been found to match the observations made for other reliability issues, such as random telegraph noise, 1/f noise, as well as gate leakage currents. Furthermore, the findings based on TDDS have lead to the development of capture/emission time (CET) maps, which can be used to understand the dynamic response of the defects given their widely distributed parameters.
{"title":"Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI","authors":"W. Goes, M. Waltl, Y. Wimmer, G. Rzepa, T. Grasser","doi":"10.1109/SISPAD.2014.6931567","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931567","url":null,"abstract":"In the course of years, several models have been put forward to explain noise phenomena, bias temperature instability (BTI), and gate leakage currents amongst other reliability issues. Mostly, these models have been developed independently and without considering that they may be caused by the same physical phenomenon. However, new experimental techniques have emerged, which are capable of studying these reliability issue on a microscopic level. One of them is the time-dependent defect spectroscopy (TDDS). Its intensive use has led to several interesting findings, including the fact that the recoverable component of BTI is due to reaction-limited processes. As a consequence, a quite detailed picture of the processes governing BTI has emerged. Interestingly, this picture has also been found to match the observations made for other reliability issues, such as random telegraph noise, 1/f noise, as well as gate leakage currents. Furthermore, the findings based on TDDS have lead to the development of capture/emission time (CET) maps, which can be used to understand the dynamic response of the defects given their widely distributed parameters.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931560
C. Sandow, R. Baburske, F. Niedernostheide, F. Pfirsch, C. Tochterle
TCAD simulations of power devices are an important tool to investigate destruction mechanisms of power diodes and IGBTs. It is found that the dynamics of filamentation is the key for understanding the limits of the safe operation area. For both diodes and IGBTs, destructive and non-destructive filamentation mechanisms are identified and the resulting destruction mechanisms are discussed.
{"title":"Exploring the limits of the safe operation area of power semiconductor devices","authors":"C. Sandow, R. Baburske, F. Niedernostheide, F. Pfirsch, C. Tochterle","doi":"10.1109/SISPAD.2014.6931560","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931560","url":null,"abstract":"TCAD simulations of power devices are an important tool to investigate destruction mechanisms of power diodes and IGBTs. It is found that the dynamics of filamentation is the key for understanding the limits of the safe operation area. For both diodes and IGBTs, destructive and non-destructive filamentation mechanisms are identified and the resulting destruction mechanisms are discussed.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133809914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931598
Yuki Furubayashi, M. Ogawa, S. Souma
We present a theoretical study on the temporal current fluctuation in nanowire FET caused by the presence of a single gate oxide trap through the Coulomb interaction. Our calculations based on the scattering theoretical formulation of the current noise showed that the presence of the trap level in the gate insulator gives rise to the enhancement of the noise at a specific gate voltage. The peak position of the noise is related to the capacitive coupling strengths of the trap to the channel and the gate electrode, suggesting that the current noise can be used to measure such physical quantities.
{"title":"Numerical simulation of current noise caused by potential fluctuation in nanowire FET with an oxide trap","authors":"Yuki Furubayashi, M. Ogawa, S. Souma","doi":"10.1109/SISPAD.2014.6931598","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931598","url":null,"abstract":"We present a theoretical study on the temporal current fluctuation in nanowire FET caused by the presence of a single gate oxide trap through the Coulomb interaction. Our calculations based on the scattering theoretical formulation of the current noise showed that the presence of the trap level in the gate insulator gives rise to the enhancement of the noise at a specific gate voltage. The peak position of the noise is related to the capacitive coupling strengths of the trap to the channel and the gate electrode, suggesting that the current noise can be used to measure such physical quantities.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116087040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931602
F. Rudolf, J. Weinbub, K. Rupp, A. Morhammer, S. Selberherr
Creating multiple meshes of a semiconductor device by varying specific geometric properties, like the gate length of a MOSFET, is a crucial step for optimization or scaling processes of these devices. A geometry generation technique for semiconductor devices using geometry templates is presented and implemented in the open source meshing tool ViennaMesh, providing a convenient mechanism for creating device geometries based on a selected set of parameters. These geometries can be used by ViennaMesh to create high-quality meshes to be exported and used by simulation tools. Results of meshes for two-dimensional MOSFET and three-dimensional FinFET devices created by this technique are presented.
{"title":"Template-based mesh generation for semiconductor devices","authors":"F. Rudolf, J. Weinbub, K. Rupp, A. Morhammer, S. Selberherr","doi":"10.1109/SISPAD.2014.6931602","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931602","url":null,"abstract":"Creating multiple meshes of a semiconductor device by varying specific geometric properties, like the gate length of a MOSFET, is a crucial step for optimization or scaling processes of these devices. A geometry generation technique for semiconductor devices using geometry templates is presented and implemented in the open source meshing tool ViennaMesh, providing a convenient mechanism for creating device geometries based on a selected set of parameters. These geometries can be used by ViennaMesh to create high-quality meshes to be exported and used by simulation tools. Results of meshes for two-dimensional MOSFET and three-dimensional FinFET devices created by this technique are presented.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129654267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931571
L. Gerrer, S. Amoroso, R. Hussin, F. Adamu-Lema, A. Asenov
New architectures introduction succeeded in reducing the device performances dispersion in scaled transistors, but as a consequence the relative importance of oxide reliability increased. In this work we present original results of charged interface traps impact on bulk, FDSOI and Fin FETs performances. Traps time constants are analyzed and recoverable and permanent degradation proportions are derived. Finally transistors parameters dispersion increase with time are simulated demonstrating our simulator ability to provide accurate reliability predictions for these three architectures.
{"title":"3D atomistic simulations of bulk, FDSOI and Fin FETs sensitivity to oxide reliability","authors":"L. Gerrer, S. Amoroso, R. Hussin, F. Adamu-Lema, A. Asenov","doi":"10.1109/SISPAD.2014.6931571","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931571","url":null,"abstract":"New architectures introduction succeeded in reducing the device performances dispersion in scaled transistors, but as a consequence the relative importance of oxide reliability increased. In this work we present original results of charged interface traps impact on bulk, FDSOI and Fin FETs performances. Traps time constants are analyzed and recoverable and permanent degradation proportions are derived. Finally transistors parameters dispersion increase with time are simulated demonstrating our simulator ability to provide accurate reliability predictions for these three architectures.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129876799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931556
P. Dorion, O. Cueto, M. Reyboz, J. Barbe, A. Grigoriu, Y. Maday
A TCAD model for Chalcogenide based CBRAM is presented. This model starts from an existing model and uses an advanced level set method to follow the growth of the filament in the electrolyte. We couple the level set method with equations which model the cations migration and the electric field in the electrolyte and in the filament. We take into account silver clusters in the electrolyte in order to study their influence on switching time.
{"title":"Advanced simulation of CBRAM devices with the level set method","authors":"P. Dorion, O. Cueto, M. Reyboz, J. Barbe, A. Grigoriu, Y. Maday","doi":"10.1109/SISPAD.2014.6931556","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931556","url":null,"abstract":"A TCAD model for Chalcogenide based CBRAM is presented. This model starts from an existing model and uses an advanced level set method to follow the growth of the filament in the electrolyte. We couple the level set method with equations which model the cations migration and the electric field in the electrolyte and in the filament. We take into account silver clusters in the electrolyte in order to study their influence on switching time.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"EM-15 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121005329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931620
J. Lorenz, E. Bar, A. Burenkov, P. Evanschitzky, A. Asenov, L. Wang, X. Wang, A. Brown, C. Millar, D. Reid
An efficient approach is presented and demonstrated which enables the simultaneous simulation of the impact of several sources of process variations, ranging from equipment-induced to stochastic ones, which are caused by the granularity of matter. Own software is combined with third-party tools to establish a hierarchical simulation sequence from equipment to circuit level. Correlations which occur because some sources of variability affect different devices and different device quantities can be rigorously studied.
{"title":"Simultaneous simulation of systematic and stochastic process variations","authors":"J. Lorenz, E. Bar, A. Burenkov, P. Evanschitzky, A. Asenov, L. Wang, X. Wang, A. Brown, C. Millar, D. Reid","doi":"10.1109/SISPAD.2014.6931620","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931620","url":null,"abstract":"An efficient approach is presented and demonstrated which enables the simultaneous simulation of the impact of several sources of process variations, ranging from equipment-induced to stochastic ones, which are caused by the granularity of matter. Own software is combined with third-party tools to establish a hierarchical simulation sequence from equipment to circuit level. Correlations which occur because some sources of variability affect different devices and different device quantities can be rigorously studied.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121677151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931622
T. Windbacher, H. Mahmoudi, V. Sverdlov, S. Selberherr
Recently, we proposed a non-volatile magnetic flip flop featuring a very small footprint. We studied its operational limits and current dependent characteristics. Since flip flops are commonly operated by clocked signals, their operation is time critical and the knowledge and understanding of their switching behavior is essential. In this work we study the dependence of the proposed flip flop on its device geometry. In order to facilitate the comparison to the previous results, the same device parameters are employed. The current density was fixed for both inputs at a value of 7 × 1010 A/m2, where all flip flops safely operated, and the free layers' dimensions were varied, independently. The free layer thickness was found as the most critical parameter affecting the switching time, followed by the layer length and a negligible dependence on width.
最近，我们提出了一种非易失性磁触发器，具有非常小的占地面积。我们研究了它的操作极限和电流依赖特性。由于触发器通常由时钟信号操作，因此其操作对时间至关重要，因此对其开关行为的了解和理解至关重要。在这项工作中，我们研究了所提出的触发器对其器件几何形状的依赖性。为了便于与以往的结果进行比较，采用了相同的器件参数。两个输入的电流密度固定为7 × 1010 a /m2，所有触发器都安全运行，并且自由层的尺寸独立变化。发现自由层厚度是影响开关时间的最关键参数，其次是层长度，对宽度的依赖可以忽略不计。
{"title":"Influence of device geometry on the non-volatile magnetic flip flop characteristics","authors":"T. Windbacher, H. Mahmoudi, V. Sverdlov, S. Selberherr","doi":"10.1109/SISPAD.2014.6931622","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931622","url":null,"abstract":"Recently, we proposed a non-volatile magnetic flip flop featuring a very small footprint. We studied its operational limits and current dependent characteristics. Since flip flops are commonly operated by clocked signals, their operation is time critical and the knowledge and understanding of their switching behavior is essential. In this work we study the dependence of the proposed flip flop on its device geometry. In order to facilitate the comparison to the previous results, the same device parameters are employed. The current density was fixed for both inputs at a value of 7 × 1010 A/m2, where all flip flops safely operated, and the free layers' dimensions were varied, independently. The free layer thickness was found as the most critical parameter affecting the switching time, followed by the layer length and a negligible dependence on width.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130631560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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