Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015409
Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Y. Chan, Kuo-Nan Yang, Chih-Jian Chen, H. Tao, Yang-Kyu Choi, M. Liang, C. Hu
We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.
我们首次展示了高性能的35纳米CMOS finfet。用简单的技术实现了非场效应晶体管和非场效应晶体管的对称失态泄漏。在保守的24 /spl栅极氧化物厚度下，1伏特工作时，晶体管的驱动电流为1240 /spl mu/ a //spl mu/m，在关闭电流为200 nA//spl mu/m时，fet的驱动电流为500 /spl mu/ a //spl mu/m。实现了出色的热载体免疫。设备性能参数超过ITRS预测。
{"title":"35 nm CMOS FinFETs","authors":"Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Y. Chan, Kuo-Nan Yang, Chih-Jian Chen, H. Tao, Yang-Kyu Choi, M. Liang, C. Hu","doi":"10.1109/VLSIT.2002.1015409","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015409","url":null,"abstract":"We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015435
M. Celik, S. Krishnan, M. Fuselier, A. Wei, D. Wu, B. En, N. Cave, P. Abramowitz, B. Min, M. Pelella, P. Yeh, G. Burbach, B. Taylor, Y. Jeon, W. Qi, Ruigang Li, J. Conner, G. Yeap, M. Woo, M. Mendicino, O. Karlsson, D. Wristers
In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.
{"title":"A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications","authors":"M. Celik, S. Krishnan, M. Fuselier, A. Wei, D. Wu, B. En, N. Cave, P. Abramowitz, B. Min, M. Pelella, P. Yeh, G. Burbach, B. Taylor, Y. Jeon, W. Qi, Ruigang Li, J. Conner, G. Yeap, M. Woo, M. Mendicino, O. Karlsson, D. Wristers","doi":"10.1109/VLSIT.2002.1015435","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015435","url":null,"abstract":"In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134138467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015378
Xiaoling Guo, J. Caserta, R. Li, B. Floyd, K. O
Inserting an aluminum nitride (AlN) layer which acts as a dielectric propagating medium between a silicon wafer containing integrated antennas and a metal chuck emulating the role of a heat sink improves the antenna power transmission gain by /spl sim/8 dB at 15 GHz. AlN, with its high thermal conductivity, also alleviates the heat removal problem. With a 760-/spl mu/m AlN layer, an on-chip wireless connection is demonstrated over a 2.2-cm distance, which is 3/spl times/ the previously reported separation.
{"title":"Propagation layers for intra-chip wireless interconnection compatible with packaging and heat removal","authors":"Xiaoling Guo, J. Caserta, R. Li, B. Floyd, K. O","doi":"10.1109/VLSIT.2002.1015378","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015378","url":null,"abstract":"Inserting an aluminum nitride (AlN) layer which acts as a dielectric propagating medium between a silicon wafer containing integrated antennas and a metal chuck emulating the role of a heat sink improves the antenna power transmission gain by /spl sim/8 dB at 15 GHz. AlN, with its high thermal conductivity, also alleviates the heat removal problem. With a 760-/spl mu/m AlN layer, an on-chip wireless connection is demonstrated over a 2.2-cm distance, which is 3/spl times/ the previously reported separation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114682416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015452
A. Misaka, T. Matsuo, M. Sasago
We propose new two phase shifting masks: centerline phase-shifting mask (CL-PSM) and outline phase-shifting mask (OL-PSM). CL-PSM enhances the DOF of line patterns more than alternating phase-shifting masks. OL-PSM drastically improves the resolution of the contact pattern compared with attenuated phase-shifting masks. Both CL-PSM and OL-PSM are classified as strong resolution enhancement technologies. Furthermore, they can be applied to random logic patterns without multiple exposures. They will allow us to make sub-65-nm node logic LSIs with ArF lithography, and will also be useful for VUV lithography.
{"title":"Super-resolution enhancement method with phase-shifting mask available for random patterns","authors":"A. Misaka, T. Matsuo, M. Sasago","doi":"10.1109/VLSIT.2002.1015452","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015452","url":null,"abstract":"We propose new two phase shifting masks: centerline phase-shifting mask (CL-PSM) and outline phase-shifting mask (OL-PSM). CL-PSM enhances the DOF of line patterns more than alternating phase-shifting masks. OL-PSM drastically improves the resolution of the contact pattern compared with attenuated phase-shifting masks. Both CL-PSM and OL-PSM are classified as strong resolution enhancement technologies. Furthermore, they can be applied to random logic patterns without multiple exposures. They will allow us to make sub-65-nm node logic LSIs with ArF lithography, and will also be useful for VUV lithography.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116832713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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