Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015405
T. Tezuka, N. Sugiyama, T. Mizuno, S. Takagi
Strained SOI (SSOI)-nMOSFETs with enhanced mobility up to 67% were fabricated on a strain-relaxed SiGe-on-insulator substrate using a novel Ge-condensation technique. This method, using only standard Si processes, realizes smooth SSOI surfaces without using SIMOX, wafer bonding, surface polishing or any other special processes. Relaxation ratio of the SiGe substrate was varied from 0% to 100%, resulting in the control of threshold voltage. The Ge-condensation process using conventional SOI substrates is an attractive technique for fabrication of multi-threshold SSOI-CMOS circuits with high current drive.
{"title":"High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique","authors":"T. Tezuka, N. Sugiyama, T. Mizuno, S. Takagi","doi":"10.1109/VLSIT.2002.1015405","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015405","url":null,"abstract":"Strained SOI (SSOI)-nMOSFETs with enhanced mobility up to 67% were fabricated on a strain-relaxed SiGe-on-insulator substrate using a novel Ge-condensation technique. This method, using only standard Si processes, realizes smooth SSOI surfaces without using SIMOX, wafer bonding, surface polishing or any other special processes. Relaxation ratio of the SiGe substrate was varied from 0% to 100%, resulting in the control of threshold voltage. The Ge-condensation process using conventional SOI substrates is an attractive technique for fabrication of multi-threshold SSOI-CMOS circuits with high current drive.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015456
H.H. Kim, Y.J. Song, S.Y. Lee, H. Joo, N. Jang, D. Jung, Y.S. Park, S.O. Park, K.M. Lee, S. Joo, S.W. Lee, S. Nam, K. Kim
Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.
铁电随机存取存储器(FRAM)具有非易失性、高耐用性、快速读写时间和低功耗等优点，被认为是一种未来的存储器件。最近，采用1T1C电容-位线(COB)电池结构和三重金属化技术开发了4mb FRAM (S.Y. Lee等，VLSI Symp.)。技术,挖掘。，第141页，1999年)。然而，目前的4mb FRAM器件由于其低密度、低成本和大单元尺寸因素，不能令人满意地用作独立应用的主要存储器件。因此，迫切需要开发超过32 Mb的高密度FRAM器件，以应用于独立存储设备。在本文中，我们首次报道了一个高度可制造的32 Mb FRAM的开发，该FRAM由300 nm电容器堆栈技术在COB电池结构中实现，双封装阻挡层(EBL)方案，最佳层间介电(ILD)和金属间介电(IMD)技术，以及一种新的公共细胞通孔方案。
{"title":"Novel integration technologies for highly manufacturable 32 Mb FRAM","authors":"H.H. Kim, Y.J. Song, S.Y. Lee, H. Joo, N. Jang, D. Jung, Y.S. Park, S.O. Park, K.M. Lee, S. Joo, S.W. Lee, S. Nam, K. Kim","doi":"10.1109/VLSIT.2002.1015456","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015456","url":null,"abstract":"Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015451
S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani
A novel resist pattern transfer process for the 70 nm technology node is presented using 157-nm lithography. By using newly developed 157-nm resists and a 157-nm microstepper (NA=0.60), sub-100 nm resist patterns are fabricated. Three types of structures are presented for the pattern transfer process. Two of these are hard mask (HM) processes. and the other is a bi-layer process using Si-containing resist. For all these structures, the underlayers of resist work well as anti-reflecting layers. By optimizing the RIE gas conditions, resist patterns are successfully transferred to the underlayer. Using the HM as an etching mask, sub-100 nm gate patterns are fabricated.
{"title":"Novel resist pattern transfer process for 70 nm technology node using 157-nm lithography","authors":"S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani","doi":"10.1109/VLSIT.2002.1015451","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015451","url":null,"abstract":"A novel resist pattern transfer process for the 70 nm technology node is presented using 157-nm lithography. By using newly developed 157-nm resists and a 157-nm microstepper (NA=0.60), sub-100 nm resist patterns are fabricated. Three types of structures are presented for the pattern transfer process. Two of these are hard mask (HM) processes. and the other is a bi-layer process using Si-containing resist. For all these structures, the underlayers of resist work well as anti-reflecting layers. By optimizing the RIE gas conditions, resist patterns are successfully transferred to the underlayer. Using the HM as an etching mask, sub-100 nm gate patterns are fabricated.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015390
S. Nakai, Y. Takao, S. Otsuka, K. Sugiyama, H. Ohta, A. Yamanoue, Y. Iriyama, R. Nanjyo, S. Sekino, H. Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y. Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, S. Sugatani, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, K. Yanai
A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell (<1 /spl mu/m/sup 2/). (2) A unique transistor feature which is referred to as "sidewall-notched gate" enables an optimal pocket implant placement and suppresses variations of the notch width much better than poly-notched gate structure. (3) 1.1 nm nitrided oxide (1.9 nm inversion T/sub ox/) is used to achieve high drive current, and the thermal budget is reduced to suppress the boron penetration. (4) SiC-capped Cu/SiLK structure in 0.28 /spl mu/m pitch metal 1-4 layers realizes k/sub eff/ of 3.0.
{"title":"A 100 nm CMOS technology with \"sidewall-notched\" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications","authors":"S. Nakai, Y. Takao, S. Otsuka, K. Sugiyama, H. Ohta, A. Yamanoue, Y. Iriyama, R. Nanjyo, S. Sekino, H. Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y. Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, S. Sugatani, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, K. Yanai","doi":"10.1109/VLSIT.2002.1015390","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015390","url":null,"abstract":"A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell (<1 /spl mu/m/sup 2/). (2) A unique transistor feature which is referred to as \"sidewall-notched gate\" enables an optimal pocket implant placement and suppresses variations of the notch width much better than poly-notched gate structure. (3) 1.1 nm nitrided oxide (1.9 nm inversion T/sub ox/) is used to achieve high drive current, and the thermal budget is reduced to suppress the boron penetration. (4) SiC-capped Cu/SiLK structure in 0.28 /spl mu/m pitch metal 1-4 layers realizes k/sub eff/ of 3.0.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015397
S.J. Lee, S. Rhee, R. Clark, D. Kwong
A systematic study of long-term reliability of ultra thin CVD HfO/sub 2/ gate stack (EOT=10.5 /spl Aring/) with TaN gate electrode is presented. The polarity and area dependence and temperature acceleration of time-to-breakdown (TBO), defect generation rate, and critical defect density are studied. It is found that T/sub BD/ is polarity-independent (T/sub BD,-Vg/=T/sub BD,+Vg/). TDDB lifetime acceleration shows that 10-year lifetime of HfO/sub 2/ gate stack is projected at Vg=1.63 V for EOT=8.6 /spl Aring/ and Vg=1.88 V for EOT=10.6 /spl Aring/ at 25/spl deg/C. However, after temperature acceleration of 150/spl deg/C, area scaling to 0.1 cm/sup 2/, and the projection to low percentage failure rate of 0.01%, the maximum operating voltages are projected to be Vg=0.6 V for EOT 8.6 /spl Aring/ and Vg=0.75 V for EOT=10.6 /spl Aring/.
{"title":"Reliability projection and polarity dependence of TDDB for ultra thin CVD HfO/sub 2/ gate dielectrics","authors":"S.J. Lee, S. Rhee, R. Clark, D. Kwong","doi":"10.1109/VLSIT.2002.1015397","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015397","url":null,"abstract":"A systematic study of long-term reliability of ultra thin CVD HfO/sub 2/ gate stack (EOT=10.5 /spl Aring/) with TaN gate electrode is presented. The polarity and area dependence and temperature acceleration of time-to-breakdown (TBO), defect generation rate, and critical defect density are studied. It is found that T/sub BD/ is polarity-independent (T/sub BD,-Vg/=T/sub BD,+Vg/). TDDB lifetime acceleration shows that 10-year lifetime of HfO/sub 2/ gate stack is projected at Vg=1.63 V for EOT=8.6 /spl Aring/ and Vg=1.88 V for EOT=10.6 /spl Aring/ at 25/spl deg/C. However, after temperature acceleration of 150/spl deg/C, area scaling to 0.1 cm/sup 2/, and the projection to low percentage failure rate of 0.01%, the maximum operating voltages are projected to be Vg=0.6 V for EOT 8.6 /spl Aring/ and Vg=0.75 V for EOT=10.6 /spl Aring/.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123990140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015436
I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka
We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.
{"title":"High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors","authors":"I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka","doi":"10.1109/VLSIT.2002.1015436","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015436","url":null,"abstract":"We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117227657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015428
A. Rotondaro, M. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M. Bevan, T. Grider, J. McPherson, L. Colombo
We report for the first time on short channel transistors fabricated using HfSiON, a new high-k gate dielectric material. HfSiON has superior electrical characteristics such as low leakage current relative to SiO/sub 2/, low interfacial trap density, electron and hole carrier mobilities /spl sim/80% of the universal curve at E/sub eff/>0.8 MV/cm and scalability to equivalent oxide thicknesses of less than 10 /spl Aring/. This material is also thermally stable up to 1100/spl deg/C in contact with poly Si, and exhibits boron blocking significantly better than SiO/sub 2/ and SiON. The results indicate that this material is a promising high-k gate dielectric with good transistor characteristics.
{"title":"Advanced CMOS transistors with a novel HfSiON gate dielectric","authors":"A. Rotondaro, M. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M. Bevan, T. Grider, J. McPherson, L. Colombo","doi":"10.1109/VLSIT.2002.1015428","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015428","url":null,"abstract":"We report for the first time on short channel transistors fabricated using HfSiON, a new high-k gate dielectric material. HfSiON has superior electrical characteristics such as low leakage current relative to SiO/sub 2/, low interfacial trap density, electron and hole carrier mobilities /spl sim/80% of the universal curve at E/sub eff/>0.8 MV/cm and scalability to equivalent oxide thicknesses of less than 10 /spl Aring/. This material is also thermally stable up to 1100/spl deg/C in contact with poly Si, and exhibits boron blocking significantly better than SiO/sub 2/ and SiON. The results indicate that this material is a promising high-k gate dielectric with good transistor characteristics.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015408
Jin Cai, Y. Taur, Shih-Fen Huang, D. Frank, S. Kosonocky, R. Dennard
This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V/sub DD/ and threshold voltage V/sub T/, an optimization procedure that takes the circuit activity factor into account is performed to find the V/sub DD/ and V/sub T/ for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.
{"title":"Supply voltage strategies for minimizing the power of CMOS processors","authors":"Jin Cai, Y. Taur, Shih-Fen Huang, D. Frank, S. Kosonocky, R. Dennard","doi":"10.1109/VLSIT.2002.1015408","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015408","url":null,"abstract":"This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V/sub DD/ and threshold voltage V/sub T/, an optimization procedure that takes the circuit activity factor into account is performed to find the V/sub DD/ and V/sub T/ for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015387
R. Rengarajan, R. Malik, Haining Yang, W. Yan, R. Ramachandran, Boyong He, R. Divakaruni, Yujun Li
In this paper, we report on integration of high performance dual workfunction logic CMOS transistors with a commodity 8F/sup 2/ vertical DRAM cell for high performance stand-alone DRAM and low-cost low-power embedded DRAM applications. Key process integration features that exploit novel aspects of the vertical DRAM cell to enable a high performance embedded DRAM technology are presented. The impact of pre-metal-dielectric reflow thermal budget on dual workfunction CMOS device characteristics is discussed.
{"title":"Integration of high performance dual workfunction logic CMOS transistors with a dense 8F/sup 2/ vertical DRAM cell","authors":"R. Rengarajan, R. Malik, Haining Yang, W. Yan, R. Ramachandran, Boyong He, R. Divakaruni, Yujun Li","doi":"10.1109/VLSIT.2002.1015387","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015387","url":null,"abstract":"In this paper, we report on integration of high performance dual workfunction logic CMOS transistors with a commodity 8F/sup 2/ vertical DRAM cell for high performance stand-alone DRAM and low-cost low-power embedded DRAM applications. Key process integration features that exploit novel aspects of the vertical DRAM cell to enable a high performance embedded DRAM technology are presented. The impact of pre-metal-dielectric reflow thermal budget on dual workfunction CMOS device characteristics is discussed.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132766724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015382
P. Oldiges, K. Bernstein, D. Heidel, B. Klaasen, E. Cannon, R. Dennard, H. Tang, M. Ieong, H.-S.P. Wong
The soft error rate in SOI devices is explored. Conventional SOI device soft error rate is compared to high mobility SOI and double gate SOI designs. We develop a theoretical understanding of the susceptibility of SOI devices to /spl alpha/-particle induced soft errors by means of simulations and measurements. Although high mobility devices will decrease soft error rate susceptibility, silicon thinning is shown to have a much larger impact. Double gate devices are shown to improve the soft error rate even further.
{"title":"Soft error rate scaling for emerging SOI technology options","authors":"P. Oldiges, K. Bernstein, D. Heidel, B. Klaasen, E. Cannon, R. Dennard, H. Tang, M. Ieong, H.-S.P. Wong","doi":"10.1109/VLSIT.2002.1015382","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015382","url":null,"abstract":"The soft error rate in SOI devices is explored. Conventional SOI device soft error rate is compared to high mobility SOI and double gate SOI designs. We develop a theoretical understanding of the susceptibility of SOI devices to /spl alpha/-particle induced soft errors by means of simulations and measurements. Although high mobility devices will decrease soft error rate susceptibility, silicon thinning is shown to have a much larger impact. Double gate devices are shown to improve the soft error rate even further.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133102185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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