Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015365
D. Antoniadis
Silicon-based MOSFETs are scalable to gate-lengths around 10 nm but will fall well short of commensurate performance enhancement. High mobility materials and device structures that eliminate the use of doping for electrostatic control will have to be incorporated in future CMOS technologies, along with very low contact resistance processes. New frontier FETs incorporating entirely new transport principles show promise but are still far from practical implementation.
{"title":"MOSFET scalability limits and \"new frontier\" devices","authors":"D. Antoniadis","doi":"10.1109/VLSIT.2002.1015365","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015365","url":null,"abstract":"Silicon-based MOSFETs are scalable to gate-lengths around 10 nm but will fall well short of commensurate performance enhancement. High mobility materials and device structures that eliminate the use of doping for electrostatic control will have to be incorporated in future CMOS technologies, along with very low contact resistance processes. New frontier FETs incorporating entirely new transport principles show promise but are still far from practical implementation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131363807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015450
T. Matsuo, M. Endo, S. Kishimura, A. Misaka, M. Sasago
For 65-nm node devices, we have systematically investigated the lithographic margin of electron-beam projection lithography (EPL), ArF lithography and vacuum ultraviolet (VUV) lithography. Among them, EPL has sufficient margin and excellent pattern fidelity and our experiments have demonstrated that it can fabricate 65-nm node device patterns. Therefore, EPL is a strong candidate for 65-nm node lithography.
{"title":"Lithography solution for 65-nm node system LSIs","authors":"T. Matsuo, M. Endo, S. Kishimura, A. Misaka, M. Sasago","doi":"10.1109/VLSIT.2002.1015450","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015450","url":null,"abstract":"For 65-nm node devices, we have systematically investigated the lithographic margin of electron-beam projection lithography (EPL), ArF lithography and vacuum ultraviolet (VUV) lithography. Among them, EPL has sufficient margin and excellent pattern fidelity and our experiments have demonstrated that it can fabricate 65-nm node device patterns. Therefore, EPL is a strong candidate for 65-nm node lithography.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132976144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015444
B.J. Park, Y. Hwang, Y. Hwang, J. Lee, K. Lee, K. Jeong, H. Jeong, Y.J. Park, Kinam Kim
A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.
{"title":"A novel bit line-SToFM (Spacerless top-flat mask)-technology for 90 nm DRAM generation and beyond","authors":"B.J. Park, Y. Hwang, Y. Hwang, J. Lee, K. Lee, K. Jeong, H. Jeong, Y.J. Park, Kinam Kim","doi":"10.1109/VLSIT.2002.1015444","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015444","url":null,"abstract":"A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116075673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015454
H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi
We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.
我们提出了一种新颖的2位/单元MONOS存储器结构，其特点是封装门。编程和擦除分别采用源侧热电子注入和热空穴注入。实现了编程速度<1 /spl mu/s，编程电流<2 /spl mu/ a //spl mu/m，擦除速度<10 /spl mu/s。
{"title":"A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection","authors":"H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi","doi":"10.1109/VLSIT.2002.1015454","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015454","url":null,"abstract":"We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125926107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015414
Jong-Ho Lee, Jung-Hyoung Lee, Yun-seok Kim, Hyung-Seok Jung, N. Lee, Ho-Kyu Kang, K. Suh
For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.
{"title":"Practical next generation solution for stand-alone and embedded DRAM capacitor","authors":"Jong-Ho Lee, Jung-Hyoung Lee, Yun-seok Kim, Hyung-Seok Jung, N. Lee, Ho-Kyu Kang, K. Suh","doi":"10.1109/VLSIT.2002.1015414","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015414","url":null,"abstract":"For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015371
S. Jang, Y.H. Chen, T. Chou, S.N. Lee, C. Chen, T.C. Tseng, B.T. Chen, S.Y. Chang, C. Yu, M. Liang
A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.
{"title":"Advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0.07 /spl mu/m generation","authors":"S. Jang, Y.H. Chen, T. Chou, S.N. Lee, C. Chen, T.C. Tseng, B.T. Chen, S.Y. Chang, C. Yu, M. Liang","doi":"10.1109/VLSIT.2002.1015371","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015371","url":null,"abstract":"A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128865609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015457
M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, H. Itoh, H. Kano, K. Bessho, H. Narisawe
This work is a report on high-performance MRAM technology. 0.4/spl times/0.8 /spl mu/m/sup 2/ MTJ elements were successfully integrated with 0.35 /spl mu/m CMOS technology without process-induced damage. A magnetoresistance (MR) ratio of more than 55% and the read/write operating point were obtained by introducing an improved magnetic tunnel junction (MTJ) material. The short-pulse writing in combination with an improved cell structure suggests that MRAM has a great deal of potential for low power applications.
{"title":"High-performance MRAM technology with an improved magnetic tunnel junction material","authors":"M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, H. Itoh, H. Kano, K. Bessho, H. Narisawe","doi":"10.1109/VLSIT.2002.1015457","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015457","url":null,"abstract":"This work is a report on high-performance MRAM technology. 0.4/spl times/0.8 /spl mu/m/sup 2/ MTJ elements were successfully integrated with 0.35 /spl mu/m CMOS technology without process-induced damage. A magnetoresistance (MR) ratio of more than 55% and the read/write operating point were obtained by introducing an improved magnetic tunnel junction (MTJ) material. The short-pulse writing in combination with an improved cell structure suggests that MRAM has a great deal of potential for low power applications.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129413385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015458
A. Suzuki, K. Tabuchi, H. Kimura, T. Hasegawa, S. Kadomura
This paper is a report on the effect of processing to form interconnects by using copper and a material with a low dielectric constant (copper/low-k) on the negative-bias temperature instability (NBTI) of p-MOSFETs. We found that the NBT-stress lifetime of copper/low-k interconnects is shorter than that of aluminum/SiO/sub 2/ interconnects. The NBTI strongly depends on the cap layer over the copper/low-k layer, on the intermetal dielectric (IMD) film, on the barrier-metal film, and on the temperature of post-metal annealing (PMA). Based on these results, we developed methods for reducing the NBTI in next-generation MOSFETs.
{"title":"A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide","authors":"A. Suzuki, K. Tabuchi, H. Kimura, T. Hasegawa, S. Kadomura","doi":"10.1109/VLSIT.2002.1015458","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015458","url":null,"abstract":"This paper is a report on the effect of processing to form interconnects by using copper and a material with a low dielectric constant (copper/low-k) on the negative-bias temperature instability (NBTI) of p-MOSFETs. We found that the NBT-stress lifetime of copper/low-k interconnects is shorter than that of aluminum/SiO/sub 2/ interconnects. The NBTI strongly depends on the cap layer over the copper/low-k layer, on the intermetal dielectric (IMD) film, on the barrier-metal film, and on the temperature of post-metal annealing (PMA). Based on these results, we developed methods for reducing the NBTI in next-generation MOSFETs.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124375177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015398
C. Lee, J.J. Lee, W. Bai, S. H. Bae, J. Sim, X. Lei, R. Clark, Y. Harada, M. Niwa, D. Kwong
In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.
{"title":"Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode","authors":"C. Lee, J.J. Lee, W. Bai, S. H. Bae, J. Sim, X. Lei, R. Clark, Y. Harada, M. Niwa, D. Kwong","doi":"10.1109/VLSIT.2002.1015398","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015398","url":null,"abstract":"In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120944213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015447
Y. Tanida, Y. Tamura, S. Miyagaki, M. Yamaguchi, C. Yoshida, Y. Sugiyama, H. Tanaka
The effect of nitrogen doping into Al/sub 2/O/sub 3/ gate dielectric grown by Metal Organic Chemical Vapor Deposition (MOCVD) on MOS device characteristics is described for the first time. The nitrogen doped Al/sub 2/O/sub 3/ (Al/sub 2/O/sub 3/:N) MOSFET has an interface trap density (D/sub it/) as low as 4.3/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/, half that of non-doped Al/sub 2/O/sub 3/ (1.0/spl times/10/sup 11/ cm/sup -2/ eV/sup -1/), and has less C-V hysteresis (39 mV) than that (69 mV) of Al/sub 2/O/sub 3/. These improvements are attributed to nitrogen doping into Al/sub 2/O/sub 3/, which also improves the corresponding MOSFET characteristics of current drivability (I/sub dsat/).
{"title":"Effect of in-situ nitrogen doping into MOCVD-grown Al/sub 2/O/sub 3/ to improve electrical characteristics of MOSFETs with polysilicon gate","authors":"Y. Tanida, Y. Tamura, S. Miyagaki, M. Yamaguchi, C. Yoshida, Y. Sugiyama, H. Tanaka","doi":"10.1109/VLSIT.2002.1015447","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015447","url":null,"abstract":"The effect of nitrogen doping into Al/sub 2/O/sub 3/ gate dielectric grown by Metal Organic Chemical Vapor Deposition (MOCVD) on MOS device characteristics is described for the first time. The nitrogen doped Al/sub 2/O/sub 3/ (Al/sub 2/O/sub 3/:N) MOSFET has an interface trap density (D/sub it/) as low as 4.3/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/, half that of non-doped Al/sub 2/O/sub 3/ (1.0/spl times/10/sup 11/ cm/sup -2/ eV/sup -1/), and has less C-V hysteresis (39 mV) than that (69 mV) of Al/sub 2/O/sub 3/. These improvements are attributed to nitrogen doping into Al/sub 2/O/sub 3/, which also improves the corresponding MOSFET characteristics of current drivability (I/sub dsat/).","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114179750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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