Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015380
Jong-wook Lee, H. Takemura, Y. Saitoh, R. Koh, S. Yamagami, T. Mogami, M. Uto, N. Ikezawa, N. Takasu
The ELFIN (elevated field insulator) process for device isolation and SEP (source/drain elevated by poly-Si plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI films of less than 20 nm. With the ELFIN process, the gate electric field at the SOI edge is negligible as the SOI edge is not wrapped around by the poly-Si gate so that the reverse narrow channel effect of the NMOSFET is improved by about 50%, gate leakage current decreased by about 30%, and hot-carrier immunity increased by about 20%. With the SEP process, an elevated S/D region 60 nm thick is obtained so that S/D resistance is deceased to a third and has excellent uniformity over a wafer.
{"title":"ELFIN (elevated field insulator) and SEP (S/D elevated by poly-Si plugging) process for ultra-thin SOI MOSFETs with high performance and high reliability","authors":"Jong-wook Lee, H. Takemura, Y. Saitoh, R. Koh, S. Yamagami, T. Mogami, M. Uto, N. Ikezawa, N. Takasu","doi":"10.1109/VLSIT.2002.1015380","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015380","url":null,"abstract":"The ELFIN (elevated field insulator) process for device isolation and SEP (source/drain elevated by poly-Si plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI films of less than 20 nm. With the ELFIN process, the gate electric field at the SOI edge is negligible as the SOI edge is not wrapped around by the poly-Si gate so that the reverse narrow channel effect of the NMOSFET is improved by about 50%, gate leakage current decreased by about 30%, and hot-carrier immunity increased by about 20%. With the SEP process, an elevated S/D region 60 nm thick is obtained so that S/D resistance is deceased to a third and has excellent uniformity over a wafer.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131485489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015446
K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, J. Maes
We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.
我们认为，在开发高/spl kappa/栅极电介质中，最重要的任务是设计接口以确保足够高的移动性和可靠性。考虑到100纳米节点，Al/sub 2/O/sub 3/在化学和热稳定性、势垒偏移以及与传统CMOS工艺的兼容性方面似乎是最有希望的候选者。Al/sub 2/O/sub 3/栅极电介质在sub-100 nm fet中的集成已经被证明;然而，由此产生的电子迁移率仅为SiO/sub - 2/栅极电介质场效应管的四分之一(D. Buchanan et al.， Tech. Digest IEDM, p. 223, 2000;李家辉等人，同上，第645页，2000)。我们已经从实验和理论上阐明了迁移率降低的机制。
{"title":"The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric","authors":"K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, J. Maes","doi":"10.1109/VLSIT.2002.1015446","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015446","url":null,"abstract":"We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132353032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015379
TingYen Chiang, B. Shieh, K. Saraswat
This paper investigates the impact of Joule heating on the scaling trends of advanced VLSI interconnects. It shows that the interconnect Joule heating can strongly affect the maximum operating temperature of the global wires which, in turn, will constrain the scaling of current density to mitigate electromigration and, thus greatly degrade the expected speed improvement from the use of low-k dielectrics. Through a combination of extensive electrothermal simulation and 2D field solver for capacitance calculation, the thermal characteristics of various Cu/low-k schemes are quantified and their effects on electromigration reliability and interconnect delay are determined. The effect of vias, as efficient heat conduction paths, is included for realistic evaluation. Our analysis suggests that Joule heating will be a bottleneck in scaling interconnects and projections of International Technology Roadmap for Semiconductors (ITRS'01) will not be met.
{"title":"Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects","authors":"TingYen Chiang, B. Shieh, K. Saraswat","doi":"10.1109/VLSIT.2002.1015379","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015379","url":null,"abstract":"This paper investigates the impact of Joule heating on the scaling trends of advanced VLSI interconnects. It shows that the interconnect Joule heating can strongly affect the maximum operating temperature of the global wires which, in turn, will constrain the scaling of current density to mitigate electromigration and, thus greatly degrade the expected speed improvement from the use of low-k dielectrics. Through a combination of extensive electrothermal simulation and 2D field solver for capacitance calculation, the thermal characteristics of various Cu/low-k schemes are quantified and their effects on electromigration reliability and interconnect delay are determined. The effect of vias, as efficient heat conduction paths, is included for realistic evaluation. Our analysis suggests that Joule heating will be a bottleneck in scaling interconnects and projections of International Technology Roadmap for Semiconductors (ITRS'01) will not be met.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128536105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015383
Y. Hirano, T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa, Y. Inoue
It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.
实验证明，带部分沟槽隔离(PTI)的体系SOI技术具有显著的高软误差抗扰性。与普通SRAM相比，采用PTI的0.18 /spl mu/m SOI 4mbit SRAM，通过平衡SOI厚度和井阻，成功地将软误差率降低了3个数量级。据估计，由于浮体撞击和漏极撞击都会引起大量电荷收集，导致浮体装置的软误差抗扰度下降。提出了一种抑制软误差的SOI结构设计准则。根据指南，在0.13 /spl mu/m节点以上，与体系SOI器件和浮体SOI器件相比，体系SOI器件预计具有较高的软误差抗免疫力。
{"title":"High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices","authors":"Y. Hirano, T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa, Y. Inoue","doi":"10.1109/VLSIT.2002.1015383","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015383","url":null,"abstract":"It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015372
K. Onishi, C. Kang, R. Choi, Hag-ju Cho, S. Gopalan, R. Nieh, S. Krishnan, J.C. Lee
Effects of forming gas (FG) annealing on HfO/sub 2/ MOSFET performance have been studied. High-temperature (500-600/spl deg/C) FG annealing has been shown to significantly improve carrier mobility and subthreshold slopes for both N and PMOSFETs. The improvement has been correlated to the reduction in interfacial state density. The effectiveness of FG annealing has also been examined on samples that underwent surface preparations with NH/sub 3/ or NO annealing prior to HfO/sub 2/ deposition. It was found that FG annealing did not degrade PMOS negative bias temperature instability characteristics.
{"title":"Effects of high-temperature forming gas anneal on HfO/sub 2/ MOSFET performance","authors":"K. Onishi, C. Kang, R. Choi, Hag-ju Cho, S. Gopalan, R. Nieh, S. Krishnan, J.C. Lee","doi":"10.1109/VLSIT.2002.1015372","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015372","url":null,"abstract":"Effects of forming gas (FG) annealing on HfO/sub 2/ MOSFET performance have been studied. High-temperature (500-600/spl deg/C) FG annealing has been shown to significantly improve carrier mobility and subthreshold slopes for both N and PMOSFETs. The improvement has been correlated to the reduction in interfacial state density. The effectiveness of FG annealing has also been examined on samples that underwent surface preparations with NH/sub 3/ or NO annealing prior to HfO/sub 2/ deposition. It was found that FG annealing did not degrade PMOS negative bias temperature instability characteristics.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"484 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116617753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015386
Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, M. Huh, G. Jeong, J. Suh, Hoyeop Kweon, J. Roh, Kisoo Shin, Sangdon Lee
The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.
{"title":"A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM","authors":"Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, M. Huh, G. Jeong, J. Suh, Hoyeop Kweon, J. Roh, Kisoo Shin, Sangdon Lee","doi":"10.1109/VLSIT.2002.1015386","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015386","url":null,"abstract":"The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122929804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015441
S. Ahn, G. Jung, C. Cho, S. shin, J.Y. Lee, J.G. Lee, H. Jeong, Kinam Kim
A novel DRAM cell transistor with an asymmetric source and drain structure is proposed, for the first time, to realize reliable high density DRAM below 0.12 /spl mu/m. The new cell structure could provide the optimized source and drain junction profiles independently. The junction profile at the storage node (SN) was designed to reduce electric field to minimize junction leakage current and thereby improving data retention time. On the other hand, the junction profile at the bit-line direct contact node (DC) was designed to suppress short channel effects of a cell transistor. It is considered to be highly scalable for device scaling and to solve fine printing and precise alignment requirements. The validity of the approach was directly confirmed by improvement in the refresh times of 512 Mb DRAM which was fabricated with 0.12 /spl mu/m DRAM technology.
{"title":"Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics","authors":"S. Ahn, G. Jung, C. Cho, S. shin, J.Y. Lee, J.G. Lee, H. Jeong, Kinam Kim","doi":"10.1109/VLSIT.2002.1015441","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015441","url":null,"abstract":"A novel DRAM cell transistor with an asymmetric source and drain structure is proposed, for the first time, to realize reliable high density DRAM below 0.12 /spl mu/m. The new cell structure could provide the optimized source and drain junction profiles independently. The junction profile at the storage node (SN) was designed to reduce electric field to minimize junction leakage current and thereby improving data retention time. On the other hand, the junction profile at the bit-line direct contact node (DC) was designed to suppress short channel effects of a cell transistor. It is considered to be highly scalable for device scaling and to solve fine printing and precise alignment requirements. The validity of the approach was directly confirmed by improvement in the refresh times of 512 Mb DRAM which was fabricated with 0.12 /spl mu/m DRAM technology.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129597007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015442
J. Lutzen, A. Birner, M. Goldbach, M. Gutsche, T. Hecht, S. Jakschik, A. Orth, A. Sanger, U. Schroder, H. Seidl, B. Sell, D. Schumann
One of the key enablers in scaling DRAM trench capacitors to sub-100 nm ground rules is a viable collar integration concept. We report, for the first time, the successful implementation of a buried collar concept, which leaves ample space for the connection from the array device to the inner electrode. The new collar integration scheme is fully compatible with a number of capacitance enhancement techniques including surface enlargement by trench widening, HSG deposition as well as the utilization of high-k node dielectrics such as Al/sub 2/O/sub 3/. These capacitance enhancement techniques are required to maintain a capacitance in excess of 30 fF/cell. In addition, a metal fill of the deep trench is necessary to maintain a low series resistance of the inner electrode, which is also demonstrated for the first time. The successful integration of these key enablers in deep trenches is presented.
{"title":"Integration of capacitor for sub-100-nm DRAM trench technology","authors":"J. Lutzen, A. Birner, M. Goldbach, M. Gutsche, T. Hecht, S. Jakschik, A. Orth, A. Sanger, U. Schroder, H. Seidl, B. Sell, D. Schumann","doi":"10.1109/VLSIT.2002.1015442","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015442","url":null,"abstract":"One of the key enablers in scaling DRAM trench capacitors to sub-100 nm ground rules is a viable collar integration concept. We report, for the first time, the successful implementation of a buried collar concept, which leaves ample space for the connection from the array device to the inner electrode. The new collar integration scheme is fully compatible with a number of capacitance enhancement techniques including surface enlargement by trench widening, HSG deposition as well as the utilization of high-k node dielectrics such as Al/sub 2/O/sub 3/. These capacitance enhancement techniques are required to maintain a capacitance in excess of 30 fF/cell. In addition, a metal fill of the deep trench is necessary to maintain a low series resistance of the inner electrode, which is also demonstrated for the first time. The successful integration of these key enablers in deep trenches is presented.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015429
R. Tsuchiya, K. Ohnishi, M. Horiuchi, S. Tsujikawa, Y. Shimamoto, N. Inada, J. Yugami, F. Ootsuka, T. Onai
We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.
{"title":"Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface","authors":"R. Tsuchiya, K. Ohnishi, M. Horiuchi, S. Tsujikawa, Y. Shimamoto, N. Inada, J. Yugami, F. Ootsuka, T. Onai","doi":"10.1109/VLSIT.2002.1015429","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015429","url":null,"abstract":"We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127774992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015399
Jong-Ho Lee, Yun-seok Kim, Hyung-Seok Jung, Jung-Hyoung Lee, N. Lee, Ho-Kyu Kang, J. Ku, Heesoo Kang, Youn-Keun Kim, K. Cho, K. Suh
For the first time, we have integrated poly-Si gate CMOS-FETs with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric (EOT=14.6 /spl Aring/) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7 /spl mu/A/cm/sup 2/ (Vg=+1.0 V) for nMOSFET and 0.2 /spl mu/A/cm/sup 2/ (Vg=-1.0 V) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT= 12/spl sim/20 /spl Aring/, Jg=2.2 mA/cm/sup 2/) estimated by ITRS. The fixed charge is decreased using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric, and consequently flatband voltage (Vfb) shift is within 0.20 V compared with the Vfb of nitrided SiO/sub 2/ control. In addition, a low gate induced drain leakage (GIDL) is obtained using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric. I/sub on/ vs. I/sub off/ plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2 V Vdd are 430 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for nMOSFET and 160 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.
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