Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015377
N. Oda, S. Ito, T. Takewaki, H. Kunishima, N. Hironaga, I. Honma, H. Namba, S. Yokogawa, T. Goto, T. Usami, K. Ohto, A. Kubo, H. Aoki, M. Suzuki, Y. Yamamoto, S. Watanabe, T. Takeda, K. Yamada, M. Kosaka, T. Horiuchi
A robust embedded ladder-oxide (k=2.9)/Cu multilevel interconnect is demonstrated for the 0.13 /spl mu/m CMOS generation. A stable ladder-oxide IMD is integrated into the Cu metallization with minimum wiring pitch of 0.34 /spl mu/m, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with SiO/sub 2/ IMD. The stress-migration lifetime of vias on wide metals for S/D Cu-plug structure is much longer than for dual damascene (D/D). The reliability test results such as those for electromigration (EM), Cu interconnect TDDB, and pressure cooker test (PCT) are quite acceptable. Moreover, high flexibility in thermal design and packaging is obtained.
{"title":"A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 /spl mu/m CMOS generation","authors":"N. Oda, S. Ito, T. Takewaki, H. Kunishima, N. Hironaga, I. Honma, H. Namba, S. Yokogawa, T. Goto, T. Usami, K. Ohto, A. Kubo, H. Aoki, M. Suzuki, Y. Yamamoto, S. Watanabe, T. Takeda, K. Yamada, M. Kosaka, T. Horiuchi","doi":"10.1109/VLSIT.2002.1015377","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015377","url":null,"abstract":"A robust embedded ladder-oxide (k=2.9)/Cu multilevel interconnect is demonstrated for the 0.13 /spl mu/m CMOS generation. A stable ladder-oxide IMD is integrated into the Cu metallization with minimum wiring pitch of 0.34 /spl mu/m, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with SiO/sub 2/ IMD. The stress-migration lifetime of vias on wide metals for S/D Cu-plug structure is much longer than for dual damascene (D/D). The reliability test results such as those for electromigration (EM), Cu interconnect TDDB, and pressure cooker test (PCT) are quite acceptable. Moreover, high flexibility in thermal design and packaging is obtained.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134348150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015443
K. McStay, D. Chidambarrao, J. Mandelman, J. Beintner, H. Tews, M. Weybright, G. Wang, Y. Li, K. Hummler, R. Divakaruni, W. Bergner, E. Crabbé, G. Bronner, W. Müller
The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.
{"title":"Vertical pass transistor design for sub-100 nm DRAM technologies","authors":"K. McStay, D. Chidambarrao, J. Mandelman, J. Beintner, H. Tews, M. Weybright, G. Wang, Y. Li, K. Hummler, R. Divakaruni, W. Bergner, E. Crabbé, G. Bronner, W. Müller","doi":"10.1109/VLSIT.2002.1015443","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015443","url":null,"abstract":"The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"415 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113995855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015433
Han-Su Kim, K. Chong, Yahong Xie, M. Devincentis, T. Itoh, A. Becker, K. Jenkins
A novel isolation technology for RF applications based on semi-insulating porous Si (PS) is demonstrated. RF cross-talk isolation of 70 dB at 2 GHz and -45 dB at 8 GHz has been demonstrated using PS trenches that provide complete isolation between neighboring regions of a p/sup +/ Si chip. On-chip spiral inductors of 6 nH fabricated over the PS regions have been demonstrated with Q/sub max/ /spl sim/29 at 7 GHz and a resonant frequency of over 20 GHz.
{"title":"A porous Si based novel isolation technology for mixed-signal integrated circuits","authors":"Han-Su Kim, K. Chong, Yahong Xie, M. Devincentis, T. Itoh, A. Becker, K. Jenkins","doi":"10.1109/VLSIT.2002.1015433","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015433","url":null,"abstract":"A novel isolation technology for RF applications based on semi-insulating porous Si (PS) is demonstrated. RF cross-talk isolation of 70 dB at 2 GHz and -45 dB at 8 GHz has been demonstrated using PS trenches that provide complete isolation between neighboring regions of a p/sup +/ Si chip. On-chip spiral inductors of 6 nH fabricated over the PS regions have been demonstrated with Q/sub max/ /spl sim/29 at 7 GHz and a resonant frequency of over 20 GHz.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116390149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015416
D.H. Kim, S. Kim, B. Hwang, S.H. Seo, J. Choi, H.S. Lee, W.S. Yang, M. Kim, K. Kwak, J.Y. Lee, J. Joo, J. Kim, K. Koh, S. Park, J. Hong
For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.
{"title":"Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation","authors":"D.H. Kim, S. Kim, B. Hwang, S.H. Seo, J. Choi, H.S. Lee, W.S. Yang, M. Kim, K. Kwak, J.Y. Lee, J. Joo, J. Kim, K. Koh, S. Park, J. Hong","doi":"10.1109/VLSIT.2002.1015416","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015416","url":null,"abstract":"For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127212474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015376
S. Takahashi, K. Tai, H. Ohtorii, N. Komai, Y. Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M. Ishihara, T. Nogami
A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.
{"title":"Fragile porous low-k/copper integration by using electro-chemical polishing","authors":"S. Takahashi, K. Tai, H. Ohtorii, N. Komai, Y. Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M. Ishihara, T. Nogami","doi":"10.1109/VLSIT.2002.1015376","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015376","url":null,"abstract":"A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114649736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015381
N. Kotani, S. Ito, T. Yasui, A. Wada, T. Yamaoka, T. Hori
This paper clarifies two SOI-specific leakage components, STI-induced punchthrough and gate-oxide leakage, found especially in large-scale integration, and proposes a new SOI technology: silicon-sidewall body-contact (SSBC). Without layout penalty and process complexity, SSBC realizes self-aligned body contact to the substrate, which suppresses gate-oxide leakage, and prevents the SOI body from being mechanically stressed, thus eliminating punchthrough leakage. SSBC is promising for scaled SOI CMOS LSIs.
{"title":"Suppression of leakage current in SOI CMOS LSIs by using silicon-sidewall body-contact (SSBC) technology","authors":"N. Kotani, S. Ito, T. Yasui, A. Wada, T. Yamaoka, T. Hori","doi":"10.1109/VLSIT.2002.1015381","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015381","url":null,"abstract":"This paper clarifies two SOI-specific leakage components, STI-induced punchthrough and gate-oxide leakage, found especially in large-scale integration, and proposes a new SOI technology: silicon-sidewall body-contact (SSBC). Without layout penalty and process complexity, SSBC realizes self-aligned body contact to the substrate, which suppresses gate-oxide leakage, and prevents the SOI body from being mechanically stressed, thus eliminating punchthrough leakage. SSBC is promising for scaled SOI CMOS LSIs.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127055316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015374
Y. Harada, M. Niwa, Sungjoo Lee, D. Kwong
We report on two key issues for CVD-HfO/sub 2/ gate dielectric which influence their reliability. The first is extrinsic defects, i.e. two types of extrinsic defects which lead to large electrical leakage. The other issue is interfaces inside the film, i.e. stoichiometric interfaces due to Si out-diffusion from the substrate, and interfaces defined by dielectric constant transitions formed by a diffusion mechanism of Si into HfO/sub 2/. Lower Weibull slope /spl beta/ is mainly determined by the distance from the Si substrate to the k-transition interface. Although /spl beta/ becomes smaller due to the k-transition interface, it was clarified to be improved by a single layered silicate without k-transition interface.
{"title":"Specific structural factors influencing on reliability of CVD-HfO/sub 2/","authors":"Y. Harada, M. Niwa, Sungjoo Lee, D. Kwong","doi":"10.1109/VLSIT.2002.1015374","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015374","url":null,"abstract":"We report on two key issues for CVD-HfO/sub 2/ gate dielectric which influence their reliability. The first is extrinsic defects, i.e. two types of extrinsic defects which lead to large electrical leakage. The other issue is interfaces inside the film, i.e. stoichiometric interfaces due to Si out-diffusion from the substrate, and interfaces defined by dielectric constant transitions formed by a diffusion mechanism of Si into HfO/sub 2/. Lower Weibull slope /spl beta/ is mainly determined by the distance from the Si substrate to the k-transition interface. Although /spl beta/ becomes smaller due to the k-transition interface, it was clarified to be improved by a single layered silicate without k-transition interface.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122088105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015448
P. Chen, E. Cartier, R. Carter, T. Kauerauf, C. Zhao, J. Pétry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Copel, W. Besling, P. Bajolet, J. Maes
It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.
{"title":"Thermal stability and scalability of Zr-aluminate-based high-k gate stacks","authors":"P. Chen, E. Cartier, R. Carter, T. Kauerauf, C. Zhao, J. Pétry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Copel, W. Besling, P. Bajolet, J. Maes","doi":"10.1109/VLSIT.2002.1015448","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015448","url":null,"abstract":"It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015445
R. Nieh, S. Krishnan, Hag-ju Cho, C. Kang, S. Gopalan, K. Onishi, R. Choi, J.C. Lee
Both NMOSCAP and self-aligned NMOSFET devices using TaN gates were fabricated and characterized in order to compare ZrO/sub 2/ and nitrogen-incorporated ZrO/sub 2/ (ZrO/sub x/N/sub y/) gate dielectrics (EOT/spl sim/10.3/spl Aring/). ZrO/sub x/N/sub y/ devices demonstrated excellent thermal stability, comparable leakage current, higher breakdown field, decreased subthreshold swing, and improved drive current over ZrO/sub x/ devices. Polysilicon-gated NMOSCAPs were also fabricated to investigate the compatibility of ZrO/sub x/N/sub y/ with the poly process (EOT/spl sim/19/spl Aring/), but high leakage and TEM analysis revealed interaction between the poly and ZrO/sub x/N/sub y/.
{"title":"Comparison between ultra-thin ZrO/sub 2/ and ZrO/sub x/N/sub y/ gate dielectrics in TaN or poly-gated NMOSCAP and NMOSFET devices","authors":"R. Nieh, S. Krishnan, Hag-ju Cho, C. Kang, S. Gopalan, K. Onishi, R. Choi, J.C. Lee","doi":"10.1109/VLSIT.2002.1015445","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015445","url":null,"abstract":"Both NMOSCAP and self-aligned NMOSFET devices using TaN gates were fabricated and characterized in order to compare ZrO/sub 2/ and nitrogen-incorporated ZrO/sub 2/ (ZrO/sub x/N/sub y/) gate dielectrics (EOT/spl sim/10.3/spl Aring/). ZrO/sub x/N/sub y/ devices demonstrated excellent thermal stability, comparable leakage current, higher breakdown field, decreased subthreshold swing, and improved drive current over ZrO/sub x/ devices. Polysilicon-gated NMOSCAPs were also fabricated to investigate the compatibility of ZrO/sub x/N/sub y/ with the poly process (EOT/spl sim/19/spl Aring/), but high leakage and TEM analysis revealed interaction between the poly and ZrO/sub x/N/sub y/.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117200223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015393
S. Song, S. Filipiak, A. Perera, M. Turner, F. Huang, S. Anderson, L. Kang, B. Min, D. Menke, S. Tukunang, S. Venkatesan
Significantly reduced plasma damage is demonstrated by including a thin conductive top film (CTF) on the contact etch stop layer (ESL) for the first time, which effectively blocks radiation generated by subsequent high density plasma processes. We also show that plasma damage exacerbates negative bias temperature instability (NBTI) in PMOSFETs and can be effectively suppressed by the CTF process.
{"title":"Avoiding plasma induced damage to gate oxide with conductive top film (CTF) on PECVD contact etch stop layer","authors":"S. Song, S. Filipiak, A. Perera, M. Turner, F. Huang, S. Anderson, L. Kang, B. Min, D. Menke, S. Tukunang, S. Venkatesan","doi":"10.1109/VLSIT.2002.1015393","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015393","url":null,"abstract":"Significantly reduced plasma damage is demonstrated by including a thin conductive top film (CTF) on the contact etch stop layer (ESL) for the first time, which effectively blocks radiation generated by subsequent high density plasma processes. We also show that plasma damage exacerbates negative bias temperature instability (NBTI) in PMOSFETs and can be effectively suppressed by the CTF process.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133883070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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