Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606633
Zhongming Shi, K. Hsu, O. Salminen, P. Wang, J. Vahe, K. Kaltiokallio
This work presents the design and measurement results of a novel second-order demodulator for high-resolution sigma-delta digital to analog converters. The demodulator combines digital to analog converting and second-order lowpass filtering into a single step, therefore, eliminating conventionally required post analog filter. This approach offers a large reduction both in chip size and power consumption. A 14-bit fully differential second-order demodulator has been designed and implemented in a complete 2.4 V cellular baseband chip by using a double-poly and triple-metal 0.5 /spl mu/m low-power CMOS process. The total active chip area and power consumption of the demodulator are 0.18 mm/sup 2/ and 700 /spl mu/W, respectively.
{"title":"A 2.4 V, 700 /spl mu/W, 0.18 mm/sup 2/ second-order demodulator for high-resolution /spl Sigma//spl Delta/ DACs","authors":"Zhongming Shi, K. Hsu, O. Salminen, P. Wang, J. Vahe, K. Kaltiokallio","doi":"10.1109/CICC.1997.606633","DOIUrl":"https://doi.org/10.1109/CICC.1997.606633","url":null,"abstract":"This work presents the design and measurement results of a novel second-order demodulator for high-resolution sigma-delta digital to analog converters. The demodulator combines digital to analog converting and second-order lowpass filtering into a single step, therefore, eliminating conventionally required post analog filter. This approach offers a large reduction both in chip size and power consumption. A 14-bit fully differential second-order demodulator has been designed and implemented in a complete 2.4 V cellular baseband chip by using a double-poly and triple-metal 0.5 /spl mu/m low-power CMOS process. The total active chip area and power consumption of the demodulator are 0.18 mm/sup 2/ and 700 /spl mu/W, respectively.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114354052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606645
R. Sáez, M. Kayal, M. Declercq
This paper presents a detailed analysis of the CMOS Current Steering Logic (CSL) technique and compares experimentally its digital switching noise to that of the CMOS static logic. Theoretical analysis of the CSL inverter is developed. More complex gates using this technique are presented. Results are validated by simulations and measurement.
{"title":"CMOS current steering logic: Toward a matured technique for mixed-mode applications","authors":"R. Sáez, M. Kayal, M. Declercq","doi":"10.1109/CICC.1997.606645","DOIUrl":"https://doi.org/10.1109/CICC.1997.606645","url":null,"abstract":"This paper presents a detailed analysis of the CMOS Current Steering Logic (CSL) technique and compares experimentally its digital switching noise to that of the CMOS static logic. Theoretical analysis of the CSL inverter is developed. More complex gates using this technique are presented. Results are validated by simulations and measurement.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114491397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606590
K. Halonen, S. Lindfors, J. Jussila, L. Siren
This paper describes a low-voltage channel selection analog front-end with continuous-time filters and on-chip tuning. The filters were realized as balanced seventh order elliptical g/sub m/ C-filters to achieve low current consumption. A novel floating resistor based transconductor was developed to satisfy stringent intermodulation distortion specification and to fulfil the requirement for low supply voltage. A novel biasing for high-swing cascode output stages that extends the practical signal swing capability was developed. A digital tuning circuit based on a time-domain integrator was realized.
{"title":"A 3V g/sub M/ C-filter with on-chip tuning for CDMA","authors":"K. Halonen, S. Lindfors, J. Jussila, L. Siren","doi":"10.1109/CICC.1997.606590","DOIUrl":"https://doi.org/10.1109/CICC.1997.606590","url":null,"abstract":"This paper describes a low-voltage channel selection analog front-end with continuous-time filters and on-chip tuning. The filters were realized as balanced seventh order elliptical g/sub m/ C-filters to achieve low current consumption. A novel floating resistor based transconductor was developed to satisfy stringent intermodulation distortion specification and to fulfil the requirement for low supply voltage. A novel biasing for high-swing cascode output stages that extends the practical signal swing capability was developed. A digital tuning circuit based on a time-domain integrator was realized.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606684
R. Patel, W. Wong, J. Lam, T. Lai, T. White, S. Cheung
This paper discusses a 3.3 V programmable logic device family which provides up to 130 Kgates. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 6,656 logic elements and circuit techniques to address low power supply and interface trends. It is designed on a 0.35 /spl mu/m triple metal-dual oxide process to operate in a 3.3 V only, 5 V only or 3.3 V-5 V systems. Under worst case operating conditions it was observed to have a typical system operating frequency of 90 MHz. The EPF10K50V is the first member of the second-generation FLEX 10K family.
{"title":"A 3.3-V programmable logic device that addresses low power supply and interface trends","authors":"R. Patel, W. Wong, J. Lam, T. Lai, T. White, S. Cheung","doi":"10.1109/CICC.1997.606684","DOIUrl":"https://doi.org/10.1109/CICC.1997.606684","url":null,"abstract":"This paper discusses a 3.3 V programmable logic device family which provides up to 130 Kgates. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 6,656 logic elements and circuit techniques to address low power supply and interface trends. It is designed on a 0.35 /spl mu/m triple metal-dual oxide process to operate in a 3.3 V only, 5 V only or 3.3 V-5 V systems. Under worst case operating conditions it was observed to have a typical system operating frequency of 90 MHz. The EPF10K50V is the first member of the second-generation FLEX 10K family.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127295831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606675
F. Wang, R. Harjani
We present a new analytical model for opamp induced nonlinearity in oversampled converters. This model incorporates both finite slew rate and finite gain bandwidth effects and is valid for both first order and higher order modulators. Theoretical predictions agree very well with measured results from fabricated ICs. The model consists only of circuit design parameters, and can be utilized to explore design tradeoffs and optimize converter performance. For our design the use of our model resulted in a 40% reduction in power consumption without loss of performance.
{"title":"Nonlinear settling behavior in oversampled converters","authors":"F. Wang, R. Harjani","doi":"10.1109/CICC.1997.606675","DOIUrl":"https://doi.org/10.1109/CICC.1997.606675","url":null,"abstract":"We present a new analytical model for opamp induced nonlinearity in oversampled converters. This model incorporates both finite slew rate and finite gain bandwidth effects and is valid for both first order and higher order modulators. Theoretical predictions agree very well with measured results from fabricated ICs. The model consists only of circuit design parameters, and can be utilized to explore design tradeoffs and optimize converter performance. For our design the use of our model resulted in a 40% reduction in power consumption without loss of performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"2839 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127446348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606602
G. van der Plas, J. Vandenbussche, G. Gielen, W. Sansen
A novel methodology to derive power and area is presented. The method consists of the generation of a training set and a subsequent training of an Artificial Neural Network. The resulting estimators do not only predict power and area accurately and efficiently, they also reflect the complex interaction between different specifications. The method has been implemented in a tool, EsteMate, and is illustrated with practical examples.
{"title":"EsteMate: a tool for automated power and area estimation in analog top-down design and synthesis","authors":"G. van der Plas, J. Vandenbussche, G. Gielen, W. Sansen","doi":"10.1109/CICC.1997.606602","DOIUrl":"https://doi.org/10.1109/CICC.1997.606602","url":null,"abstract":"A novel methodology to derive power and area is presented. The method consists of the generation of a training set and a subsequent training of an Artificial Neural Network. The resulting estimators do not only predict power and area accurately and efficiently, they also reflect the complex interaction between different specifications. The method has been implemented in a tool, EsteMate, and is illustrated with practical examples.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606648
N. Verghese, D. Allstot
This paper introduces the substrate coupling problem in RF and mixed-signal integrated circuits and discusses methods for its verification. Special emphasis is placed on modeling techniques for the substrate. A methodology is presented that utilizes macromodels of the circuit, substrate and package for efficient simulation of substrate coupling. A design example illustrates an application of such a methodology.
{"title":"Verification of RF and mixed-signal integrated circuits for substrate coupling effects","authors":"N. Verghese, D. Allstot","doi":"10.1109/CICC.1997.606648","DOIUrl":"https://doi.org/10.1109/CICC.1997.606648","url":null,"abstract":"This paper introduces the substrate coupling problem in RF and mixed-signal integrated circuits and discusses methods for its verification. Special emphasis is placed on modeling techniques for the substrate. A methodology is presented that utilizes macromodels of the circuit, substrate and package for efficient simulation of substrate coupling. A design example illustrates an application of such a methodology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126718061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606639
Jind-Yeh Lee, Huan-Chang Liu, J. Putnam, K. Kindsfater, H. Samueli
A VLSI implementation of an integrated complete adaptive beamforming processor and QAM demodulator is presented. The adaptive beamforming processor includes variable number of adaptive beamforming channel combining, a fully writable training processor, a programmable adaptive beamforming control processor, and a microcontroller interface. Interleaving area intensive blocks such as the Nyquist filters and multipliers is often employed to save chip area and thus enable the integration of all these features into a single chip. This chip can operate as a stand alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for the high bit-rate indoor wireless applications. In a 2.22 dB SINR interference environment, the receiver achieves a link quality of 32.6 dB SNR by the digital adaptive beamforming processing.
{"title":"A 42 MB/S multi-channel digital adaptive beamforming QAM demodulator for wireless applications","authors":"Jind-Yeh Lee, Huan-Chang Liu, J. Putnam, K. Kindsfater, H. Samueli","doi":"10.1109/CICC.1997.606639","DOIUrl":"https://doi.org/10.1109/CICC.1997.606639","url":null,"abstract":"A VLSI implementation of an integrated complete adaptive beamforming processor and QAM demodulator is presented. The adaptive beamforming processor includes variable number of adaptive beamforming channel combining, a fully writable training processor, a programmable adaptive beamforming control processor, and a microcontroller interface. Interleaving area intensive blocks such as the Nyquist filters and multipliers is often employed to save chip area and thus enable the integration of all these features into a single chip. This chip can operate as a stand alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for the high bit-rate indoor wireless applications. In a 2.22 dB SINR interference environment, the receiver achieves a link quality of 32.6 dB SNR by the digital adaptive beamforming processing.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"241 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606661
R. Tang, J. Ford, B. Pryor, S. Anandakugan, P. Welch, K. Ginn, C. Burt, B. Yeung, J. Babcock
SiGe HBTs with low 1/f noise, low base resistance (for low noise figure and high f/sub max/) and high intrinsic gain and breakdown voltage provide design leverage for RF communication applications. This work describes an optimal extrinsic base fabrication for SiGe HBTs, achieving f/sub max/ increased 2 times, R/sub B/ reduced 50%, noise figure at 900 MHz reduced about 0.5 dB, 1/f noise reduced 10 times, and current gain increased 2 times. Breakdown voltage V/sub CEO/ is larger than 8.0 V, sufficient for 3 V operations. Those results have been achieved at no additional mask or process steps to the conventional base-line process.
{"title":"Optimal extrinsic base fabrication for high performance SiGe HBTs for RF communication applications","authors":"R. Tang, J. Ford, B. Pryor, S. Anandakugan, P. Welch, K. Ginn, C. Burt, B. Yeung, J. Babcock","doi":"10.1109/CICC.1997.606661","DOIUrl":"https://doi.org/10.1109/CICC.1997.606661","url":null,"abstract":"SiGe HBTs with low 1/f noise, low base resistance (for low noise figure and high f/sub max/) and high intrinsic gain and breakdown voltage provide design leverage for RF communication applications. This work describes an optimal extrinsic base fabrication for SiGe HBTs, achieving f/sub max/ increased 2 times, R/sub B/ reduced 50%, noise figure at 900 MHz reduced about 0.5 dB, 1/f noise reduced 10 times, and current gain increased 2 times. Breakdown voltage V/sub CEO/ is larger than 8.0 V, sufficient for 3 V operations. Those results have been achieved at no additional mask or process steps to the conventional base-line process.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115294112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606576
S. Baumgartner, L. Freitag, H. Paschal, D. Siljenberg
This paper presents the first reported integrated 1.25 Gbit/s post amplifier and laser driver, to the authors knowledge. The post amplifier amplifies 20 mV signals from a pre-amplifier and provides redundant loss of signal detectors. The laser driver provides up to 100 mA DC drive and 25 mA/sub p-p/ C drive. This presents a large on chip isolation challenge and 79 dB of isolation was achieved. The chip has sufficient redundancy and error detection to provide international Class 1 laser safety certification. The chip operated up to 1.6 Gb/s. The design is implemented in a 0.45 um L/sub eff/ BiCMOS technology with 12 GHz NPN's. It is packaged in a 48 lead 7 mm plastic quad flat pack surface mount package.
{"title":"An integrated 1.25 Gbit/s laser driver/post amplifer IC","authors":"S. Baumgartner, L. Freitag, H. Paschal, D. Siljenberg","doi":"10.1109/CICC.1997.606576","DOIUrl":"https://doi.org/10.1109/CICC.1997.606576","url":null,"abstract":"This paper presents the first reported integrated 1.25 Gbit/s post amplifier and laser driver, to the authors knowledge. The post amplifier amplifies 20 mV signals from a pre-amplifier and provides redundant loss of signal detectors. The laser driver provides up to 100 mA DC drive and 25 mA/sub p-p/ C drive. This presents a large on chip isolation challenge and 79 dB of isolation was achieved. The chip has sufficient redundancy and error detection to provide international Class 1 laser safety certification. The chip operated up to 1.6 Gb/s. The design is implemented in a 0.45 um L/sub eff/ BiCMOS technology with 12 GHz NPN's. It is packaged in a 48 lead 7 mm plastic quad flat pack surface mount package.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124950171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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