Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606630
A. Makynen, T. Rahkonen, J. Kostamovaara
Implementation and test results of a 16 by 16 binary CMOS photodetector array for position sensing applications is presented. Unlike conventional position sensitive detectors (PSDs), it is capable of simultaneous multiple spot detection with high accuracy. To decrease signal processing overhead characteristic of this kind of area arrays, binary detection with on-site thresholding and random access readout is used. The fill factor and pitch of the array are 30% and 50 /spl mu/m, respectively. Quantization limited position sensing accuracy of 4.3 /spl mu/m is achieved using spot of a 280 /spl mu/m in diameter, total signal power of about 8 nW and pulse width of 8 ms. The sensitivity is limited by the spatial noise caused by the mismatch of threshold setting current mirrors operating in weak inversion.
{"title":"A CMOS binary position-sensitive photodetector (PSD) array","authors":"A. Makynen, T. Rahkonen, J. Kostamovaara","doi":"10.1109/CICC.1997.606630","DOIUrl":"https://doi.org/10.1109/CICC.1997.606630","url":null,"abstract":"Implementation and test results of a 16 by 16 binary CMOS photodetector array for position sensing applications is presented. Unlike conventional position sensitive detectors (PSDs), it is capable of simultaneous multiple spot detection with high accuracy. To decrease signal processing overhead characteristic of this kind of area arrays, binary detection with on-site thresholding and random access readout is used. The fill factor and pitch of the array are 30% and 50 /spl mu/m, respectively. Quantization limited position sensing accuracy of 4.3 /spl mu/m is achieved using spot of a 280 /spl mu/m in diameter, total signal power of about 8 nW and pulse width of 8 ms. The sensitivity is limited by the spatial noise caused by the mismatch of threshold setting current mirrors operating in weak inversion.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127719844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606658
W.M. Huang, Y. Tseng, D. Monk, D. Diaz, J. Ford, S. Cheng
Recent growth in the portable wireless communication market has driven semiconductor technologies toward voltage and power reduction. The reduced junction capacitance and near-ideal MOS device characteristics of SOI provides an inherent advantage for low-voltage low-power applications. Substantial progress in applying SOI technology for these applications has been demonstrated in recent years. The quest for a single chip system has also initiated work in developing high frequency and analog SOI circuits. In this paper, the application of Thin-Film-Silicon-On-Insulator (TFSOI) technology for wireless communication systems is reviewed and future development discussed.
{"title":"TFSOI technology for portable wireless communication systems","authors":"W.M. Huang, Y. Tseng, D. Monk, D. Diaz, J. Ford, S. Cheng","doi":"10.1109/CICC.1997.606658","DOIUrl":"https://doi.org/10.1109/CICC.1997.606658","url":null,"abstract":"Recent growth in the portable wireless communication market has driven semiconductor technologies toward voltage and power reduction. The reduced junction capacitance and near-ideal MOS device characteristics of SOI provides an inherent advantage for low-voltage low-power applications. Substantial progress in applying SOI technology for these applications has been demonstrated in recent years. The quest for a single chip system has also initiated work in developing high frequency and analog SOI circuits. In this paper, the application of Thin-Film-Silicon-On-Insulator (TFSOI) technology for wireless communication systems is reviewed and future development discussed.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127933883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606619
S. Okada, Y. Matsuda, T. Watanabe, K. Kondo
We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640/spl times/480) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI uses compression ratio control to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer so that it can process signals at high speed without using high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW) for broader application in image processing in consumer markets.
{"title":"A single chip motion JPEG codec LSI","authors":"S. Okada, Y. Matsuda, T. Watanabe, K. Kondo","doi":"10.1109/CICC.1997.606619","DOIUrl":"https://doi.org/10.1109/CICC.1997.606619","url":null,"abstract":"We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640/spl times/480) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI uses compression ratio control to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer so that it can process signals at high speed without using high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW) for broader application in image processing in consumer markets.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132607981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606625
P. Favrat, P. Deval, M. Declercq
A charge pump cell is used to make a voltage doubler using improved serial switches. The PMOS transistor used for the serial switch is analyzed and a model suitable for simulation is described. The importance of capacitors is shown with plots of efficiency versus load and stray capacitance. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. An efficiency of 94% has been reached using external capacitors.
{"title":"A new high efficiency CMOS voltage doubler","authors":"P. Favrat, P. Deval, M. Declercq","doi":"10.1109/CICC.1997.606625","DOIUrl":"https://doi.org/10.1109/CICC.1997.606625","url":null,"abstract":"A charge pump cell is used to make a voltage doubler using improved serial switches. The PMOS transistor used for the serial switch is analyzed and a model suitable for simulation is described. The importance of capacitors is shown with plots of efficiency versus load and stray capacitance. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. An efficiency of 94% has been reached using external capacitors.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133833839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606631
M. Steyaert, V. Peluso, J. Bastos, P. Kinget, W. Sansen
The never ending story of technology trends towards smaller transistor dimensions have resulted to date in deep submicron transistors. The consequence is the down scaling of the power supply voltages, to date even lower than 2 V, with almost the same threshold voltages of the CMOS transistors. Those low voltages mean that some widespread techniques such as switched-capacitors cannot be implemented anymore. On the other hand custom integrated circuits require continually higher speeds, more accuracy and less power drain. In the first section, the impact of mismatch or accuracy in analog circuits and the impact on power drain is discussed. Secondly, in section two some fundamental limitations of analog integrated circuit design in the trade-off between speed, accuracy and power drain are analysed. In the third section the problem of very low voltage signal processing in switched-capacitor circuits is studied. Some solutions, such as the switched-opamp technique are presented, and the technique is demonstrated by the design of a very low power, low voltage sigma delta modulator. The design and the measurements of 12 bit sigma delta AD converters running at 1.5 V power supply voltage and consuming less than 100 /spl mu/W in standard CMOS technology are finally discussed.
{"title":"Custom analog low power design: the problem of low voltage and mismatch","authors":"M. Steyaert, V. Peluso, J. Bastos, P. Kinget, W. Sansen","doi":"10.1109/CICC.1997.606631","DOIUrl":"https://doi.org/10.1109/CICC.1997.606631","url":null,"abstract":"The never ending story of technology trends towards smaller transistor dimensions have resulted to date in deep submicron transistors. The consequence is the down scaling of the power supply voltages, to date even lower than 2 V, with almost the same threshold voltages of the CMOS transistors. Those low voltages mean that some widespread techniques such as switched-capacitors cannot be implemented anymore. On the other hand custom integrated circuits require continually higher speeds, more accuracy and less power drain. In the first section, the impact of mismatch or accuracy in analog circuits and the impact on power drain is discussed. Secondly, in section two some fundamental limitations of analog integrated circuit design in the trade-off between speed, accuracy and power drain are analysed. In the third section the problem of very low voltage signal processing in switched-capacitor circuits is studied. Some solutions, such as the switched-opamp technique are presented, and the technique is demonstrated by the design of a very low power, low voltage sigma delta modulator. The design and the measurements of 12 bit sigma delta AD converters running at 1.5 V power supply voltage and consuming less than 100 /spl mu/W in standard CMOS technology are finally discussed.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122670062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606616
G. Roberts
The author presents a discussion on several methods that can be used to improve the testability of mixed-signal integrated circuits. He begins by outlining the role of test, and its impact on product cost and qualify. A brief look is taken at the pending test crises for mixed-signal circuits. Subsequently, the author outlines several common test strategies, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. In the remainder of the paper he describes several analog test buses and circuits for built-in self-test applications.
{"title":"Improving the testability of mixed-signal integrated circuits","authors":"G. Roberts","doi":"10.1109/CICC.1997.606616","DOIUrl":"https://doi.org/10.1109/CICC.1997.606616","url":null,"abstract":"The author presents a discussion on several methods that can be used to improve the testability of mixed-signal integrated circuits. He begins by outlining the role of test, and its impact on product cost and qualify. A brief look is taken at the pending test crises for mixed-signal circuits. Subsequently, the author outlines several common test strategies, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. In the remainder of the paper he describes several analog test buses and circuits for built-in self-test applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123987868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606637
J. Routama, K. Koli, P. Ruhanen, K. Halonen
This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal.
{"title":"A transmitter and receiver interface circuit including an equalizer and PFLL for 150 Mbit/s cable communication","authors":"J. Routama, K. Koli, P. Ruhanen, K. Halonen","doi":"10.1109/CICC.1997.606637","DOIUrl":"https://doi.org/10.1109/CICC.1997.606637","url":null,"abstract":"This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129642164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606640
K. Choi, A. Buchwald
A CMOS modulator for broadband PAM and QPSK data formats is presented. The circuit is based on a poly-phase implementation of a traditional all-digital architecture. A digital-to-analog current-division wave-shaping converter serves as an FIR bandwidth limiting filter. Digital data is applied at the input and an analog waveform is produced at the output, without the need for a standard D/A converter at the back-end, thus reducing power consumption and area. The circuit has been fabricated in a 0.8 um CMOS process (MOSIS HPCMOS26G), occupies an area of 1.2-mm/spl times/1.213-mm, and dissipates 20-mW from a single 5 V supply. The maximum baud rate of the modulator is 10-Mbaud. The 33-tap FIR wave-shaping filter insures out-of-band ripples are suppressed by more than 30-dB. This modulator is applicable to broadband digital communication such as wireless telephony, wireless modems and digital video.
提出了一种适用于宽带PAM和QPSK数据格式的CMOS调制器。该电路基于传统全数字架构的多相实现。数模分流整形转换器作为FIR带宽限制滤波器。在输入端应用数字数据，在输出端产生模拟波形，而不需要在后端使用标准的D/ a转换器，从而降低了功耗和面积。该电路采用0.8 um CMOS工艺(MOSIS HPCMOS26G)制造，占地面积为1.2 mm/spl倍/1.213 mm，单个5 V电源功耗为20 mw。调制器的最大波特率为10mbaud。33分接FIR整形滤波器确保带外波纹被抑制超过30db。该调制器适用于无线电话、无线调制解调器、数字视频等宽带数字通信。
{"title":"A CMOS 10-Mbaud 20-mW PAM/QPSK modulator using a digital-to-analog current-division waveshaping converter","authors":"K. Choi, A. Buchwald","doi":"10.1109/CICC.1997.606640","DOIUrl":"https://doi.org/10.1109/CICC.1997.606640","url":null,"abstract":"A CMOS modulator for broadband PAM and QPSK data formats is presented. The circuit is based on a poly-phase implementation of a traditional all-digital architecture. A digital-to-analog current-division wave-shaping converter serves as an FIR bandwidth limiting filter. Digital data is applied at the input and an analog waveform is produced at the output, without the need for a standard D/A converter at the back-end, thus reducing power consumption and area. The circuit has been fabricated in a 0.8 um CMOS process (MOSIS HPCMOS26G), occupies an area of 1.2-mm/spl times/1.213-mm, and dissipates 20-mW from a single 5 V supply. The maximum baud rate of the modulator is 10-Mbaud. The 33-tap FIR wave-shaping filter insures out-of-band ripples are suppressed by more than 30-dB. This modulator is applicable to broadband digital communication such as wireless telephony, wireless modems and digital video.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131303826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606678
Y. Shin, K. Bult
A low cost 900-MHz RF Low-Noise Amplifier is implemented in a standard 0.9 /spl mu/m digital CMOS process. The design circumvents the use of both expensive external inductors as well as large on-chip inductors, by employing a gyrator circuit to emulate the inductors. This results in a high gain at RF of 20 dB, a tunable resonance frequency and a chip area of only 0.1 mm/sup 2/. At a 940 MHz center frequency, this fully balanced LNA exhibits -23 dB of S11, a 5.3 dB noise figure and an IIP3 of -8.6 dBm. It drains 12.5 mA from a 3.3 V supply.
{"title":"An inductorless 900 MHz RF low-noise amplifier in 0.9 /spl mu/m CMOS","authors":"Y. Shin, K. Bult","doi":"10.1109/CICC.1997.606678","DOIUrl":"https://doi.org/10.1109/CICC.1997.606678","url":null,"abstract":"A low cost 900-MHz RF Low-Noise Amplifier is implemented in a standard 0.9 /spl mu/m digital CMOS process. The design circumvents the use of both expensive external inductors as well as large on-chip inductors, by employing a gyrator circuit to emulate the inductors. This results in a high gain at RF of 20 dB, a tunable resonance frequency and a chip area of only 0.1 mm/sup 2/. At a 940 MHz center frequency, this fully balanced LNA exhibits -23 dB of S11, a 5.3 dB noise figure and an IIP3 of -8.6 dBm. It drains 12.5 mA from a 3.3 V supply.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117024060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606649
Jinsong Zhao, W. Dai, R. Frye, K. Tai
Recently the substrate coupling and substrate parasitics are calling for more and more research efforts. This paper addresses this problem by formulating the multilayer substrate Green function equivalent to purely lossy transmission line circuits. Infinite number of exact images can be tracked by wave-tracing. Moment matching technique is used to approximate the fast decaying part while the slow decaying part is extracted by the wave-tracing. We achieve highly accurate yet closed-form space-domain Green function. Parasitics for our MCM on-wafer inductors due to substrate coupling can be efficiently extracted.
{"title":"Green function via moment matching for rapid and accurate substrate parasitics evaluation","authors":"Jinsong Zhao, W. Dai, R. Frye, K. Tai","doi":"10.1109/CICC.1997.606649","DOIUrl":"https://doi.org/10.1109/CICC.1997.606649","url":null,"abstract":"Recently the substrate coupling and substrate parasitics are calling for more and more research efforts. This paper addresses this problem by formulating the multilayer substrate Green function equivalent to purely lossy transmission line circuits. Infinite number of exact images can be tracked by wave-tracing. Moment matching technique is used to approximate the fast decaying part while the slow decaying part is extracted by the wave-tracing. We achieve highly accurate yet closed-form space-domain Green function. Parasitics for our MCM on-wafer inductors due to substrate coupling can be efficiently extracted.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129344786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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