As today's process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities in combination with the smaller feature sizes requires that we now address defect mechanisms that safely could be more or less ignored in earlier technology nodes. Scan based delay fault testing (AC-scan) fills a large gap in defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in (Rajski, et al.,2003). Our scheme is very diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Stanojevic et al., 2005 and Leininger et al., 2005). Yet, the compactor has comparable performance to other schemes (Rajski et., 2003) when it comes to 'X' tolerance and aliasing
{"title":"Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor","authors":"Sverre Wichlund, F. Berntsen, E. Aas","doi":"10.1109/DFT.2006.53","DOIUrl":"https://doi.org/10.1109/DFT.2006.53","url":null,"abstract":"As today's process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities in combination with the smaller feature sizes requires that we now address defect mechanisms that safely could be more or less ignored in earlier technology nodes. Scan based delay fault testing (AC-scan) fills a large gap in defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in (Rajski, et al.,2003). Our scheme is very diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Stanojevic et al., 2005 and Leininger et al., 2005). Yet, the compactor has comparable performance to other schemes (Rajski et., 2003) when it comes to 'X' tolerance and aliasing","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131347339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS phase frequency detector (PFD) is investigated. When a phase locked loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence the authors consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was 1dBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified
{"title":"Effect of Process Variation on the Performance of Phase Frequency Detector","authors":"Nandakumar P. Venugopal, N. Shastry, S. Upadhyaya","doi":"10.1109/DFT.2006.23","DOIUrl":"https://doi.org/10.1109/DFT.2006.23","url":null,"abstract":"In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS phase frequency detector (PFD) is investigated. When a phase locked loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence the authors consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was 1dBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. E. Salloum, A. Steininger, Peter Tummeltshammer, Werner Harter
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic information is available, and error handling comes down to a reset of both cores. The strategy proposed in this paper allows a more fine-grained error handling. It is based on the following steps: (1) Identification of those registers that are actually relevant for recovering the last known correct core state. (2) Protection of these registers by additional comparators. (3) Use of the trap mechanism for recovering a consistent state of the complete core. (4) (Optional) provision of rollback capability for the relevant registers in order to relax the critical path constraints. In the paper these individual steps was discussed and motivated, and put them into context. In many cases the speed-up that was gained for the recovery was sufficient for using a dual core as a fail-operational instead of a fail-silent component with respect to transient faults. Rather than being restricted to a specific processor design our mechanisms can be employed in a wide variety of dual-core architectures
{"title":"Recovery Mechanisms for Dual Core Architectures","authors":"C. E. Salloum, A. Steininger, Peter Tummeltshammer, Werner Harter","doi":"10.1109/DFT.2006.52","DOIUrl":"https://doi.org/10.1109/DFT.2006.52","url":null,"abstract":"Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic information is available, and error handling comes down to a reset of both cores. The strategy proposed in this paper allows a more fine-grained error handling. It is based on the following steps: (1) Identification of those registers that are actually relevant for recovering the last known correct core state. (2) Protection of these registers by additional comparators. (3) Use of the trap mechanism for recovering a consistent state of the complete core. (4) (Optional) provision of rollback capability for the relevant registers in order to relax the critical path constraints. In the paper these individual steps was discussed and motivated, and put them into context. In many cases the speed-up that was gained for the recovery was sufficient for using a dual core as a fail-operational instead of a fail-silent component with respect to transient faults. Rather than being restricted to a specific processor design our mechanisms can be employed in a wide variety of dual-core architectures","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method for diagnosing analog circuits that is realized by combining the operation-region model and the X-Y zoning method have been proposed. In the method, the authors cloud implement a diagnosis procedure based on a diagnostic method for digital circuits. In this paper, the method by using an adaptive test to obtain a shorter diagnostic sequence length was improved and its characteristics were shown. Moreover, a new data processing method that utilizes the output response of a circuit to obtain better diagnostic performance was proposed. The effectiveness of the proposed methods by applying them to ITC'97 benchmark circuits was demonstrated with hard faults and soft faults. These improved methods can reduce a diagnostic sequence length without degrading the performance of diagnostic resolution and CPU time
{"title":"Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics","authors":"Y. Miura, J. Kato","doi":"10.1109/DFT.2006.30","DOIUrl":"https://doi.org/10.1109/DFT.2006.30","url":null,"abstract":"A method for diagnosing analog circuits that is realized by combining the operation-region model and the X-Y zoning method have been proposed. In the method, the authors cloud implement a diagnosis procedure based on a diagnostic method for digital circuits. In this paper, the method by using an adaptive test to obtain a shorter diagnostic sequence length was improved and its characteristics were shown. Moreover, a new data processing method that utilizes the output response of a circuit to obtain better diagnostic performance was proposed. The effectiveness of the proposed methods by applying them to ITC'97 benchmark circuits was demonstrated with hard faults and soft faults. These improved methods can reduce a diagnostic sequence length without degrading the performance of diagnostic resolution and CPU time","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"410 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122855768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. L. Haye, C. Jung, David Chen, G. Chapman, J. Dudas
A fault tolerant active pixel sensor (FTAPS) has been designed and fabricated to correct for point defects that occur in CMOS image sensors both at manufacturing and over the lifetime of the sensor. For some time it has been known that fabrication of CMOS image sensors in processes less than 0.35mum would generate significant performance changes, yet imagers are being fabricated in 0.18mum technology or smaller. Therefore the characteristics of the FTAPS are presented for pixels fabricated in both a standard 0.18mum and 0.35mum CMOS process and compared for consistency
设计和制造了一种容错有源像素传感器(FTAPS)，以纠正CMOS图像传感器在制造和使用寿命期间出现的点缺陷。一段时间以来，人们已经知道，在小于0.35 μ m的工艺中制造CMOS图像传感器将产生显着的性能变化，但成像仪正在以0.18 μ m或更小的工艺制造。因此，介绍了在标准0.18和0.35 μ m CMOS工艺中制造的像素的FTAPS特性，并比较了其一致性
{"title":"Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies","authors":"M. L. Haye, C. Jung, David Chen, G. Chapman, J. Dudas","doi":"10.1109/DFT.2006.31","DOIUrl":"https://doi.org/10.1109/DFT.2006.31","url":null,"abstract":"A fault tolerant active pixel sensor (FTAPS) has been designed and fabricated to correct for point defects that occur in CMOS image sensors both at manufacturing and over the lifetime of the sensor. For some time it has been known that fabrication of CMOS image sensors in processes less than 0.35mum would generate significant performance changes, yet imagers are being fabricated in 0.18mum technology or smaller. Therefore the characteristics of the FTAPS are presented for pixels fabricated in both a standard 0.18mum and 0.35mum CMOS process and compared for consistency","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124863506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS'89 benchmarks, the method can improve the average ranks of injected defects in the suspect list from 9.14 to 5.97 as injected delay size is 1% of longest paths
{"title":"Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method","authors":"Ying-Yen Chen, J. Liou","doi":"10.1109/DFT.2006.27","DOIUrl":"https://doi.org/10.1109/DFT.2006.27","url":null,"abstract":"In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS'89 benchmarks, the method can improve the average ranks of injected defects in the suspect list from 9.14 to 5.97 as injected delay size is 1% of longest paths","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121737519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Valeriu Beiu, W. Ibrahim, Y. A. Alkhawwar, M. Sulieman
This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems
{"title":"Gate Failures Effectively Shape Multiplexing","authors":"Valeriu Beiu, W. Ibrahim, Y. A. Alkhawwar, M. Sulieman","doi":"10.1109/DFT.2006.33","DOIUrl":"https://doi.org/10.1109/DFT.2006.33","url":null,"abstract":"This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124264628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the authors focus on modeling the data dependent jitter (DDJ) in high-speed interconnect. To investigate the data dependent jitter, the analysis is performed with Fourier series based on the interconnect RLC model. By calculating the pattern dependent delay deviation, the data dependent jitter is characterized. To validate the modeling accuracy, the analysis results have been compared against the Cadence simulations
{"title":"Data Dependent Jitter Characterization Based on Fourier Analysis","authors":"Di Mu, T. Xia, Hao Zheng","doi":"10.1109/DFT.2006.19","DOIUrl":"https://doi.org/10.1109/DFT.2006.19","url":null,"abstract":"In this paper, the authors focus on modeling the data dependent jitter (DDJ) in high-speed interconnect. To investigate the data dependent jitter, the analysis is performed with Fourier series based on the interconnect RLC model. By calculating the pattern dependent delay deviation, the data dependent jitter is characterized. To validate the modeling accuracy, the analysis results have been compared against the Cadence simulations","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126703825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Datta, J. Abraham, A. U. Diril, A. Chatterjee, K. Nowka
We present adaptive design techniques that compensate for manufacturing induced process variations in deep sub-micron (DSM) integrated circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations
{"title":"Adaptive Design for Performance-Optimized Robustness","authors":"R. Datta, J. Abraham, A. U. Diril, A. Chatterjee, K. Nowka","doi":"10.1109/DFT.2006.12","DOIUrl":"https://doi.org/10.1109/DFT.2006.12","url":null,"abstract":"We present adaptive design techniques that compensate for manufacturing induced process variations in deep sub-micron (DSM) integrated circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1989 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125494619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the NP-complete problem of reconfiguring two-dimensional degradable processor arrays under the row and column rerouting constraint. One promising approach to this problem is to treat the reconfiguration problem as a combinatorial optimization problem of finding the set of rerouting rules for all rows/columns and employ a genetic algorithm (GA) to obtain an optimal solution (Fukushi et al., 2005 ). However, major drawback of this method is poor utilization of processing elements (PEs) in the reconfiguration process. In this paper, the previous method (Fukushi et al., 2005) for efficient reconfiguration was improved. The key idea is to treat the reconfiguration problem as an optimization problem of determining routing directions for all faulty PEs. A new rerouting scheme is also proposed to reroute logical rows/columns efficiently. Experimental study shows that the proposed method produces good results in terms of the percentage of harvest and degradation
研究了在行、列重路由约束下二维可降解处理器阵列重构的np完全问题。解决这一问题的一种有希望的方法是将重构问题视为寻找所有行/列的重路由规则集的组合优化问题，并使用遗传算法(GA)来获得最优解(Fukushi et al.， 2005)。然而，该方法的主要缺点是在重构过程中加工元素(pe)的利用率较差。本文对之前的方法(Fukushi et al.， 2005)进行了改进，实现了高效重构。关键思想是将重构问题视为确定所有故障pe路由方向的优化问题。提出了一种新的重路由方案，可以有效地对逻辑行/列进行重路由。实验研究表明，该方法在采收率和降解率方面均取得了较好的效果
{"title":"An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm","authors":"Y. Fukushima, Masaru Fukushi, S. Horiguchi","doi":"10.1109/DFT.2006.15","DOIUrl":"https://doi.org/10.1109/DFT.2006.15","url":null,"abstract":"This paper addresses the NP-complete problem of reconfiguring two-dimensional degradable processor arrays under the row and column rerouting constraint. One promising approach to this problem is to treat the reconfiguration problem as a combinatorial optimization problem of finding the set of rerouting rules for all rows/columns and employ a genetic algorithm (GA) to obtain an optimal solution (Fukushi et al., 2005 ). However, major drawback of this method is poor utilization of processing elements (PEs) in the reconfiguration process. In this paper, the previous method (Fukushi et al., 2005) for efficient reconfiguration was improved. The key idea is to treat the reconfiguration problem as an optimization problem of determining routing directions for all faulty PEs. A new rerouting scheme is also proposed to reroute logical rows/columns efficiently. Experimental study shows that the proposed method produces good results in terms of the percentage of harvest and degradation","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132930882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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