I. Polian, B. Becker, M. Nakasato, S. Ohtake, H. Fujiwara
Image processing systems are increasingly used in safety-critical applications, and their hardening against soft errors becomes an issue. The authors propose a methodology to identify soft errors as uncritical based on their impact on the system's functionality. The authors call a soft error uncritical if its impact is provably limited to image perturbations during a very short period of time (number of cycles) and the system is guaranteed to recover thereafter. Uncritical errors do not require hardening as their effects are unperceivable for the human user of the system. The authors focus on soft errors in the motion estimation subsystem of MPEG-2 and introduce different definitions of uncritical soft errors in that subsystem. A method is proposed to automatically determine uncritical errors and provide experimental results for various parameters. The concept can be adapted to further systems and enhance existing methods
{"title":"Low-Cost Hardening of Image Processing Applications Against Soft Errors","authors":"I. Polian, B. Becker, M. Nakasato, S. Ohtake, H. Fujiwara","doi":"10.1109/DFT.2006.40","DOIUrl":"https://doi.org/10.1109/DFT.2006.40","url":null,"abstract":"Image processing systems are increasingly used in safety-critical applications, and their hardening against soft errors becomes an issue. The authors propose a methodology to identify soft errors as uncritical based on their impact on the system's functionality. The authors call a soft error uncritical if its impact is provably limited to image perturbations during a very short period of time (number of cycles) and the system is guaranteed to recover thereafter. Uncritical errors do not require hardening as their effects are unperceivable for the human user of the system. The authors focus on soft errors in the motion estimation subsystem of MPEG-2 and introduce different definitions of uncritical soft errors in that subsystem. A method is proposed to automatically determine uncritical errors and provide experimental results for various parameters. The concept can be adapted to further systems and enhance existing methods","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"85 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126085626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increases. Lasers fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, the authors present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio
{"title":"Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost","authors":"A. Garg, P. Dubey","doi":"10.1109/DFT.2006.32","DOIUrl":"https://doi.org/10.1109/DFT.2006.32","url":null,"abstract":"Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increases. Lasers fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, the authors present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128082551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the fault injection analysis campaign
{"title":"Combined software and hardware techniques for the design of reliable IP processors","authors":"M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto","doi":"10.1109/DFT.2006.18","DOIUrl":"https://doi.org/10.1109/DFT.2006.18","url":null,"abstract":"In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the fault injection analysis campaign","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123673847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Register file is often implemented using static random access memory (SRAM) due to its fast operation. Furthermore, SRAM-based multi-port register file can perform multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust register file for microprocessors and investigating their failure characteristics become critical. In this work, the authors present a register file with a structure of 3-port SRAM cell and a differential current-mode sense amplifier for read circuitry. The authors then study the fault models for resistive defect within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defect at 4-6times for dual-port read and 5.8times for 3-port read compared to voltage-mode sensing with 0.18mum manufacturing process technology
{"title":"A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells","authors":"Lushan Liu, R. Sridhar, S. Upadhyaya","doi":"10.1109/DFT.2006.5","DOIUrl":"https://doi.org/10.1109/DFT.2006.5","url":null,"abstract":"Register file is often implemented using static random access memory (SRAM) due to its fast operation. Furthermore, SRAM-based multi-port register file can perform multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust register file for microprocessors and investigating their failure characteristics become critical. In this work, the authors present a register file with a structure of 3-port SRAM cell and a differential current-mode sense amplifier for read circuitry. The authors then study the fault models for resistive defect within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defect at 4-6times for dual-port read and 5.8times for 3-port read compared to voltage-mode sensing with 0.18mum manufacturing process technology","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125054361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they are able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS'89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design
{"title":"An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint","authors":"Geewhun Seok, Il-soo Lee, T. Ambler, B. Womack","doi":"10.1109/DFT.2006.14","DOIUrl":"https://doi.org/10.1109/DFT.2006.14","url":null,"abstract":"A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they are able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS'89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122191792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gang Zeng, Youhua Shi, T. Takabatake, M. Yanagisawa, Hideo Ito
A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach
{"title":"Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters","authors":"Gang Zeng, Youhua Shi, T. Takabatake, M. Yanagisawa, Hideo Ito","doi":"10.1109/DFT.2006.41","DOIUrl":"https://doi.org/10.1109/DFT.2006.41","url":null,"abstract":"A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116493466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Zhang, W. Necoechea, Peter Reiter, Yong-Bin Kim, F. Lombardi
This paper presents two load board designs for hierarchical calibration of largely populated ATE. Compound dot technique and phase detector are used on both boards to provide automatic and low cost calibration of ATE with or without a single reference clock. Two different relay tree structures are implemented on the two boards with advanced board design techniques for group offset calibration. Various error sources have been identified and analyzed on both boards based on SPICE simulations and real measurements. TDR measurement compares the two approaches and shows that the two load boards give a maximum of 37ps group timing skew and can be calibrated out by the calibration software
{"title":"Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations","authors":"F. Zhang, W. Necoechea, Peter Reiter, Yong-Bin Kim, F. Lombardi","doi":"10.1109/DFT.2006.38","DOIUrl":"https://doi.org/10.1109/DFT.2006.38","url":null,"abstract":"This paper presents two load board designs for hierarchical calibration of largely populated ATE. Compound dot technique and phase detector are used on both boards to provide automatic and low cost calibration of ATE with or without a single reference clock. Two different relay tree structures are implemented on the two boards with advanced board design techniques for group offset calibration. Various error sources have been identified and analyzed on both boards based on SPICE simulations and real measurements. TDR measurement compares the two approaches and shows that the two load boards give a maximum of 37ps group timing skew and can be calibrated out by the calibration software","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132795126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses a defect tolerant and energy economized computing array for the DSP plane of a 3D heterogeneous system on a chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application example relating to defect tolerant visible sensors is described. We also discuss energy economization through the use of sleep transistor networks and multi-hop communication. The ultimate goal is to build such 3D heterogeneous sensor nodes with integrated processing and communications capability, and with provision for defect tolerance on the sensor plane as well as the multiple processing planes
{"title":"Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC","authors":"V. Jain, G. Chapman","doi":"10.1109/DFT.2006.20","DOIUrl":"https://doi.org/10.1109/DFT.2006.20","url":null,"abstract":"This paper discusses a defect tolerant and energy economized computing array for the DSP plane of a 3D heterogeneous system on a chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application example relating to defect tolerant visible sensors is described. We also discuss energy economization through the use of sleep transistor networks and multi-hop communication. The ultimate goal is to build such 3D heterogeneous sensor nodes with integrated processing and communications capability, and with provision for defect tolerance on the sensor plane as well as the multiple processing planes","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129056998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead
{"title":"Low Power SoC Memory BIST","authors":"Yuejian Wu, A. Ivanov","doi":"10.1109/DFT.2006.39","DOIUrl":"https://doi.org/10.1109/DFT.2006.39","url":null,"abstract":"With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116999388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Á. Michels, Lorenzo Petroli, C. Lisbôa, F. Kastensmidt, L. Carro
This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. We propose a new type of voter circuit that uses some knowledge from the analog design arena, and show that these circuits can be used to implement fully fault tolerant modules, in a more efficient way than using triple modular redundancy (TMR). Second, based on already known techniques used to implement any combinational function with the use of majority gates, it is proven that a semi-analog voter can be used to implement fault tolerant majority gates that perform the same functions as the regular combinations of AND, OR and INVERTER gates. Finally, the implementation and test of an adder circuit, using both conventional TMR and the proposed solution, is described and analyzed, in order to confirm that the proposed solution is fault tolerant and also compares favorably to some classic designs that are not 100 percent fault tolerant
{"title":"SET Fault Tolerant Combinational Circuits Based on Majority Logic","authors":"Á. Michels, Lorenzo Petroli, C. Lisbôa, F. Kastensmidt, L. Carro","doi":"10.1109/DFT.2006.59","DOIUrl":"https://doi.org/10.1109/DFT.2006.59","url":null,"abstract":"This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. We propose a new type of voter circuit that uses some knowledge from the analog design arena, and show that these circuits can be used to implement fully fault tolerant modules, in a more efficient way than using triple modular redundancy (TMR). Second, based on already known techniques used to implement any combinational function with the use of majority gates, it is proven that a semi-analog voter can be used to implement fault tolerant majority gates that perform the same functions as the regular combinations of AND, OR and INVERTER gates. Finally, the implementation and test of an adder circuit, using both conventional TMR and the proposed solution, is described and analyzed, in order to confirm that the proposed solution is fault tolerant and also compares favorably to some classic designs that are not 100 percent fault tolerant","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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