Hiroshi Takahashi, Shuhei Kadoyama, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Aikyo, Yasuo Sato
With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis based on the compressed responses from BIST was called the post-BIST fault diagnosis (Takahashi et al., 2005, Takamatsu, 2005). The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 (Sato et al., 2005) benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, the feasibility of diagnosing the large circuits within the practical CPU times can be confirmed. The feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis was proven
随着大规模集成电路的日益复杂，内建自测试(BIST)技术在生产测试中是一个很有前途的技术之一。从我们在制造测试期间的观察来看，在良率上升过程中，失效芯片中经常存在多个卡滞故障。为此，作者提出了一种基于BIST压缩响应的多卡滞故障诊断方法。基于BIST压缩响应的故障诊断称为后BIST故障诊断(Takahashi et al.， 2005, Takamatsu, 2005)。讨论了对成功率的影响以及对大型电路进行诊断的可行性。从ISCAS和STARC03 (Sato et al.， 2005)基准电路的实验结果来看，很明显，所提出的诊断方法获得了约98%的高成功率。通过对100K门的大型电路的实验结果，验证了在实际CPU时间内对大型电路进行诊断的可行性。验证了后bist故障诊断中多卡滞故障诊断的可行性
{"title":"Effective Post-BIST Fault Diagnosis for Multiple Faults","authors":"Hiroshi Takahashi, Shuhei Kadoyama, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Aikyo, Yasuo Sato","doi":"10.1109/DFT.2006.24","DOIUrl":"https://doi.org/10.1109/DFT.2006.24","url":null,"abstract":"With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis based on the compressed responses from BIST was called the post-BIST fault diagnosis (Takahashi et al., 2005, Takamatsu, 2005). The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 (Sato et al., 2005) benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, the feasibility of diagnosing the large circuits within the practical CPU times can be confirmed. The feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis was proven","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127685108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Systems-on-chip integrate increasingly larger numbers of pre-designed cores interconnected through complex communication fabrics. For nanometer-scale VLSI processes (45 nm and below), it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing defects. In order to improve the yield and reliability of multi-core SoCs, their interconnect infrastructures must be designed such that fabrication and life-time faults can be tolerated. In this work we present a self-repair method for the interconnect fabrics of integrated multi-core systems. Our method is based on the use of redundant links and crosspoints, and improves both post-manufacturing yield and life-time reliability of on-chip communication fabrics. Our method can provide a significant interconnect yield improvement (up to 72% in our experiments), and allows fine-tuning of yield versus redundant components
{"title":"NoC Interconnect Yield Improvement Using Crosspoint Redundancy","authors":"C. Grecu, A. Ivanov, R. Saleh, P. Pande","doi":"10.1109/DFT.2006.46","DOIUrl":"https://doi.org/10.1109/DFT.2006.46","url":null,"abstract":"Systems-on-chip integrate increasingly larger numbers of pre-designed cores interconnected through complex communication fabrics. For nanometer-scale VLSI processes (45 nm and below), it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing defects. In order to improve the yield and reliability of multi-core SoCs, their interconnect infrastructures must be designed such that fabrication and life-time faults can be tolerated. In this work we present a self-repair method for the interconnect fabrics of integrated multi-core systems. Our method is based on the use of redundant links and crosspoints, and improves both post-manufacturing yield and life-time reliability of on-chip communication fabrics. Our method can provide a significant interconnect yield improvement (up to 72% in our experiments), and allows fine-tuning of yield versus redundant components","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and pass transistors. The paper also presents construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, experimental results show that the proposed method has higher soft error tolerant capability than the existing methods. For driving voltage VDD=3.3V, the proposed method is capable of masking transient pulses of magnitude 4.0V or less
{"title":"Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit","authors":"Yoichi Sasaki, K. Namba, Hideo Ito","doi":"10.1109/DFT.2006.60","DOIUrl":"https://doi.org/10.1109/DFT.2006.60","url":null,"abstract":"In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and pass transistors. The paper also presents construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, experimental results show that the proposed method has higher soft error tolerant capability than the existing methods. For driving voltage VDD=3.3V, the proposed method is capable of masking transient pulses of magnitude 4.0V or less","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ferringer, Gottfried Fuchs, A. Steininger, G. Kempf
In this paper the authors introduce a novel approach for the on-chip generation of a fault-tolerant clock. The authors motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. The authors present the underlying algorithm, point out the difficulties for the hardware implementation and provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method the authors also present some measurement results from a prototype implementation
{"title":"VLSI Implementation of a Fault-Tolerant Distributed Clock Generation","authors":"M. Ferringer, Gottfried Fuchs, A. Steininger, G. Kempf","doi":"10.1109/DFT.2006.67","DOIUrl":"https://doi.org/10.1109/DFT.2006.67","url":null,"abstract":"In this paper the authors introduce a novel approach for the on-chip generation of a fault-tolerant clock. The authors motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. The authors present the underlying algorithm, point out the difficulties for the hardware implementation and provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method the authors also present some measurement results from a prototype implementation","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128031867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption
{"title":"Testing Reversible 1D Arrays for Molecular QCA","authors":"Xiaojun Ma, Jing Huang, C. Metra, F. Lombardi","doi":"10.1109/DFT.2006.63","DOIUrl":"https://doi.org/10.1109/DFT.2006.63","url":null,"abstract":"Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131997716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor's architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults
{"title":"Online hardening of programs against SEUs and SETs","authors":"C. Lisbôa, L. Carro, M. Reorda, M. Violante","doi":"10.1109/DFT.2006.49","DOIUrl":"https://doi.org/10.1109/DFT.2006.49","url":null,"abstract":"Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor's architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MEMS (micro electromechanical system) yield and reliability have been a very critical issue. In our previous paper, the authors have proposed a self-repairable MEMS comb accelerometer device, and the yield analysis has demonstrated effective yield increase due to the BISR (built-in self-repair) design. In this paper, the authors developed a MEMS reliability model for quantitative assessment of the MEMS reliability analysis. Based on this model, analysis of the reliability of both non-BISR and BISR MEMS comb accelerometers under z-axis shocking environment. Simulation results demonstrate very effective reliability enhancement due to the BISR design. The reliability model can also be applied to other MEMS devices under various failure mechanisms in a similar way
{"title":"Reliability Analysis of Self-Repairable MEMS Accelerometer","authors":"X. Xiong, Yu-Liang Wu, W. Jone","doi":"10.1109/DFT.2006.54","DOIUrl":"https://doi.org/10.1109/DFT.2006.54","url":null,"abstract":"MEMS (micro electromechanical system) yield and reliability have been a very critical issue. In our previous paper, the authors have proposed a self-repairable MEMS comb accelerometer device, and the yield analysis has demonstrated effective yield increase due to the BISR (built-in self-repair) design. In this paper, the authors developed a MEMS reliability model for quantitative assessment of the MEMS reliability analysis. Based on this model, analysis of the reliability of both non-BISR and BISR MEMS comb accelerometers under z-axis shocking environment. Simulation results demonstrate very effective reliability enhancement due to the BISR design. The reliability model can also be applied to other MEMS devices under various failure mechanisms in a similar way","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126072338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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