Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268858
B. Nakhal, R. Querrec
In this work, we propose a model for building Virtual Learning Environment (VLE) where intelligent virtual agents play the role of tutors and are expected to help a human user to follow a procedural scenario with predefined learning outcomes. Our model provides the agents with a cognitive architecture to make sound reasoning on its knowledge base. The agent is materialized in front of the user as an Embodied Conversational Agent (ECA) that communicates and interacts with her/him in a credible human-like manner. Our implemented model is then tested in a concrete pedagogical scenario for learning blood analysis procedures in a biomedical laboratory.
{"title":"Cognitive embodied conversational agents in virtual learning environment","authors":"B. Nakhal, R. Querrec","doi":"10.1109/ICM.2017.8268858","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268858","url":null,"abstract":"In this work, we propose a model for building Virtual Learning Environment (VLE) where intelligent virtual agents play the role of tutors and are expected to help a human user to follow a procedural scenario with predefined learning outcomes. Our model provides the agents with a cognitive architecture to make sound reasoning on its knowledge base. The agent is materialized in front of the user as an Embodied Conversational Agent (ECA) that communicates and interacts with her/him in a credible human-like manner. Our implemented model is then tested in a concrete pedagogical scenario for learning blood analysis procedures in a biomedical laboratory.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124804989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268838
Sajjad Sabbaghi Saber, M. Ehsanian
A linear referenceless CDR with adaptive loop bandwidth suitable for OC-192 SONET transceiver is presented. The system employs a linear Hogge PD with enhanced capture range technique for a better jitter performance. Improved jitter transfer is also obtained utilizing an adjustable loop bandwidth. The proposed CDR Operates at 9–11 Gb/s with 3.5–7 MHz adjustable loop bandwidth and enhances jitter transfer by 3 dB for a 27-1 PRBS input. Jitter parameters of CDR system are compatible with OC-192 jitter requirements.
{"title":"A linear high capture range CDR with adaptive loop bandwidth for SONET application","authors":"Sajjad Sabbaghi Saber, M. Ehsanian","doi":"10.1109/ICM.2017.8268838","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268838","url":null,"abstract":"A linear referenceless CDR with adaptive loop bandwidth suitable for OC-192 SONET transceiver is presented. The system employs a linear Hogge PD with enhanced capture range technique for a better jitter performance. Improved jitter transfer is also obtained utilizing an adjustable loop bandwidth. The proposed CDR Operates at 9–11 Gb/s with 3.5–7 MHz adjustable loop bandwidth and enhances jitter transfer by 3 dB for a 27-1 PRBS input. Jitter parameters of CDR system are compatible with OC-192 jitter requirements.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123950435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268870
J. Ayoub, Rabih Rammal, A. Assi, I. Assi
Current solar panels can be improved using several techniques that boost the efficiency and cell performance. Looking in the latest studies currently on-going in the laboratories, two main fields were mostly taking a considerable success: PERC technology and passive thermal management. PERC technology involves the addition of a dielectric passivation layer to the already existing layers in the p-type crystalline wafers. This helps trap more sunlight and generate more electricity, thus improving the crystalline silicon panel. In addition, proper thermal management of photovoltaics leads to better heat dissipation, which improves the conversion of sunlight to electricity and maintains a stable panel performance in the long run.
{"title":"Two techniques used to improve the efficiency of existing PV panels: Thermal management & PERC technology","authors":"J. Ayoub, Rabih Rammal, A. Assi, I. Assi","doi":"10.1109/ICM.2017.8268870","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268870","url":null,"abstract":"Current solar panels can be improved using several techniques that boost the efficiency and cell performance. Looking in the latest studies currently on-going in the laboratories, two main fields were mostly taking a considerable success: PERC technology and passive thermal management. PERC technology involves the addition of a dielectric passivation layer to the already existing layers in the p-type crystalline wafers. This helps trap more sunlight and generate more electricity, thus improving the crystalline silicon panel. In addition, proper thermal management of photovoltaics leads to better heat dissipation, which improves the conversion of sunlight to electricity and maintains a stable panel performance in the long run.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126969761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268883
Khaled A. Helal, Ahmed Yasser Abo Elmkarem, A. Refaat, Taha Shawky Kamel, Kareem Ayman Mohamed, Mohamed Mahmoud Kamal, Mohamed Mostafa Abdelrahman, H. Mostafa, Y. Ismail
Neural interfaces are systems operating at the intersection of the nervous system and an internal or external device. Neuro-stimulator is one of the most important neural interfaces used to help those who experience epileptic seizures. To use this stimulator efficiently, seizure should be detected at the right time. Seizure detection is basically founded on digital signal processing by monitoring certain features of the intracranial electroencephalogram. Many of the previous researches are directed to study the detection efficacies using different systems, however, a few of them study the feasibility of implementing these systems over a computationally limited power implantable platforms. In this paper, five time-domain features and three wavelet-domain features are investigated. Following that, a high accuracy seizure detection algorithm is presented with efficient power consumption which makes it suitable for implantable neural systems. The experiment results show that the presented method achieves a sensitivity, specificity, and accuracy of 92.64%, 99.29%, and 99.16% respectively for long-term iEEG seizure detection. The area and power results are obtained from implementing the algorithms on Xilinx Spartan-6 XC6SLX45T FPGA.
{"title":"Low-power high-accuracy seizure detection algorithms for neural implantable platforms","authors":"Khaled A. Helal, Ahmed Yasser Abo Elmkarem, A. Refaat, Taha Shawky Kamel, Kareem Ayman Mohamed, Mohamed Mahmoud Kamal, Mohamed Mostafa Abdelrahman, H. Mostafa, Y. Ismail","doi":"10.1109/ICM.2017.8268883","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268883","url":null,"abstract":"Neural interfaces are systems operating at the intersection of the nervous system and an internal or external device. Neuro-stimulator is one of the most important neural interfaces used to help those who experience epileptic seizures. To use this stimulator efficiently, seizure should be detected at the right time. Seizure detection is basically founded on digital signal processing by monitoring certain features of the intracranial electroencephalogram. Many of the previous researches are directed to study the detection efficacies using different systems, however, a few of them study the feasibility of implementing these systems over a computationally limited power implantable platforms. In this paper, five time-domain features and three wavelet-domain features are investigated. Following that, a high accuracy seizure detection algorithm is presented with efficient power consumption which makes it suitable for implantable neural systems. The experiment results show that the presented method achieves a sensitivity, specificity, and accuracy of 92.64%, 99.29%, and 99.16% respectively for long-term iEEG seizure detection. The area and power results are obtained from implementing the algorithms on Xilinx Spartan-6 XC6SLX45T FPGA.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268849
R. Abreu, T. Pimenta, D. Spadoti
The efficiency of tunable wireless power transfer between two antennas with a low-cost embedded circuit is investigated. The system operates in the strong coupling regime and, therefore, within the near field region. The efficiency was numerically calculated by varying the distance between the transmitter/receiver system, and analyzing by the Maximum Power Point Tracking (MPPT) algorithm. The maximum increase of efficiency achieved was 27.39% at a distance of 30 cm and 154.16% at a distance of 1 meter.
{"title":"Self-tuning capacitance for impedance matching in wireless power transfer devices","authors":"R. Abreu, T. Pimenta, D. Spadoti","doi":"10.1109/ICM.2017.8268849","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268849","url":null,"abstract":"The efficiency of tunable wireless power transfer between two antennas with a low-cost embedded circuit is investigated. The system operates in the strong coupling regime and, therefore, within the near field region. The efficiency was numerically calculated by varying the distance between the transmitter/receiver system, and analyzing by the Maximum Power Point Tracking (MPPT) algorithm. The maximum increase of efficiency achieved was 27.39% at a distance of 30 cm and 154.16% at a distance of 1 meter.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124141635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268833
Andrew Boutros, Salma Hesham, Barbara Georgey, M. A. E. Ghany
In this paper, we propose a new chaos-based image encryption algorithm that combines Arnold's Cat and cascaded discrete Duffing equations maps for the confusion and diffusion stages of an image cryptosystem. The algorithm performs only one Arnold's Cat shuffle on the encryption side using two different keys instead of several shuffles used in conventional implementations. The security analysis of the proposed algorithm proves robustness when compared to state-of-the-art chaos-based encryption algorithms with less runtime and simpler operations. A complete accelerated hardware design of the proposed algorithm is implemented on Xilinx Zynq XC7Z020 FPGA board. For a 512 × 512 image, the hardware design achieves a maximum frequency of 135 MHz encrypting 256 fps which meets the real-time requirements of IoT applications.
{"title":"Hardware acceleration of novel chaos-based image encryption for IoT applications","authors":"Andrew Boutros, Salma Hesham, Barbara Georgey, M. A. E. Ghany","doi":"10.1109/ICM.2017.8268833","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268833","url":null,"abstract":"In this paper, we propose a new chaos-based image encryption algorithm that combines Arnold's Cat and cascaded discrete Duffing equations maps for the confusion and diffusion stages of an image cryptosystem. The algorithm performs only one Arnold's Cat shuffle on the encryption side using two different keys instead of several shuffles used in conventional implementations. The security analysis of the proposed algorithm proves robustness when compared to state-of-the-art chaos-based encryption algorithms with less runtime and simpler operations. A complete accelerated hardware design of the proposed algorithm is implemented on Xilinx Zynq XC7Z020 FPGA board. For a 512 × 512 image, the hardware design achieves a maximum frequency of 135 MHz encrypting 256 fps which meets the real-time requirements of IoT applications.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268846
Ahmed M. Saied, M. M. Abutaleb, I. I. Ibrahim, H. Ragai
In this paper, a design methodology to enhance the performance of low-noise amplifier (LNA) is presented. The methodology proposes a new operating parameter (OP) by using the drain-source saturation voltage (VDSsat) as an additional design parameter. This OP reaches a maximum value close to the threshold voltage (Vt) in moderate inversion region. A 3–5 GHz ultra-wideband (UWB) common gate design is used as an example to show the effectiveness of the proposed methodology. Simulation results show that the proposed methodology can reduce power consumption by 22% and increase the figure of merit (FoM) by 30% compared to traditional methodology, without having a significant effect on either noise figure (NF) or linearity characteristics.
{"title":"Ultra-low-power design methodology for UWB low-noise amplifiers","authors":"Ahmed M. Saied, M. M. Abutaleb, I. I. Ibrahim, H. Ragai","doi":"10.1109/ICM.2017.8268846","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268846","url":null,"abstract":"In this paper, a design methodology to enhance the performance of low-noise amplifier (LNA) is presented. The methodology proposes a new operating parameter (OP) by using the drain-source saturation voltage (VDSsat) as an additional design parameter. This OP reaches a maximum value close to the threshold voltage (Vt) in moderate inversion region. A 3–5 GHz ultra-wideband (UWB) common gate design is used as an example to show the effectiveness of the proposed methodology. Simulation results show that the proposed methodology can reduce power consumption by 22% and increase the figure of merit (FoM) by 30% compared to traditional methodology, without having a significant effect on either noise figure (NF) or linearity characteristics.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124430418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268854
Emad Badry, A. Shalaby, M. Sayed
In this paper, a new interpolation-free algorithm for fractional pixel motion estimation (FME) is proposed based on the statistical analysis of the matching error surface around the integer-pixel motion vector location. Performance analysis shows that 96% saving can be achieved for FME computation cost at the expense of only 2.2% BD-rate increment. The proposed algorithm was prototyped using Verilog and synthesized targeting 65nm CMOS technology. The design achieves a maximum frequency of 602 MHz and a high throughput where it can process 71 fps for FQHD (3840×2160) videos. It has only 26.6 kgates and power consumption of 18.6 mW.
{"title":"A hardware friendly fractional-pixel motion estimation algorithm based on adaptive weighted model","authors":"Emad Badry, A. Shalaby, M. Sayed","doi":"10.1109/ICM.2017.8268854","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268854","url":null,"abstract":"In this paper, a new interpolation-free algorithm for fractional pixel motion estimation (FME) is proposed based on the statistical analysis of the matching error surface around the integer-pixel motion vector location. Performance analysis shows that 96% saving can be achieved for FME computation cost at the expense of only 2.2% BD-rate increment. The proposed algorithm was prototyped using Verilog and synthesized targeting 65nm CMOS technology. The design achieves a maximum frequency of 602 MHz and a high throughput where it can process 71 fps for FQHD (3840×2160) videos. It has only 26.6 kgates and power consumption of 18.6 mW.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131367873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268825
Md Anam Mahmud, A. Abdelgawad, K. Yelamarthi, Y. Ismail
With the advancement of modern technology, structures like buildings, bridges, etc. are getting structurally complicated, and safety has become an issue. Structural Health Monitoring (SHM) with Internet of Things (IoT) can help improving security and safety. However, efficient signal processing for IoT is a challenge. In this paper, a signal processing based SHM is proposed where a simple Butterworth filter was used to remove noises. Cross-Correlation was used for damage detection. If there was any damage found, using a mathematical model, damage size and location were determined. After analyzing the experimental data, error found in damage localization is 2.9% and error in determining damage size is 3.344%. Since the whole algorithm does not associate with complex mathematical calculations, this system can be used for low-cost distributed system for SHM.
{"title":"Signal processing techniques for IoT-based structural health monitoring","authors":"Md Anam Mahmud, A. Abdelgawad, K. Yelamarthi, Y. Ismail","doi":"10.1109/ICM.2017.8268825","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268825","url":null,"abstract":"With the advancement of modern technology, structures like buildings, bridges, etc. are getting structurally complicated, and safety has become an issue. Structural Health Monitoring (SHM) with Internet of Things (IoT) can help improving security and safety. However, efficient signal processing for IoT is a challenge. In this paper, a signal processing based SHM is proposed where a simple Butterworth filter was used to remove noises. Cross-Correlation was used for damage detection. If there was any damage found, using a mathematical model, damage size and location were determined. After analyzing the experimental data, error found in damage localization is 2.9% and error in determining damage size is 3.344%. Since the whole algorithm does not associate with complex mathematical calculations, this system can be used for low-cost distributed system for SHM.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268853
O. Elgabry, F. Hussien, A. Mohieldin
In this paper an automated CAD tool for rapid technology characterization is presented. The proposed methodology fills the gap found in old, as well as, new IC desgin methdologies technology. The tool allows the user doing a rapid characterization for different devices models available in a technology. The tool is based on a pre-defined suite of test-benches in addition to SKILL code and OCEAN script to allow seamless integration of the tool in the design environment. Finally, a design example is presented using 130 nm CMOS technology using the tool; results are shown for MOSFET devices characterization.
{"title":"An automated CAD tool for rapid technology characterization","authors":"O. Elgabry, F. Hussien, A. Mohieldin","doi":"10.1109/ICM.2017.8268853","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268853","url":null,"abstract":"In this paper an automated CAD tool for rapid technology characterization is presented. The proposed methodology fills the gap found in old, as well as, new IC desgin methdologies technology. The tool allows the user doing a rapid characterization for different devices models available in a technology. The tool is based on a pre-defined suite of test-benches in addition to SKILL code and OCEAN script to allow seamless integration of the tool in the design environment. Finally, a design example is presented using 130 nm CMOS technology using the tool; results are shown for MOSFET devices characterization.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134472644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：