Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268835
Ali Hamieh, Jihad Hamieh, A. Hamie, A. Ghorayeb, A. Zaiour, B. Assaf
In this paper, the Optical and Semiconductor properties of epitaxial thin films of Fe2−xTixO3-δ, deposited on SrTiO3 (001) by pulsed laser deposition (PLD) are studied. We use Perlin Elmer 9500 spechtrophotometer in order to measure the optical transmission and reflection. The prepared films using oxygen pressure PO2 above 3 ∗ 10−7 Torr, presents a R(3) symmetry structure. The prepared samples present a deficiency δ = 0.35. The optical properties show a very important dependence with the oxygen cation stoichiometry. These last properties, which are dominated by the oxygen deficiency obtained during the growth of thin films, show a semiconductor behavior where the conductivity increase more with S than by the atomic ordering of titanium.
{"title":"Effect of oxygen pressure on the semiconductor properties of FTO thin films","authors":"Ali Hamieh, Jihad Hamieh, A. Hamie, A. Ghorayeb, A. Zaiour, B. Assaf","doi":"10.1109/ICM.2017.8268835","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268835","url":null,"abstract":"In this paper, the Optical and Semiconductor properties of epitaxial thin films of Fe<inf>2−x</inf>Ti<inf>x</inf>O<inf>3-δ</inf>, deposited on SrTiO<inf>3</inf> (001) by pulsed laser deposition (PLD) are studied. We use Perlin Elmer 9500 spechtrophotometer in order to measure the optical transmission and reflection. The prepared films using oxygen pressure PO2 above 3 ∗ 10<sup>−7</sup> Torr, presents a R(3) symmetry structure. The prepared samples present a deficiency δ = 0.35. The optical properties show a very important dependence with the oxygen cation stoichiometry. These last properties, which are dominated by the oxygen deficiency obtained during the growth of thin films, show a semiconductor behavior where the conductivity increase more with S than by the atomic ordering of titanium.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"173 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268894
K. Bousmar, F. Monteiro, Z. Habbas, S. Dellagi, A. Dandache
SAT (Boolean SATisfiability Problem) is a well studied type of NP-complete problem. Most SAT solvers rely on software implemented tree-search based algorithms. These algorithms, basically sequential or weakly parallel, are most often ineffective when dealing with large scale instances of SAT due to the large search space to be explored in order to find one solution. Despite several improvements and heuristics being proposed for this kind of approach, the fact remains that in real problems, the computational cost continues to be prohibitive. To improve SAT solvers performance, a new trend has emerged in the late years, introducing hardware acceleration. The proposed architectures are in general hybrid, combining software and hardware parts dedicated respectively to the decisional and hard-computional parts of the algorithm. Still, most the hybrid approaches remain constrained by their limited data-access bandwith capacity. In this paper, we propose a new approach, entirely based on hardware and not depending on the SAT-instance to be solved (treated as data). It is fully configurable at synthesis in regard to the level of parallel computation and parallel buffering, as to the size of the SAT instance that can be processed (maximal number of variables and maximal clause length, the total number of clauses being unlimited). One of the main goals is to allow a more effective use of the hardware computational power by reducing the dependence to data contained in low bandwith data storage (such as RAM).
{"title":"A pure hardware k-SAT solver architecture for FPGA based on generic tree-search","authors":"K. Bousmar, F. Monteiro, Z. Habbas, S. Dellagi, A. Dandache","doi":"10.1109/ICM.2017.8268894","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268894","url":null,"abstract":"SAT (Boolean SATisfiability Problem) is a well studied type of NP-complete problem. Most SAT solvers rely on software implemented tree-search based algorithms. These algorithms, basically sequential or weakly parallel, are most often ineffective when dealing with large scale instances of SAT due to the large search space to be explored in order to find one solution. Despite several improvements and heuristics being proposed for this kind of approach, the fact remains that in real problems, the computational cost continues to be prohibitive. To improve SAT solvers performance, a new trend has emerged in the late years, introducing hardware acceleration. The proposed architectures are in general hybrid, combining software and hardware parts dedicated respectively to the decisional and hard-computional parts of the algorithm. Still, most the hybrid approaches remain constrained by their limited data-access bandwith capacity. In this paper, we propose a new approach, entirely based on hardware and not depending on the SAT-instance to be solved (treated as data). It is fully configurable at synthesis in regard to the level of parallel computation and parallel buffering, as to the size of the SAT instance that can be processed (maximal number of variables and maximal clause length, the total number of clauses being unlimited). One of the main goals is to allow a more effective use of the hardware computational power by reducing the dependence to data contained in low bandwith data storage (such as RAM).","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117220300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268811
J. Bazzi, H. Kassem, A. Curutchet, F. Pourchon, N. Derrier, D. Céli, T. Zimmer
This paper presents different de-embedding methods applied in semiconductor industry, used to retrieve intrinsic device performances from high frequency S-parameters On-wafer measurement. A de-embedding method with a reduced set of dummies is proposed for conducting accurate on-wafer device measurement in the gigahertz range. The experimental results on a device characteristic up to 110GHz show that it has a comparable accuracy than a more complex one.
{"title":"A two-step de-embedding method valid up to 110 GHz","authors":"J. Bazzi, H. Kassem, A. Curutchet, F. Pourchon, N. Derrier, D. Céli, T. Zimmer","doi":"10.1109/ICM.2017.8268811","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268811","url":null,"abstract":"This paper presents different de-embedding methods applied in semiconductor industry, used to retrieve intrinsic device performances from high frequency S-parameters On-wafer measurement. A de-embedding method with a reduced set of dummies is proposed for conducting accurate on-wafer device measurement in the gigahertz range. The experimental results on a device characteristic up to 110GHz show that it has a comparable accuracy than a more complex one.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116135082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268872
M. Tolba, L. Said, A. Madian, A. Radwan
The fractional-order derivative and integral of Grünwald Letnikov's definition are implemented based on FPGA for different fractional orders. A new algorithm is proposed to implement the GL integral based on linear approximation approach, where the memory dependency of the fractional order systems is eliminated. Moreover, the linear approximation design shows an improvement of 91% and 92% in the error and the mean percentage error compared with prior art. The proposed approach has been designed and implemented based on Verilog Hardware Description Language (HDL) and realized on Nexys 4 Artix-7 FPGA XC7A100T.
{"title":"FPGA implementation of fractional-order integrator and differentiator based on Grünwald Letnikov's definition","authors":"M. Tolba, L. Said, A. Madian, A. Radwan","doi":"10.1109/ICM.2017.8268872","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268872","url":null,"abstract":"The fractional-order derivative and integral of Grünwald Letnikov's definition are implemented based on FPGA for different fractional orders. A new algorithm is proposed to implement the GL integral based on linear approximation approach, where the memory dependency of the fractional order systems is eliminated. Moreover, the linear approximation design shows an improvement of 91% and 92% in the error and the mean percentage error compared with prior art. The proposed approach has been designed and implemented based on Verilog Hardware Description Language (HDL) and realized on Nexys 4 Artix-7 FPGA XC7A100T.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268837
A. Abdallah, D. Felici, G. Aielli, R. Cardarelli
In this article we present a Field Programmable Gate Arrays (FPGA) implementation inspired by a weighting resistor matrix (WRM) for fast discrete segment line detection in digital images. The implementation proposed here achieves both real time processing and very good performance, taking advantage of the flexibility and the fast deployment of the FPGA for real time segment detection applications.
{"title":"FPGA implementation of resistor network for fast segment line detector","authors":"A. Abdallah, D. Felici, G. Aielli, R. Cardarelli","doi":"10.1109/ICM.2017.8268837","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268837","url":null,"abstract":"In this article we present a Field Programmable Gate Arrays (FPGA) implementation inspired by a weighting resistor matrix (WRM) for fast discrete segment line detection in digital images. The implementation proposed here achieves both real time processing and very good performance, taking advantage of the flexibility and the fast deployment of the FPGA for real time segment detection applications.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268842
Dalila Laouej, H. Daoud, M. Loulou
A fully differential Telescopic operational transconductance amplifier (OTA) and a sixth order Butterworth Gm-C low pass filter are presented in this paper. Both circuits are designed for medical applications in 2.4 GHz ISM band for IEEE 802.15.4 / ZigBee standard. The filter consists of three biquads. The design of the Telescopic OTA is carried out using two optimization methods, Gm/ID and Particle Swarm Optimization (PSO) algorithm. Both circuits are implemented with TSMC 0.18 μm CMOS technology. Based on optimized OTA, the Gm-C filter has a cutoff frequency of 2.3 MHz and consumes only 1.55mW.
{"title":"Design of sixth order butterworth Gm-C filter using Particle Swarm Optimization program for biomedical application","authors":"Dalila Laouej, H. Daoud, M. Loulou","doi":"10.1109/ICM.2017.8268842","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268842","url":null,"abstract":"A fully differential Telescopic operational transconductance amplifier (OTA) and a sixth order Butterworth Gm-C low pass filter are presented in this paper. Both circuits are designed for medical applications in 2.4 GHz ISM band for IEEE 802.15.4 / ZigBee standard. The filter consists of three biquads. The design of the Telescopic OTA is carried out using two optimization methods, Gm/ID and Particle Swarm Optimization (PSO) algorithm. Both circuits are implemented with TSMC 0.18 μm CMOS technology. Based on optimized OTA, the Gm-C filter has a cutoff frequency of 2.3 MHz and consumes only 1.55mW.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116964723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268888
J. A. Costa, T. Pimenta
A CMOS Gm-C Notch filter for powerline interference rejection in EEG systems is described. The pass-band covers all the four bands of brain wave and, with a bandwidth of 2.17 kHz, enables a deep study of the frequencies of less interest. Besides that, a capacitor programmable circuit makes the filter possible to reject with more than 90 dB the powerline interference for 50 Hz or 60 Hz. The notch filter employs operational transconductance amplifiers working in the weak region, with transconductance of 1.259 nA/V, enabling the use of small capacitors for on-chip integration. In this project, we designed a circuit in 0.13 μm CMOS technology, for a 1.0 V power supply and 10 nA bias current. Simulations conducted on CADENCE (Virtuoso Analog Design Environment) show good performance of the filter for filtering the noise in acquired EEG signals.
{"title":"A CMOS low-power wider band Gm-C notch filter for EEG","authors":"J. A. Costa, T. Pimenta","doi":"10.1109/ICM.2017.8268888","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268888","url":null,"abstract":"A CMOS Gm-C Notch filter for powerline interference rejection in EEG systems is described. The pass-band covers all the four bands of brain wave and, with a bandwidth of 2.17 kHz, enables a deep study of the frequencies of less interest. Besides that, a capacitor programmable circuit makes the filter possible to reject with more than 90 dB the powerline interference for 50 Hz or 60 Hz. The notch filter employs operational transconductance amplifiers working in the weak region, with transconductance of 1.259 nA/V, enabling the use of small capacitors for on-chip integration. In this project, we designed a circuit in 0.13 μm CMOS technology, for a 1.0 V power supply and 10 nA bias current. Simulations conducted on CADENCE (Virtuoso Analog Design Environment) show good performance of the filter for filtering the noise in acquired EEG signals.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116999922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268877
Z. Sabiri, N. Machkour, Elm. Kheddioui, Abdellah Ailane, M. Tabaa
This paper This paper covers the control of a hybrid system made up of a photovoltaic field, a variable speed wind turbine based on an asynchronous Doubly-Fed Induction Generator and a storage battery. The main objective of this work is to control the energy sources separately to extract the maximum of power from solar and wind energies. Then, a management algorithm will be implemented to explore the collected energy. The verification of the achieved study will be done in a simulation within the Matlab/Simulink environment. The contribution of this paper is supposed to present a new power management architecture.
{"title":"A new architecture of energy management applied to hybrid renewable energy system","authors":"Z. Sabiri, N. Machkour, Elm. Kheddioui, Abdellah Ailane, M. Tabaa","doi":"10.1109/ICM.2017.8268877","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268877","url":null,"abstract":"This paper This paper covers the control of a hybrid system made up of a photovoltaic field, a variable speed wind turbine based on an asynchronous Doubly-Fed Induction Generator and a storage battery. The main objective of this work is to control the energy sources separately to extract the maximum of power from solar and wind energies. Then, a management algorithm will be implemented to explore the collected energy. The verification of the achieved study will be done in a simulation within the Matlab/Simulink environment. The contribution of this paper is supposed to present a new power management architecture.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125267177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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