Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268812
M. Moradi, M. Ehsanian
Carrier recovery is very essential in tracking systems especially in noisy environment and high dynamic receivers. There are different PLL approaches that are proposed for making compromise between noise and dynamic in literatures. Here, a novel Digital PLL is proposed with a type-2 fuzzy logic controller for improving compatibility with noise and user dynamic in digital receivers. Adjusting filter coefficients with a type-2 Fuzzy Logic controller will result in best operation for rejecting noise and dynamic compensation. The proposed DPLL resultant by Xilinx System Generator shows better response to phase step, input signal jitter, frequency step and ramp signals.
{"title":"An FPGA based DPLL with fuzzy logic controllable loop filters","authors":"M. Moradi, M. Ehsanian","doi":"10.1109/ICM.2017.8268812","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268812","url":null,"abstract":"Carrier recovery is very essential in tracking systems especially in noisy environment and high dynamic receivers. There are different PLL approaches that are proposed for making compromise between noise and dynamic in literatures. Here, a novel Digital PLL is proposed with a type-2 fuzzy logic controller for improving compatibility with noise and user dynamic in digital receivers. Adjusting filter coefficients with a type-2 Fuzzy Logic controller will result in best operation for rejecting noise and dynamic compensation. The proposed DPLL resultant by Xilinx System Generator shows better response to phase step, input signal jitter, frequency step and ramp signals.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128996848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268863
Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache
This article presents a new pipeline-parallel architecture of Inverse Discrete Wavelet Packet Transform (IDWPT) for all wavelet family implemented in FPGA technology using a parallel direct FIR filter. Our aim in this work is to develop a generic VHDL-RTL model and configurable architecture of pipeline-parallel architecture of IDWPT. This architecture provide ultra-high speed sample processing with a restricted amount of used hardware. To achieve that, we propose a P-parallel IDWPT based on Mallat binary tree algorithm and a P-parallel/modified direct FIR filter under the strategy of pipeline-parallel and sharing hardware resource. The key of this model is the data manage/interleaving of pipeline/P-parallel concept and shared hardware of different level in the transformation. This architecture is fully configurable: (i) in synthesis according of various parameters like the parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient and (ii) in pro-synthesis according to the coefficients of low-pass and high-pass filters, in other words the filters coefficients can be loaded after synthesis. Consequently, the simulation results accelerated to an approximate value of P∗(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV — (FPGA) and it was developed in VHDL at RTL level modeling.
本文提出了一种新的基于并行直接FIR滤波器的反离散小波包变换(IDWPT)的流水线并行结构。本文的目标是开发通用的VHDL-RTL模型和IDWPT管道并行体系结构的可配置体系结构。该架构在使用有限数量的硬件的情况下提供超高速样品处理。为此，我们提出了一种基于Mallat二叉树算法的p并行IDWPT和一种基于管道并行和硬件资源共享策略的p并行/改进直接FIR滤波器。该模型的关键是数据管理/管道的交错/ p并行概念和转换中不同层次的共享硬件。该架构是完全可配置的:(i)在合成时根据并行度、树深度(树层数)、滤波器的顺序和滤波器量化系数等各种参数进行合成;(ii)在预合成时根据低通和高通滤波器的系数进行合成，即在合成后可以加载滤波器系数。因此，模拟结果加速到P *(频率)的近似值。此外，树的深度和过滤器的顺序对吞吐量的影响很小(仅由于位置和路由的变化)。该架构采用Altera Quartus prime lite版合成，目标是Altera Cyclone IV - (FPGA)，并在RTL级建模中使用VHDL进行开发。
{"title":"A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture","authors":"Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache","doi":"10.1109/ICM.2017.8268863","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268863","url":null,"abstract":"This article presents a new pipeline-parallel architecture of Inverse Discrete Wavelet Packet Transform (IDWPT) for all wavelet family implemented in FPGA technology using a parallel direct FIR filter. Our aim in this work is to develop a generic VHDL-RTL model and configurable architecture of pipeline-parallel architecture of IDWPT. This architecture provide ultra-high speed sample processing with a restricted amount of used hardware. To achieve that, we propose a P-parallel IDWPT based on Mallat binary tree algorithm and a P-parallel/modified direct FIR filter under the strategy of pipeline-parallel and sharing hardware resource. The key of this model is the data manage/interleaving of pipeline/P-parallel concept and shared hardware of different level in the transformation. This architecture is fully configurable: (i) in synthesis according of various parameters like the parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient and (ii) in pro-synthesis according to the coefficients of low-pass and high-pass filters, in other words the filters coefficients can be loaded after synthesis. Consequently, the simulation results accelerated to an approximate value of P∗(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV — (FPGA) and it was developed in VHDL at RTL level modeling.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128575830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268889
A. Rodrigues, R. Moreno, P. Crepaldi, T. Pimenta
Ultra-dense array of Electroencephalogram (EEG) may contain 256 or even 512 electrodes, which offers a challenge to provide intercommunication between each electrode and a central communication hub. This article presents a solution for communication between several electrodes and a hub, in same channel, to be implemented by a pair of wires. Since each electrode may be differently located over the scalp, and since they can perform signal amplification and filtering, they must be individually configured, and thus the communication must be bidirectional. A dedicated channel to each electrode would be unfeasible due to the large number of wiring. Thus, we have developed an asynchronous bidirectional communication protocol that allows a large number of devices in a single channel. The communication hub acts a single master and all electrodes are the slaves, but only one at a time. The protocol was implemented in Verilog and validated in a system implemented with FPGA boards.
{"title":"Implementation of a bidirecional serial communication protocol using shared channel","authors":"A. Rodrigues, R. Moreno, P. Crepaldi, T. Pimenta","doi":"10.1109/ICM.2017.8268889","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268889","url":null,"abstract":"Ultra-dense array of Electroencephalogram (EEG) may contain 256 or even 512 electrodes, which offers a challenge to provide intercommunication between each electrode and a central communication hub. This article presents a solution for communication between several electrodes and a hub, in same channel, to be implemented by a pair of wires. Since each electrode may be differently located over the scalp, and since they can perform signal amplification and filtering, they must be individually configured, and thus the communication must be bidirectional. A dedicated channel to each electrode would be unfeasible due to the large number of wiring. Thus, we have developed an asynchronous bidirectional communication protocol that allows a large number of devices in a single channel. The communication hub acts a single master and all electrodes are the slaves, but only one at a time. The protocol was implemented in Verilog and validated in a system implemented with FPGA boards.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128613400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268844
Ata Khorami, M. Sharifkhani
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC.
{"title":"An ultra low-power digital to analog converter for SAR ADCs","authors":"Ata Khorami, M. Sharifkhani","doi":"10.1109/ICM.2017.8268844","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268844","url":null,"abstract":"A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"879 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268865
Abbas Naghibzadeh, H. Rezaee-Dehsorkh, N. Ravanshad
Successive approximation analog to digital converters (SARs) are widely used in electronic circuits because of good performance from the power consumption, resolution and speed points of view. Leakage currents and DAC incomplete settling limits the performance of these ADCs in low and high sampling rates respectively. This limits the range of the sampling rate in which a SAR ADC can be used and so the usage of this ADC in multi-purpose SoCs. In this paper a background calibration technique is used in order to improve the range of the SAR ADC sampling rate. It is shown that by utilizing this technique, the sampling rate can be improved in a range of from 50 kHz to 1 MHz for a 10-bit SAR ADC with ENOB > 9 bit which is designed and simulated in 90 nm CMOS technology with a 1.2 V supply voltage.
{"title":"Calibration of SAR analog-to-digital converters for expanding the sampling rate range","authors":"Abbas Naghibzadeh, H. Rezaee-Dehsorkh, N. Ravanshad","doi":"10.1109/ICM.2017.8268865","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268865","url":null,"abstract":"Successive approximation analog to digital converters (SARs) are widely used in electronic circuits because of good performance from the power consumption, resolution and speed points of view. Leakage currents and DAC incomplete settling limits the performance of these ADCs in low and high sampling rates respectively. This limits the range of the sampling rate in which a SAR ADC can be used and so the usage of this ADC in multi-purpose SoCs. In this paper a background calibration technique is used in order to improve the range of the SAR ADC sampling rate. It is shown that by utilizing this technique, the sampling rate can be improved in a range of from 50 kHz to 1 MHz for a 10-bit SAR ADC with ENOB > 9 bit which is designed and simulated in 90 nm CMOS technology with a 1.2 V supply voltage.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268814
Y. Erhel, N. Amiot, D. Lemur, F. Marie, M. Oger
This paper presents an application of PDOA methods to the localization of a static VHF transmitter. After a summary presentation of hyperbolic methods, simulations are carried out involving least mean squares algorithms to estimate the transmitter position. They underline a reduction of the localization error induced by the weighted least mean squares algorithm. In a final step, an experimentation on a small scale scheme and set up with 9 sensors provides a transmitter localization with an accuracy coherent with simulation results.
{"title":"Localization of a VHF transmitter based on PDOA methods: Simulations and experiments","authors":"Y. Erhel, N. Amiot, D. Lemur, F. Marie, M. Oger","doi":"10.1109/ICM.2017.8268814","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268814","url":null,"abstract":"This paper presents an application of PDOA methods to the localization of a static VHF transmitter. After a summary presentation of hyperbolic methods, simulations are carried out involving least mean squares algorithms to estimate the transmitter position. They underline a reduction of the localization error induced by the weighted least mean squares algorithm. In a final step, an experimentation on a small scale scheme and set up with 9 sensors provides a transmitter localization with an accuracy coherent with simulation results.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133785401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268890
Hossam ElGemmazy, A. Helmy, H. Mostafa, Y. Ismail
This paper presents a novel concept along with a suggested CMOS-based design of the fully differential operational floating conveyor (FD-OFC). The FD-OFC concept and design has been introduced for the first time by the authors [9] as an 8 (4×4) port general purpose analog building block. The differential action offered by the proposed design can be empolyed in numerous analog and/or hybrid (analog/digital) VLSI applications, particularly where a high noise rejection ratio is desired. Furthermore, the proposed design can operate under biasing conditions as low as 1.2 V (instead of the 1.5 V bias in [9]) at frequencies up to 600 MHz in addition to higher open loop transimpedance gain of 104 dB (compared to 44.5 dB in [9]). These operating conditions recommend the proposed device to be integrated to a wide range of low power-high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment.
{"title":"An improved design for high speed analog applications of the fully differential operational floating conveyor","authors":"Hossam ElGemmazy, A. Helmy, H. Mostafa, Y. Ismail","doi":"10.1109/ICM.2017.8268890","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268890","url":null,"abstract":"This paper presents a novel concept along with a suggested CMOS-based design of the fully differential operational floating conveyor (FD-OFC). The FD-OFC concept and design has been introduced for the first time by the authors [9] as an 8 (4×4) port general purpose analog building block. The differential action offered by the proposed design can be empolyed in numerous analog and/or hybrid (analog/digital) VLSI applications, particularly where a high noise rejection ratio is desired. Furthermore, the proposed design can operate under biasing conditions as low as 1.2 V (instead of the 1.5 V bias in [9]) at frequencies up to 600 MHz in addition to higher open loop transimpedance gain of 104 dB (compared to 44.5 dB in [9]). These operating conditions recommend the proposed device to be integrated to a wide range of low power-high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131880351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268896
M. E. Gibari, S. Bretin, Patrick Derval, S. Ginestar, Guillaume Lirzin, Hongwu Li
A novel structure of high performance narrow band-pass filters on thin polymer film is reported in this paper. It's composed of two microstrip resonators placed between two via-free microstrip-grounded coplanar waveguide transitions. It combines therefore compactness, low-cost, fabrication easiness of microstrip lines and connection facility of coplanar pads. Narrow band-pass filters have been optimized by using HFSS software, realized and characterized, over the range of Ka-band frequencies. With the band-pass filter realized on thin BCB polymer (benzocyclobutene, relative permittivity er = 2.65 and loss tangent tanô = 0.0025) film of 60 μm thick, the performance obtained for a center frequency optimized at 30.5 GHz is 28.8 for quality factor and −1.4 dB for insertion losses, with very good agreement between simulation and experiment results.
{"title":"Conception and realization of highly selective band-pass filters in Ka-band built on thin polymer films","authors":"M. E. Gibari, S. Bretin, Patrick Derval, S. Ginestar, Guillaume Lirzin, Hongwu Li","doi":"10.1109/ICM.2017.8268896","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268896","url":null,"abstract":"A novel structure of high performance narrow band-pass filters on thin polymer film is reported in this paper. It's composed of two microstrip resonators placed between two via-free microstrip-grounded coplanar waveguide transitions. It combines therefore compactness, low-cost, fabrication easiness of microstrip lines and connection facility of coplanar pads. Narrow band-pass filters have been optimized by using HFSS software, realized and characterized, over the range of Ka-band frequencies. With the band-pass filter realized on thin BCB polymer (benzocyclobutene, relative permittivity er = 2.65 and loss tangent tanô = 0.0025) film of 60 μm thick, the performance obtained for a center frequency optimized at 30.5 GHz is 28.8 for quality factor and −1.4 dB for insertion losses, with very good agreement between simulation and experiment results.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129689307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268882
A. Fouad, Y. Ismail, H. Mostafa
This paper presents a new design methodology of time-based capacitance-to-digital converters (T-CDCs). The sensor capacitance is the load capacitance of a voltage-to-time converter (VTC) circuit based on current starved inverters. The VTC circuit used has improved sensitivity, linearity and dynamic range. The time delay provided by the VTC circuit is buffered providing a time pulse proportional to the sensor capacitance (Cs). Thus, the VTC circuit becomes a capacitance-to-time converter (CTC) circuit. The time pulse is then digitized using a time-to-digital converter (TDC) circuit providing an output digital code proportional to the sensor capacitance. The output digital code is PVT calibrated using a reference capacitor (Cref). The proposed T-CDC system is a time-based ADC, but with the sensor capacitance as the load capacitance of the used VTC circuit and the input voltages of the current starved inverters in the VTC circuit are fixed and used for biasing. The prototype of the proposed T-CDC is implemented in UMC 130 nm CMOS technology. The T-CDC system is clocked with a 1-MHz clock signal to the VTC circuit. Experimental results show that for a 1 ns counting cycle of the TDC circuit, the system achieves a 8.5-bit resolution and consumes 20 μW with an energy efficiency figure-of-merit (FoM) of 55 fJ/step and a conversion time of 1 μs.
{"title":"Design of a time-based capacitance-to-digital converter using current starved inverters","authors":"A. Fouad, Y. Ismail, H. Mostafa","doi":"10.1109/ICM.2017.8268882","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268882","url":null,"abstract":"This paper presents a new design methodology of time-based capacitance-to-digital converters (T-CDCs). The sensor capacitance is the load capacitance of a voltage-to-time converter (VTC) circuit based on current starved inverters. The VTC circuit used has improved sensitivity, linearity and dynamic range. The time delay provided by the VTC circuit is buffered providing a time pulse proportional to the sensor capacitance (Cs). Thus, the VTC circuit becomes a capacitance-to-time converter (CTC) circuit. The time pulse is then digitized using a time-to-digital converter (TDC) circuit providing an output digital code proportional to the sensor capacitance. The output digital code is PVT calibrated using a reference capacitor (Cref). The proposed T-CDC system is a time-based ADC, but with the sensor capacitance as the load capacitance of the used VTC circuit and the input voltages of the current starved inverters in the VTC circuit are fixed and used for biasing. The prototype of the proposed T-CDC is implemented in UMC 130 nm CMOS technology. The T-CDC system is clocked with a 1-MHz clock signal to the VTC circuit. Experimental results show that for a 1 ns counting cycle of the TDC circuit, the system achieves a 8.5-bit resolution and consumes 20 μW with an energy efficiency figure-of-merit (FoM) of 55 fJ/step and a conversion time of 1 μs.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132270283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268826
Hussein Bazzi, Mohammad Abou Chanine, Ali Mohsen, A. Harb
This paper presents a 1V low phase noise ring based voltage-controlled-oscillator (VCO) for ultra-wide band (UWB) applications. The circuit is implemented in a 28-nm FDSOI technology. The VCO delay cell structure is characterized by a 3.75 mW power consumption and benefits from a new voltage control through the transistor body bias in order to achieve high performance with a wide tuning range. In the frequency range from 29 to 49 GHz, the lowest phase noise result is −132 dBc/Hz at 1 MHz frequency offset while operating at 49 GHz. These measurements lead to an excellent Figure of Merit (FoM) of −220 dBc/Hz.
{"title":"A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology","authors":"Hussein Bazzi, Mohammad Abou Chanine, Ali Mohsen, A. Harb","doi":"10.1109/ICM.2017.8268826","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268826","url":null,"abstract":"This paper presents a 1V low phase noise ring based voltage-controlled-oscillator (VCO) for ultra-wide band (UWB) applications. The circuit is implemented in a 28-nm FDSOI technology. The VCO delay cell structure is characterized by a 3.75 mW power consumption and benefits from a new voltage control through the transistor body bias in order to achieve high performance with a wide tuning range. In the frequency range from 29 to 49 GHz, the lowest phase noise result is −132 dBc/Hz at 1 MHz frequency offset while operating at 49 GHz. These measurements lead to an excellent Figure of Merit (FoM) of −220 dBc/Hz.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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