Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268841
M. Nakkar, Moustafa Mahmoud, A. Youssef
Multivariate Public Key Cryptosystems (MPKC) are cryptographic schemes based on the difficulty of solving a set of multivariate system of nonlinear equations over a finite field. MPKC are considered to be secure against quantum attacks. Rainbow, an MPKC signature scheme, is among the leading MPKC candidates for post quantum cryptography. In this paper, we propose and compare two fault analysis-resistant implementations for the Rainbow signature scheme. The hardware platform for our implementations is Xilinx FPGA Virtex 7 family. Our implementation for the Rainbow signature completes in 191 cycles using a 20ns clock period which is an improvement over the previously reported implementations. The verification completes in 141 cycles using the same clock period. The two proposed fault analysis-resistant schemes offer different levels of protections and increase the area overhead by a factor of 33% and 9%, respectively. The first protection scheme acquires a time overhead of about 72%, but the second one does not have any time overhead.
{"title":"Fault analysis-resistant implementation of Rainbow Signature scheme","authors":"M. Nakkar, Moustafa Mahmoud, A. Youssef","doi":"10.1109/ICM.2017.8268841","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268841","url":null,"abstract":"Multivariate Public Key Cryptosystems (MPKC) are cryptographic schemes based on the difficulty of solving a set of multivariate system of nonlinear equations over a finite field. MPKC are considered to be secure against quantum attacks. Rainbow, an MPKC signature scheme, is among the leading MPKC candidates for post quantum cryptography. In this paper, we propose and compare two fault analysis-resistant implementations for the Rainbow signature scheme. The hardware platform for our implementations is Xilinx FPGA Virtex 7 family. Our implementation for the Rainbow signature completes in 191 cycles using a 20ns clock period which is an improvement over the previously reported implementations. The verification completes in 141 cycles using the same clock period. The two proposed fault analysis-resistant schemes offer different levels of protections and increase the area overhead by a factor of 33% and 9%, respectively. The first protection scheme acquires a time overhead of about 72%, but the second one does not have any time overhead.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268860
Wessam S. ElAraby, A. Madian, M. Ashour, Ibrahim Farag, M. Nassef
In this paper, four different algorithms present a comparative study of edge detection algorithms based on different fractional order differentiation. The first two algorithms present different fractional masks for the edge detection. Then, the other two algorithms use genetic algorithm to get better edge detection using the previous fractional masks. A fully automatic way to get the number of thresholds for each image using K-means principle is used. The performance comparison is done between different fractional algorithms with and without genetic algorithm. The performance comparison upon the addition of salt and pepper noise is evaluated by measuring the peak signal to noise ratio (PSNR) and bit error rate (BER). From results, it can be concluded that fractional edge detection based on genetic algorithm enhances performance.
{"title":"Fractional edge detection based on genetic algorithm","authors":"Wessam S. ElAraby, A. Madian, M. Ashour, Ibrahim Farag, M. Nassef","doi":"10.1109/ICM.2017.8268860","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268860","url":null,"abstract":"In this paper, four different algorithms present a comparative study of edge detection algorithms based on different fractional order differentiation. The first two algorithms present different fractional masks for the edge detection. Then, the other two algorithms use genetic algorithm to get better edge detection using the previous fractional masks. A fully automatic way to get the number of thresholds for each image using K-means principle is used. The performance comparison is done between different fractional algorithms with and without genetic algorithm. The performance comparison upon the addition of salt and pepper noise is evaluated by measuring the peak signal to noise ratio (PSNR) and bit error rate (BER). From results, it can be concluded that fractional edge detection based on genetic algorithm enhances performance.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114859469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268815
Arsham Abedini, M. Ehsanian
In many researches, defects are detected with using reference image. But recently, detection of defects without reference image is considered. Because Automated visual examination systems are necessary for developing in the industry, specifically when the quality of products is considered in industry [1]. Therefore, we present a novel method for detecting defects on integrated circuit based on defect features. In this paper, we classify defects with evaluating dispersion of defects based on Hough Transform.
{"title":"Defect detection on IC wafers based on neural network","authors":"Arsham Abedini, M. Ehsanian","doi":"10.1109/ICM.2017.8268815","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268815","url":null,"abstract":"In many researches, defects are detected with using reference image. But recently, detection of defects without reference image is considered. Because Automated visual examination systems are necessary for developing in the industry, specifically when the quality of products is considered in industry [1]. Therefore, we present a novel method for detecting defects on integrated circuit based on defect features. In this paper, we classify defects with evaluating dispersion of defects based on Hough Transform.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121850739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268874
K. Bousmar, F. Monteiro, S. Dellagi, Z. Habbas, A. Dandache
This paper presents the industrial manufacturing problem, by using the ILP (Integer Linear Programming) method, which will help us to get closer to the SAT (SATisfiability) of propositional formula that is a well-known to be a NP-Complete problem. The chosen problem for this paper is the production merchandise system that has a lot of constraints, which were studied, analyzed and modeled in ILP. Our purpose for those researches is to present this industrial problem in a SAT formula, because in these last decades, a promising approach has emerged for solving efficiently large size instances by using FPGA architectures. This paper follows so this last direction and proposes a new and original way to solve them by using Integer Linear Programming, which is close to SAT.
{"title":"Modelling industrial manufacturing problem using ILP solver : Case of production analysis","authors":"K. Bousmar, F. Monteiro, S. Dellagi, Z. Habbas, A. Dandache","doi":"10.1109/ICM.2017.8268874","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268874","url":null,"abstract":"This paper presents the industrial manufacturing problem, by using the ILP (Integer Linear Programming) method, which will help us to get closer to the SAT (SATisfiability) of propositional formula that is a well-known to be a NP-Complete problem. The chosen problem for this paper is the production merchandise system that has a lot of constraints, which were studied, analyzed and modeled in ILP. Our purpose for those researches is to present this industrial problem in a SAT formula, because in these last decades, a promising approach has emerged for solving efficiently large size instances by using FPGA architectures. This paper follows so this last direction and proposes a new and original way to solve them by using Integer Linear Programming, which is close to SAT.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114158178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268820
K. Salah, Mohamed Abdel Salam
Electromagnetic (EM) simulation is currently a highly-needed planning tool in high frequency systems. The main objective of EM simulation is to find an approximate solution for Maxwell's equations that satisfies the given boundary conditions and a set of initial conditions. The most famous methods for solving EM problems are finite element method (FEM). Computations involved in FEM consume too much time. In this paper, the performance improvement from using hardware emulation (FPGAs) and GPUs to solve large numbers of linear equations is evaluated. The results show that GPUs have superior performance over FPGAs.
{"title":"A comparative analysis between FPGA and GPU for solving large numbers of linear equations","authors":"K. Salah, Mohamed Abdel Salam","doi":"10.1109/ICM.2017.8268820","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268820","url":null,"abstract":"Electromagnetic (EM) simulation is currently a highly-needed planning tool in high frequency systems. The main objective of EM simulation is to find an approximate solution for Maxwell's equations that satisfies the given boundary conditions and a set of initial conditions. The most famous methods for solving EM problems are finite element method (FEM). Computations involved in FEM consume too much time. In this paper, the performance improvement from using hardware emulation (FPGAs) and GPUs to solve large numbers of linear equations is evaluated. The results show that GPUs have superior performance over FPGAs.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134216681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268864
Ahmed El-Naggar, A. Medhat, Bassma Al-Abassy, Essraa Massoud, Hala Ibrahim, Mostafa Khamis, A. Shalaby
On-chip communication is one of the main challenges introduced to high level integrated system-on-chip design. To address complexity and wiring challenges, network-on-chip has been proposed as a prominent solution capable of providing a reliable and efficient communication platform. Accordingly, network design counts as a key parameter that defines the overall system performance. In this paper, we propose a network design that integrates centralized routers in distributed networks. Our results are compared to distributed networks of different sizes using a variety of synthetic traffic patterns and benchmarks.
{"title":"Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip","authors":"Ahmed El-Naggar, A. Medhat, Bassma Al-Abassy, Essraa Massoud, Hala Ibrahim, Mostafa Khamis, A. Shalaby","doi":"10.1109/ICM.2017.8268864","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268864","url":null,"abstract":"On-chip communication is one of the main challenges introduced to high level integrated system-on-chip design. To address complexity and wiring challenges, network-on-chip has been proposed as a prominent solution capable of providing a reliable and efficient communication platform. Accordingly, network design counts as a key parameter that defines the overall system performance. In this paper, we propose a network design that integrates centralized routers in distributed networks. Our results are compared to distributed networks of different sizes using a variety of synthetic traffic patterns and benchmarks.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126616881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268810
Z. Szadkowski, A. Szadkowska
The standard triggers T1 and ToT for the surface detectors of the Pierre Auger Observatory based on 3-fold (T1) or 2-fold (ToT) coincidences in the time domain. The Discrete Cosine Transform (DCT) algorithm implemented as 3 engines for 3 PMT channels implemented into the surface detector Front-End Board (FEB) FPGA analyzes online shapes of the signal waveforms (ADC traces) and generates a trigger if selected number (7–9) of sub-triggers (as scaled DCT[k]/DCT[1]) are “fired” in at least two channels simultaneously. For assumed sampling frequency fS = 120 MHz, the filter is built from RLC components on relatively small values. Resistors and inductors are available in 0.1 % and 5 % tolerance, however, capacitors in pF range are available even in 0.1 pF, but the parasitic capacitance on the FEB can dramatically change the frequency characteristics. Daily temperature variations reach even 40 ° C, which additionally change the characteristic of the analog FEB section. The paper analyzes the influence of the Bessel filter frequency characteristics on the efficiency of the DCT trigger.
{"title":"DCT trigger rate as a function of anti-aliasing Bessel filter environmental variation","authors":"Z. Szadkowski, A. Szadkowska","doi":"10.1109/ICM.2017.8268810","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268810","url":null,"abstract":"The standard triggers T1 and ToT for the surface detectors of the Pierre Auger Observatory based on 3-fold (T1) or 2-fold (ToT) coincidences in the time domain. The Discrete Cosine Transform (DCT) algorithm implemented as 3 engines for 3 PMT channels implemented into the surface detector Front-End Board (FEB) FPGA analyzes online shapes of the signal waveforms (ADC traces) and generates a trigger if selected number (7–9) of sub-triggers (as scaled DCT[k]/DCT[1]) are “fired” in at least two channels simultaneously. For assumed sampling frequency fS = 120 MHz, the filter is built from RLC components on relatively small values. Resistors and inductors are available in 0.1 % and 5 % tolerance, however, capacitors in pF range are available even in 0.1 pF, but the parasitic capacitance on the FEB can dramatically change the frequency characteristics. Daily temperature variations reach even 40 ° C, which additionally change the characteristic of the analog FEB section. The paper analyzes the influence of the Bessel filter frequency characteristics on the efficiency of the DCT trigger.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123529531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268851
Jérémy Nadal, C. A. Nour, A. Baghdadi
Several technical contributions are emerging nowadays to fulfill the new requirements foreseen in the 5th generation (5G) of mobile communication systems. Among these contributions, different variants of waveform design are proposed for the new radio air interface as alternative to orthogonal frequency-division multiplexing (OFDM) adopted in 4G. However, in order to prove the feasibility and the benefits of the proposed waveforms, practical hardware implementations are necessary. This paper presents one of the first flexible and efficient hardware platform for waveform design proof-of-concept. The proposed platform constitutes a complete hardware/software development environment, with digital processing, radio frequency boards, and all associated interfaces for control, communication, and display. Promising waveform candidates are implemented, in addition to OFDM, with careful architectural choices to allow fair comparisons. Furthermore, the proposed platform allows the support of several communication scenarios as foreseen in 5G.
{"title":"Flexible hardware platform for demonstrating new 5G waveform candidates","authors":"Jérémy Nadal, C. A. Nour, A. Baghdadi","doi":"10.1109/ICM.2017.8268851","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268851","url":null,"abstract":"Several technical contributions are emerging nowadays to fulfill the new requirements foreseen in the 5th generation (5G) of mobile communication systems. Among these contributions, different variants of waveform design are proposed for the new radio air interface as alternative to orthogonal frequency-division multiplexing (OFDM) adopted in 4G. However, in order to prove the feasibility and the benefits of the proposed waveforms, practical hardware implementations are necessary. This paper presents one of the first flexible and efficient hardware platform for waveform design proof-of-concept. The proposed platform constitutes a complete hardware/software development environment, with digital processing, radio frequency boards, and all associated interfaces for control, communication, and display. Promising waveform candidates are implemented, in addition to OFDM, with careful architectural choices to allow fair comparisons. Furthermore, the proposed platform allows the support of several communication scenarios as foreseen in 5G.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"32 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268824
M. Assaad, A. Harb
This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10−12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s.
{"title":"A synthesizable serial link for point-to-point communication in SoC/NoC","authors":"M. Assaad, A. Harb","doi":"10.1109/ICM.2017.8268824","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268824","url":null,"abstract":"This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10−12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125717908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICM.2017.8268852
Abdallah Nasser Eldeen, A. Rahal
In this paper we present the design of a digital PIN diode based attenuator at L-band. The design concept uses an analog attenuator digitally controlled to generate accurate bias. A six-bit attenuator is presented. The digital control concept allows a high cumulative accuracy which is implemented using of the shelf Arduino processor.
{"title":"Digitally controlled microwave variable attenuator","authors":"Abdallah Nasser Eldeen, A. Rahal","doi":"10.1109/ICM.2017.8268852","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268852","url":null,"abstract":"In this paper we present the design of a digital PIN diode based attenuator at L-band. The design concept uses an analog attenuator digitally controlled to generate accurate bias. A six-bit attenuator is presented. The digital control concept allows a high cumulative accuracy which is implemented using of the shelf Arduino processor.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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