Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242136
Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou
Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25∼3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23∼0.4 times of the related work).
{"title":"Research and design of add-based length-scalable dual-field modular multiplication-addition-subtraction","authors":"Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou","doi":"10.1109/ICAM.2017.8242136","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242136","url":null,"abstract":"Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25∼3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23∼0.4 times of the related work).","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127313063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242129
Yaping Cheng, S. Huang, Jiaqi Yin, Q. Duan
This paper presents an effective design solution for a high-sensitivity current-shunt monitor which operates with an independent supply voltage from 5 to 16 V and achieves a wide input common-mode voltage range from −16 to 60 V. The proposed current-shunt monitor adopts two amplifiers, a current source and several resistors to constitute a feedback circuit and successfully sense drops across shunt at common-mode voltages from −16 to 60 V. The sensing current was magnified by using a current-mirror circuit and a linear regulator. The proposed architecture has been implemented in a VIS-0.25μm BCD technology and its performances have been confirmed by simulation. The simulation results show that the current-shunt monitor can sense an input voltage difference between 4 and 16 mV and keeps a constant scaled gain of 100V / V where the input CM voltage varies from −16 to 60 V.
{"title":"A high-sensitivity current-shunt monitor with extended input common-mode voltage range","authors":"Yaping Cheng, S. Huang, Jiaqi Yin, Q. Duan","doi":"10.1109/ICAM.2017.8242129","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242129","url":null,"abstract":"This paper presents an effective design solution for a high-sensitivity current-shunt monitor which operates with an independent supply voltage from 5 to 16 V and achieves a wide input common-mode voltage range from −16 to 60 V. The proposed current-shunt monitor adopts two amplifiers, a current source and several resistors to constitute a feedback circuit and successfully sense drops across shunt at common-mode voltages from −16 to 60 V. The sensing current was magnified by using a current-mirror circuit and a linear regulator. The proposed architecture has been implemented in a VIS-0.25μm BCD technology and its performances have been confirmed by simulation. The simulation results show that the current-shunt monitor can sense an input voltage difference between 4 and 16 mV and keeps a constant scaled gain of 100V / V where the input CM voltage varies from −16 to 60 V.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127328454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Failure location and mechanism analysis about a microsystem fault is presented in this work. The fault phenomenon of abnormal low output power amplitude appears only at low temperature during thermal cycle test. A series of analysis including internal fault location and replacing parts for validation help to find the fault origin: a line winding inductor. The failure mechanism of the failed inductor is analyzed by optical microscope, X-ray inspection, scanning electron microscope, energy spectrum analysis and so on. It is found that the enameled wire of the abnormal inductor is damaged during the installation process and the crack develops under thermal cyclic stress. By summarizing the analysis process and the test result, the investigation can provide reference for the failure analysis of similar microsystems.
{"title":"Failure analysis on the low output power abnormity of a microsystem during the thermal cycle","authors":"Jiajia Sun, Xu Wang, Zhibin Wang, Meng Meng, Zhimin Ding","doi":"10.1109/ICAM.2017.8242170","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242170","url":null,"abstract":"Failure location and mechanism analysis about a microsystem fault is presented in this work. The fault phenomenon of abnormal low output power amplitude appears only at low temperature during thermal cycle test. A series of analysis including internal fault location and replacing parts for validation help to find the fault origin: a line winding inductor. The failure mechanism of the failed inductor is analyzed by optical microscope, X-ray inspection, scanning electron microscope, energy spectrum analysis and so on. It is found that the enameled wire of the abnormal inductor is damaged during the installation process and the crack develops under thermal cyclic stress. By summarizing the analysis process and the test result, the investigation can provide reference for the failure analysis of similar microsystems.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242190
S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan
Present research work propose the design of a low energy and high throughput, hierarchical clustering based routing protocol for smart home sensor network application. Proposed protocol perform dynamic cluster head selection based on multiple node characteristics like node residual energy, node distance from sink and node average distance from neighbour nodes. Cluster head distribution is even and results in enhanced network lifetime. Sensor nodes process the sense data using local on-board processors and omit the redundant data from transmission. In this manner, cooperative effort by sensor nodes save significant amount of node transmission energy. Elongated lifetime and reduced data traffic in network reduce data loss rates during transmission and result in high throughput. Wireless channel model and path loss model for indoor residential environment are used for protocol simulation. Simulation is carried using MATLAB tool and results are obtained in terms of network lifetime, stability period, throughput etc. Results, as compared with existing protocols, proves the efficiency of proposed protocol.
{"title":"Cooperative effort based wireless sensor network clustering algorithm for smart home application","authors":"S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan","doi":"10.1109/ICAM.2017.8242190","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242190","url":null,"abstract":"Present research work propose the design of a low energy and high throughput, hierarchical clustering based routing protocol for smart home sensor network application. Proposed protocol perform dynamic cluster head selection based on multiple node characteristics like node residual energy, node distance from sink and node average distance from neighbour nodes. Cluster head distribution is even and results in enhanced network lifetime. Sensor nodes process the sense data using local on-board processors and omit the redundant data from transmission. In this manner, cooperative effort by sensor nodes save significant amount of node transmission energy. Elongated lifetime and reduced data traffic in network reduce data loss rates during transmission and result in high throughput. Wireless channel model and path loss model for indoor residential environment are used for protocol simulation. Simulation is carried using MATLAB tool and results are obtained in terms of network lifetime, stability period, throughput etc. Results, as compared with existing protocols, proves the efficiency of proposed protocol.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242140
Huibo Guo, G. Feng, Anping He, Jinzhao Wu
This paper proposes an asynchronous cycle circuit by providing Click element and joint module rather than clock-domain. The asynchronous mode of operation re-uses the simple asynchronous control protocols, takes full advantage of characteristics of Click, and commendably inherits the elasticity of the asynchronous micropipeline. The circuit in this paper has some individual coin. As a result, we can use it as a fixed and naturalized structure in application of VLSI asynchronous circuit design. Actually, when we transfer it to a strange circumstance, we only alter the output of counter which is the kernel of for-loop.
{"title":"An innovative implementation of asynchronous for-loop circuit with click micropipeline","authors":"Huibo Guo, G. Feng, Anping He, Jinzhao Wu","doi":"10.1109/ICAM.2017.8242140","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242140","url":null,"abstract":"This paper proposes an asynchronous cycle circuit by providing Click element and joint module rather than clock-domain. The asynchronous mode of operation re-uses the simple asynchronous control protocols, takes full advantage of characteristics of Click, and commendably inherits the elasticity of the asynchronous micropipeline. The circuit in this paper has some individual coin. As a result, we can use it as a fixed and naturalized structure in application of VLSI asynchronous circuit design. Actually, when we transfer it to a strange circumstance, we only alter the output of counter which is the kernel of for-loop.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131649946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242186
L. Wei, Duan Peng
The carrier frequency offset(CFO) in OFDM system is one of the key factors that affect the performance of wireless communication. Based on the analysis of the CFO estimation algorithm, this paper presents FPGA implementation scheme in the problem of OFDM fractional CFO estimation using pilot-based algorithm, including CFO estimation and CFO compensation. The circuit modules in the program were written in Verilog HDL. They are compiled, simulated and integrated under Xilinx programming software Vivado 2014.4. The simulation results show that the circuit module can accurately estimate and compensate the fractional CFO.
{"title":"Carrier frequency offset estimation and FPGA implementation in OFDM system","authors":"L. Wei, Duan Peng","doi":"10.1109/ICAM.2017.8242186","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242186","url":null,"abstract":"The carrier frequency offset(CFO) in OFDM system is one of the key factors that affect the performance of wireless communication. Based on the analysis of the CFO estimation algorithm, this paper presents FPGA implementation scheme in the problem of OFDM fractional CFO estimation using pilot-based algorithm, including CFO estimation and CFO compensation. The circuit modules in the program were written in Verilog HDL. They are compiled, simulated and integrated under Xilinx programming software Vivado 2014.4. The simulation results show that the circuit module can accurately estimate and compensate the fractional CFO.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242157
Xian Su, Qifeng Xu, Hao Chen
An OVT based on Mach-Zehnder interferometer is proposed in this paper, which helps to convert the electro-optic phase delay into the displacement of the interference fringe. And then, the voltage applied to the electro-optic crystal is obtained by positioning the displacement of the fringe, and the effectiveness of this method is verified by experiments. The new OVT meets the requirements of 0.5% accuracy class. And it has advantages of direct linear measurement, independent of light intensity and no limit by half wave voltage of crystal in measurement range. Moreover the new OVT is simple and easy to be built up.
{"title":"A new optical voltage sensor for linear measurement","authors":"Xian Su, Qifeng Xu, Hao Chen","doi":"10.1109/ICAM.2017.8242157","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242157","url":null,"abstract":"An OVT based on Mach-Zehnder interferometer is proposed in this paper, which helps to convert the electro-optic phase delay into the displacement of the interference fringe. And then, the voltage applied to the electro-optic crystal is obtained by positioning the displacement of the fringe, and the effectiveness of this method is verified by experiments. The new OVT meets the requirements of 0.5% accuracy class. And it has advantages of direct linear measurement, independent of light intensity and no limit by half wave voltage of crystal in measurement range. Moreover the new OVT is simple and easy to be built up.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242152
Yi Zuo, Anping He, Caihong Li, Lvying Yu
Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that it both embraces the efficient optimal capacity of synthesizing commercial FPGA Design Suite and the flexible bottom control ability for the implementation of the open-source third-part software. Moreover, this tool-chain can automatically generate customized placement and routing, which provided a feasibility to synthesize and implement asynchronous FPGA designs in bulk without the manual labor.
{"title":"An innovation tool-chain for synthesis and implementation of Xilinx FPGA devices","authors":"Yi Zuo, Anping He, Caihong Li, Lvying Yu","doi":"10.1109/ICAM.2017.8242152","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242152","url":null,"abstract":"Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that it both embraces the efficient optimal capacity of synthesizing commercial FPGA Design Suite and the flexible bottom control ability for the implementation of the open-source third-part software. Moreover, this tool-chain can automatically generate customized placement and routing, which provided a feasibility to synthesize and implement asynchronous FPGA designs in bulk without the manual labor.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to study the influence of vertical grounding electrode on impulse grounding resistance of substation ground network, the grounding model was built in COMSOL, and the impulse grounding resistances of substation grounding grid in different distribution, length and quantity of vertical grounding electrode were simulated and calculated. The results show that the closer the vertical ground to the lightning current injection point is, the smaller the impact grounding resistance is. The impulse grounding resistance, that has a minimum value, decreases first and then increases with the increase of the vertical grounding electrode length. When the additional vertical grounding electrodes are placed in accordance with the evacuation outside and internal density manner within a certain region ranging from the lightning current injection point, the impact grounding resistance has the best reduction effect.
{"title":"Simulation of impact of vertical grounding electrode on impulse grounding resistance of substation grounding network","authors":"Lijun Zhou, Jian He, Han Xu, Pengcheng Wang, Ying Chen, Sixiang Chen","doi":"10.1109/ICAM.2017.8242130","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242130","url":null,"abstract":"In order to study the influence of vertical grounding electrode on impulse grounding resistance of substation ground network, the grounding model was built in COMSOL, and the impulse grounding resistances of substation grounding grid in different distribution, length and quantity of vertical grounding electrode were simulated and calculated. The results show that the closer the vertical ground to the lightning current injection point is, the smaller the impact grounding resistance is. The impulse grounding resistance, that has a minimum value, decreases first and then increases with the increase of the vertical grounding electrode length. When the additional vertical grounding electrodes are placed in accordance with the evacuation outside and internal density manner within a certain region ranging from the lightning current injection point, the impact grounding resistance has the best reduction effect.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128227710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242127
W. Lai, S. Jang, Meng-Yan Fang
This letter presents a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductors to reduce the die area. At the supply voltage of 1V, the divider's free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.
{"title":"Small die area capacitive cross-coupled injection-locked frequency divider","authors":"W. Lai, S. Jang, Meng-Yan Fang","doi":"10.1109/ICAM.2017.8242127","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242127","url":null,"abstract":"This letter presents a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductors to reduce the die area. At the supply voltage of 1V, the divider's free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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