Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242166
Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun
A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.
{"title":"A 12.42μA 0.192ppm/°C high PSRR curvature-compensated CMOS bandgap voltage reference","authors":"Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun","doi":"10.1109/ICAM.2017.8242166","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242166","url":null,"abstract":"A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124575515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242136
Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou
Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25∼3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23∼0.4 times of the related work).
{"title":"Research and design of add-based length-scalable dual-field modular multiplication-addition-subtraction","authors":"Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou","doi":"10.1109/ICAM.2017.8242136","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242136","url":null,"abstract":"Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25∼3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23∼0.4 times of the related work).","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127313063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242129
Yaping Cheng, S. Huang, Jiaqi Yin, Q. Duan
This paper presents an effective design solution for a high-sensitivity current-shunt monitor which operates with an independent supply voltage from 5 to 16 V and achieves a wide input common-mode voltage range from −16 to 60 V. The proposed current-shunt monitor adopts two amplifiers, a current source and several resistors to constitute a feedback circuit and successfully sense drops across shunt at common-mode voltages from −16 to 60 V. The sensing current was magnified by using a current-mirror circuit and a linear regulator. The proposed architecture has been implemented in a VIS-0.25μm BCD technology and its performances have been confirmed by simulation. The simulation results show that the current-shunt monitor can sense an input voltage difference between 4 and 16 mV and keeps a constant scaled gain of 100V / V where the input CM voltage varies from −16 to 60 V.
{"title":"A high-sensitivity current-shunt monitor with extended input common-mode voltage range","authors":"Yaping Cheng, S. Huang, Jiaqi Yin, Q. Duan","doi":"10.1109/ICAM.2017.8242129","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242129","url":null,"abstract":"This paper presents an effective design solution for a high-sensitivity current-shunt monitor which operates with an independent supply voltage from 5 to 16 V and achieves a wide input common-mode voltage range from −16 to 60 V. The proposed current-shunt monitor adopts two amplifiers, a current source and several resistors to constitute a feedback circuit and successfully sense drops across shunt at common-mode voltages from −16 to 60 V. The sensing current was magnified by using a current-mirror circuit and a linear regulator. The proposed architecture has been implemented in a VIS-0.25μm BCD technology and its performances have been confirmed by simulation. The simulation results show that the current-shunt monitor can sense an input voltage difference between 4 and 16 mV and keeps a constant scaled gain of 100V / V where the input CM voltage varies from −16 to 60 V.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127328454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Failure location and mechanism analysis about a microsystem fault is presented in this work. The fault phenomenon of abnormal low output power amplitude appears only at low temperature during thermal cycle test. A series of analysis including internal fault location and replacing parts for validation help to find the fault origin: a line winding inductor. The failure mechanism of the failed inductor is analyzed by optical microscope, X-ray inspection, scanning electron microscope, energy spectrum analysis and so on. It is found that the enameled wire of the abnormal inductor is damaged during the installation process and the crack develops under thermal cyclic stress. By summarizing the analysis process and the test result, the investigation can provide reference for the failure analysis of similar microsystems.
{"title":"Failure analysis on the low output power abnormity of a microsystem during the thermal cycle","authors":"Jiajia Sun, Xu Wang, Zhibin Wang, Meng Meng, Zhimin Ding","doi":"10.1109/ICAM.2017.8242170","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242170","url":null,"abstract":"Failure location and mechanism analysis about a microsystem fault is presented in this work. The fault phenomenon of abnormal low output power amplitude appears only at low temperature during thermal cycle test. A series of analysis including internal fault location and replacing parts for validation help to find the fault origin: a line winding inductor. The failure mechanism of the failed inductor is analyzed by optical microscope, X-ray inspection, scanning electron microscope, energy spectrum analysis and so on. It is found that the enameled wire of the abnormal inductor is damaged during the installation process and the crack develops under thermal cyclic stress. By summarizing the analysis process and the test result, the investigation can provide reference for the failure analysis of similar microsystems.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242190
S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan
Present research work propose the design of a low energy and high throughput, hierarchical clustering based routing protocol for smart home sensor network application. Proposed protocol perform dynamic cluster head selection based on multiple node characteristics like node residual energy, node distance from sink and node average distance from neighbour nodes. Cluster head distribution is even and results in enhanced network lifetime. Sensor nodes process the sense data using local on-board processors and omit the redundant data from transmission. In this manner, cooperative effort by sensor nodes save significant amount of node transmission energy. Elongated lifetime and reduced data traffic in network reduce data loss rates during transmission and result in high throughput. Wireless channel model and path loss model for indoor residential environment are used for protocol simulation. Simulation is carried using MATLAB tool and results are obtained in terms of network lifetime, stability period, throughput etc. Results, as compared with existing protocols, proves the efficiency of proposed protocol.
{"title":"Cooperative effort based wireless sensor network clustering algorithm for smart home application","authors":"S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan","doi":"10.1109/ICAM.2017.8242190","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242190","url":null,"abstract":"Present research work propose the design of a low energy and high throughput, hierarchical clustering based routing protocol for smart home sensor network application. Proposed protocol perform dynamic cluster head selection based on multiple node characteristics like node residual energy, node distance from sink and node average distance from neighbour nodes. Cluster head distribution is even and results in enhanced network lifetime. Sensor nodes process the sense data using local on-board processors and omit the redundant data from transmission. In this manner, cooperative effort by sensor nodes save significant amount of node transmission energy. Elongated lifetime and reduced data traffic in network reduce data loss rates during transmission and result in high throughput. Wireless channel model and path loss model for indoor residential environment are used for protocol simulation. Simulation is carried using MATLAB tool and results are obtained in terms of network lifetime, stability period, throughput etc. Results, as compared with existing protocols, proves the efficiency of proposed protocol.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242140
Huibo Guo, G. Feng, Anping He, Jinzhao Wu
This paper proposes an asynchronous cycle circuit by providing Click element and joint module rather than clock-domain. The asynchronous mode of operation re-uses the simple asynchronous control protocols, takes full advantage of characteristics of Click, and commendably inherits the elasticity of the asynchronous micropipeline. The circuit in this paper has some individual coin. As a result, we can use it as a fixed and naturalized structure in application of VLSI asynchronous circuit design. Actually, when we transfer it to a strange circumstance, we only alter the output of counter which is the kernel of for-loop.
{"title":"An innovative implementation of asynchronous for-loop circuit with click micropipeline","authors":"Huibo Guo, G. Feng, Anping He, Jinzhao Wu","doi":"10.1109/ICAM.2017.8242140","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242140","url":null,"abstract":"This paper proposes an asynchronous cycle circuit by providing Click element and joint module rather than clock-domain. The asynchronous mode of operation re-uses the simple asynchronous control protocols, takes full advantage of characteristics of Click, and commendably inherits the elasticity of the asynchronous micropipeline. The circuit in this paper has some individual coin. As a result, we can use it as a fixed and naturalized structure in application of VLSI asynchronous circuit design. Actually, when we transfer it to a strange circumstance, we only alter the output of counter which is the kernel of for-loop.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131649946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242186
L. Wei, Duan Peng
The carrier frequency offset(CFO) in OFDM system is one of the key factors that affect the performance of wireless communication. Based on the analysis of the CFO estimation algorithm, this paper presents FPGA implementation scheme in the problem of OFDM fractional CFO estimation using pilot-based algorithm, including CFO estimation and CFO compensation. The circuit modules in the program were written in Verilog HDL. They are compiled, simulated and integrated under Xilinx programming software Vivado 2014.4. The simulation results show that the circuit module can accurately estimate and compensate the fractional CFO.
{"title":"Carrier frequency offset estimation and FPGA implementation in OFDM system","authors":"L. Wei, Duan Peng","doi":"10.1109/ICAM.2017.8242186","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242186","url":null,"abstract":"The carrier frequency offset(CFO) in OFDM system is one of the key factors that affect the performance of wireless communication. Based on the analysis of the CFO estimation algorithm, this paper presents FPGA implementation scheme in the problem of OFDM fractional CFO estimation using pilot-based algorithm, including CFO estimation and CFO compensation. The circuit modules in the program were written in Verilog HDL. They are compiled, simulated and integrated under Xilinx programming software Vivado 2014.4. The simulation results show that the circuit module can accurately estimate and compensate the fractional CFO.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242131
Parth Parekh, F. Yuan
This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.
{"title":"Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator","authors":"Parth Parekh, F. Yuan","doi":"10.1109/ICAM.2017.8242131","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242131","url":null,"abstract":"This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242156
Hongguang Zhang, Zhangwen Tang
A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.
{"title":"A 318 nA quiescent current 0–10mA output transient enhanced low-dropout regulator applied in energy harvest system","authors":"Hongguang Zhang, Zhangwen Tang","doi":"10.1109/ICAM.2017.8242156","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242156","url":null,"abstract":"A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242127
W. Lai, S. Jang, Meng-Yan Fang
This letter presents a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductors to reduce the die area. At the supply voltage of 1V, the divider's free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.
{"title":"Small die area capacitive cross-coupled injection-locked frequency divider","authors":"W. Lai, S. Jang, Meng-Yan Fang","doi":"10.1109/ICAM.2017.8242127","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242127","url":null,"abstract":"This letter presents a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductors to reduce the die area. At the supply voltage of 1V, the divider's free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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