Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242179
Y. Lo, Mu-Hsuan Chuang, Min-Hsin Cheng, Yuan-Hao Huang
This paper presents a particle filter processor IC for fingerprinting-based positioning in mobile communication systems. The proposed particle filter improves the positioning accuracy from algorithmic and architectural perspectives. For the algorithmic perspective, the proposed particle filter solves the bottleneck of large information exchange of particles by proposing a threshold IMH resampling method to raise the hardware utilization rate and reduce processing latency. For the architectural perspective, the proposed multiple-processing-element (multiple-PE) architecture based on central unit (CU) for threshold IMH resampling can further reduce the processing latency because no particle routing is needed in the PE-CU architecture. The proposed particle filter processor IC was designed and implemented by TSMC 0.18 μ m technology. The processor chip achieves 118MHz clock frequency with 1.48mm2 core area and 3.64mm2 chip area. The IC measurement results show that the proposed multiple-PE particle filter chip has two times hardware efficiency of one-PE particle filter.
{"title":"Multiple-PE particle filter processor IC for mobile positioning systems","authors":"Y. Lo, Mu-Hsuan Chuang, Min-Hsin Cheng, Yuan-Hao Huang","doi":"10.1109/ICAM.2017.8242179","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242179","url":null,"abstract":"This paper presents a particle filter processor IC for fingerprinting-based positioning in mobile communication systems. The proposed particle filter improves the positioning accuracy from algorithmic and architectural perspectives. For the algorithmic perspective, the proposed particle filter solves the bottleneck of large information exchange of particles by proposing a threshold IMH resampling method to raise the hardware utilization rate and reduce processing latency. For the architectural perspective, the proposed multiple-processing-element (multiple-PE) architecture based on central unit (CU) for threshold IMH resampling can further reduce the processing latency because no particle routing is needed in the PE-CU architecture. The proposed particle filter processor IC was designed and implemented by TSMC 0.18 μ m technology. The processor chip achieves 118MHz clock frequency with 1.48mm2 core area and 3.64mm2 chip area. The IC measurement results show that the proposed multiple-PE particle filter chip has two times hardware efficiency of one-PE particle filter.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127178096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242156
Hongguang Zhang, Zhangwen Tang
A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.
{"title":"A 318 nA quiescent current 0–10mA output transient enhanced low-dropout regulator applied in energy harvest system","authors":"Hongguang Zhang, Zhangwen Tang","doi":"10.1109/ICAM.2017.8242156","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242156","url":null,"abstract":"A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242131
Parth Parekh, F. Yuan
This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.
{"title":"Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator","authors":"Parth Parekh, F. Yuan","doi":"10.1109/ICAM.2017.8242131","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242131","url":null,"abstract":"This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242177
Meirong Wei, Yan Liu
As the air bearing flying height (a few nanometer levels) and the deformation of suspensions (micro-or millimeter level) run at two different scales, a dual-scale model for head disk interface (HDIs) has been proposed to analyze the unloading behavior of a subambient pressure slider. With the scheme developed, the unloading process can be simulated efficiently. The nonlinear vibrations of the air bearing forces and moments were described with analytical expression obtained from a surface fitting scheme. Combined with a 3 degree of freedom (DOF) suspension model whose parameters were estimated from a comprehensive FEM and experiments are applied to verify the value. The results from the FEM and the experiments are comparable and acceptable for simulations.
{"title":"An efficient scheme for analyzing unloading process","authors":"Meirong Wei, Yan Liu","doi":"10.1109/ICAM.2017.8242177","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242177","url":null,"abstract":"As the air bearing flying height (a few nanometer levels) and the deformation of suspensions (micro-or millimeter level) run at two different scales, a dual-scale model for head disk interface (HDIs) has been proposed to analyze the unloading behavior of a subambient pressure slider. With the scheme developed, the unloading process can be simulated efficiently. The nonlinear vibrations of the air bearing forces and moments were described with analytical expression obtained from a surface fitting scheme. Combined with a 3 degree of freedom (DOF) suspension model whose parameters were estimated from a comprehensive FEM and experiments are applied to verify the value. The results from the FEM and the experiments are comparable and acceptable for simulations.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128704598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242192
Y. Ban
This paper presents the design, trade-off of a very high bandwidth variable gain stage, and the practical limits during its implementation as a tunable gain cell in the high speed equalizer for next generation serial electrical / optical communication links. The variable gain stage presented in this work, achieves a bandwidth of above 50 GHz and a tunable gain range of 40 dB. With a very high input and output impedance, it could be used in the equalizer with the input data streams up to 80 Gb/s. The variable gain stage is designed in an 130 nm SiGe BiCMOS technology, with an active area of 0.04 mm2 and a power consumption of 30 mW from a 2.5 V supply.
{"title":"An 80 Gb/s SiGe BiCMOS fully differential variable gain stage in a digitally-controlled adaptive equalizer for high speed serial electrical communication","authors":"Y. Ban","doi":"10.1109/ICAM.2017.8242192","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242192","url":null,"abstract":"This paper presents the design, trade-off of a very high bandwidth variable gain stage, and the practical limits during its implementation as a tunable gain cell in the high speed equalizer for next generation serial electrical / optical communication links. The variable gain stage presented in this work, achieves a bandwidth of above 50 GHz and a tunable gain range of 40 dB. With a very high input and output impedance, it could be used in the equalizer with the input data streams up to 80 Gb/s. The variable gain stage is designed in an 130 nm SiGe BiCMOS technology, with an active area of 0.04 mm2 and a power consumption of 30 mW from a 2.5 V supply.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242161
B. Wang, Xiaodong Wang, Yulu Chen, Liwei Hou, Wei Xie, M. Pan
In this work, the device structure of the mesa-type GaAs:Te blocked-impurity-band detector was designed. The fabrication processes were presented briefly, and optimization of the fabrication processes was investigated. A 3-micron-thick SiO2 film was deposited as resist to substitute for photoresist in the 50-micron-deep mesa etching process. In addition, a bi-layer photoresist lithography technique was adopted to optimize the process of electrode fabrication. It is demonstrated that the device quality can be improved significantly after optimization.
{"title":"Optimization of fabrication processes of the mesa-type GaAs:Te blocked-impurity-band detector","authors":"B. Wang, Xiaodong Wang, Yulu Chen, Liwei Hou, Wei Xie, M. Pan","doi":"10.1109/ICAM.2017.8242161","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242161","url":null,"abstract":"In this work, the device structure of the mesa-type GaAs:Te blocked-impurity-band detector was designed. The fabrication processes were presented briefly, and optimization of the fabrication processes was investigated. A 3-micron-thick SiO2 film was deposited as resist to substitute for photoresist in the 50-micron-deep mesa etching process. In addition, a bi-layer photoresist lithography technique was adopted to optimize the process of electrode fabrication. It is demonstrated that the device quality can be improved significantly after optimization.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242194
Zhou Dali, Yang Jiapeng, Zhou Jun, Shen Ya
Through silicon vias (TSVs) are arranged to form a rectangular resonant cavity to improve performance of silicon based antenna in this paper. On the basis of fundamental theory of rectangular resonant cavity, the model of cavity made of through silicon vias is analyzed. Considering the size of millimeter-wave antenna, the three dimensions of cavity for mode TE101 is calculated. Applying the resonant cavity on coplanar waveguide (CPW) coupled slot antenna, a new frequency is generated which can lead to dual bands or a wider bandwidth. And the radiation gain can be improved by 1.9dB. So the application of through silicon via on improving performances of silicon based antenna is effective enough.
{"title":"Application of through silicon vias on millimeter-wave silicon based antenna","authors":"Zhou Dali, Yang Jiapeng, Zhou Jun, Shen Ya","doi":"10.1109/ICAM.2017.8242194","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242194","url":null,"abstract":"Through silicon vias (TSVs) are arranged to form a rectangular resonant cavity to improve performance of silicon based antenna in this paper. On the basis of fundamental theory of rectangular resonant cavity, the model of cavity made of through silicon vias is analyzed. Considering the size of millimeter-wave antenna, the three dimensions of cavity for mode TE101 is calculated. Applying the resonant cavity on coplanar waveguide (CPW) coupled slot antenna, a new frequency is generated which can lead to dual bands or a wider bandwidth. And the radiation gain can be improved by 1.9dB. So the application of through silicon via on improving performances of silicon based antenna is effective enough.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There will always have a greater residual stress in the processing process of the micromechanical gyroscopes straight elastic-beam. affecting the performance of micromechanical gyroscopes. According to the principle of stiffness equivalence, the original elastic-beam of the micromechanical gyroscope is improved to the beam of drive as the U-beam and sense as the carb-leg beam by the combination of theoretical analysis and finite element calculation. Compared with the ANSYS calculation results, The stiffness error and sensitivity of the driving beam are relatively small, the natural frequency error of the micromachined gyroscope is also within reasonable range; the interference mode differs from the working mode and The frequency of the drive and the sense match very well. The improved Micro-Electro-Mechanical System gyroscope satisfies the requirements of frequency matching and interference modal isolation. The improved design method provides theoretical guidance for the improvement and optimization of MEMS gyroscope.
{"title":"Optimized design of the micromechanical gyroscope's elastic beam","authors":"Chenqing Zhang, Shuying Hao, Huijie Li, Qichang Zhang","doi":"10.1109/ICAM.2017.8242160","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242160","url":null,"abstract":"There will always have a greater residual stress in the processing process of the micromechanical gyroscopes straight elastic-beam. affecting the performance of micromechanical gyroscopes. According to the principle of stiffness equivalence, the original elastic-beam of the micromechanical gyroscope is improved to the beam of drive as the U-beam and sense as the carb-leg beam by the combination of theoretical analysis and finite element calculation. Compared with the ANSYS calculation results, The stiffness error and sensitivity of the driving beam are relatively small, the natural frequency error of the micromachined gyroscope is also within reasonable range; the interference mode differs from the working mode and The frequency of the drive and the sense match very well. The improved Micro-Electro-Mechanical System gyroscope satisfies the requirements of frequency matching and interference modal isolation. The improved design method provides theoretical guidance for the improvement and optimization of MEMS gyroscope.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131265100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242168
Li Qi, Luo Le, Li Haiou, L. Shiwei, Zhang Fabi, Yang Nianjiong
In this paper, a new LDMOS on silicon-on-insulator (SOI) with homo-type fixed interface charges in the bottom of field oxide layer is proposed. The surface electric field can be improved by adding the fixed interface charges and optimizing the doping profile, which can effectively modulate electric field to obtain the optimization trade-off between the breakdown voltage and on-resistance. The numerical results indicate that the breakdown voltage of device proposed is increased by 40% and the on-resistance reduced by 44% in comparison to that of the conventional LDMOS.
{"title":"A new modulating electric field structure with homo-type fixed interface charges","authors":"Li Qi, Luo Le, Li Haiou, L. Shiwei, Zhang Fabi, Yang Nianjiong","doi":"10.1109/ICAM.2017.8242168","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242168","url":null,"abstract":"In this paper, a new LDMOS on silicon-on-insulator (SOI) with homo-type fixed interface charges in the bottom of field oxide layer is proposed. The surface electric field can be improved by adding the fixed interface charges and optimizing the doping profile, which can effectively modulate electric field to obtain the optimization trade-off between the breakdown voltage and on-resistance. The numerical results indicate that the breakdown voltage of device proposed is increased by 40% and the on-resistance reduced by 44% in comparison to that of the conventional LDMOS.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242162
Yulu Chen, B. Wang, Chuansheng Zhang, Liwei Hou, M. Pan, Xiaodong Wang
GaAs-based Blocked-Impurity-Band (BIB) detector, as a potential high-sensitive, low noise Terahertz (THz) detector, has been developed for the broad application in the area of THz security check and astronomy mission. In this work, GaAs:Si and GaAs:Te BIB detectors were fabricated. Their responsivity properties were measured at T=3.5K, under different biases and the same black body temperature of 1000K. The experimental results reveal that the GaAs:Si BIB device has a higher responsivity of 66 mA/W (Vbias=1V), about 5 times higher than that of GaAs:Te BIB device. This work demonstrates Si as a suitable choice of doping element for the absorption layer of GaAs based BIB detectors.
{"title":"Responsivity properties of GaAs based Blocked-Impurity-Band detectors","authors":"Yulu Chen, B. Wang, Chuansheng Zhang, Liwei Hou, M. Pan, Xiaodong Wang","doi":"10.1109/ICAM.2017.8242162","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242162","url":null,"abstract":"GaAs-based Blocked-Impurity-Band (BIB) detector, as a potential high-sensitive, low noise Terahertz (THz) detector, has been developed for the broad application in the area of THz security check and astronomy mission. In this work, GaAs:Si and GaAs:Te BIB detectors were fabricated. Their responsivity properties were measured at T=3.5K, under different biases and the same black body temperature of 1000K. The experimental results reveal that the GaAs:Si BIB device has a higher responsivity of 66 mA/W (Vbias=1V), about 5 times higher than that of GaAs:Te BIB device. This work demonstrates Si as a suitable choice of doping element for the absorption layer of GaAs based BIB detectors.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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