Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242189
Peter Wang
More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite very complicated debugging procedures and cause the problems and concerns of a multitude of engineering resources. The latest Marvell Ethernet PHY IC UVM verification platform integrating with the Marvell selected IP vendor's UVM library has been developed. A unique centralized-management methology block/architecture idea is brought in to build this UVM verification platform for the latest Marvell Ethernet PHY integrated circuit. All the eighty different test modes can be tested and verified in the same single UVM platform environment. This UVM verification platform environment significantly reduces the number of engineering resources needed to create and maintain the test cases. It also greatly saves debugging time and reduces chip development time. In the meanwhile, a novel random input stimulus controlled variables table idea is also implemented in this UVM verification platform to manage and improve the function coverage much more easily and efficiently.
如果使用传统的工业验证方法，则需要创建和维护80多个不同的测试环境来调试Marvell以太网PHY芯片。这很容易引发非常复杂的调试过程，并引起大量工程资源的问题和关注。最新的Marvell以太网PHY IC UVM验证平台集成了Marvell选择的IP供应商的UVM库。为最新的Marvell以太网PHY集成电路构建UVM验证平台，引入了独特的集中式管理方法块/体系结构思想。所有80种不同的测试模式都可以在同一个UVM平台环境中进行测试和验证。这个UVM验证平台环境显著地减少了创建和维护测试用例所需的工程资源的数量。大大节省了调试时间，缩短了芯片开发时间。同时，在UVM验证平台中还采用了一种新颖的随机输入刺激控制变量表的思想，使UVM验证平台更容易有效地管理和改进函数覆盖。
{"title":"A unique centralized-management methodology block/architecture and a novel random input stimulus controlled variable table implementation for the latest marvell ethernet PHY UVM verification platform","authors":"Peter Wang","doi":"10.1109/ICAM.2017.8242189","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242189","url":null,"abstract":"More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite very complicated debugging procedures and cause the problems and concerns of a multitude of engineering resources. The latest Marvell Ethernet PHY IC UVM verification platform integrating with the Marvell selected IP vendor's UVM library has been developed. A unique centralized-management methology block/architecture idea is brought in to build this UVM verification platform for the latest Marvell Ethernet PHY integrated circuit. All the eighty different test modes can be tested and verified in the same single UVM platform environment. This UVM verification platform environment significantly reduces the number of engineering resources needed to create and maintain the test cases. It also greatly saves debugging time and reduces chip development time. In the meanwhile, a novel random input stimulus controlled variables table idea is also implemented in this UVM verification platform to manage and improve the function coverage much more easily and efficiently.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127094968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242150
Matthew Dolan, F. Yuan
This paper presents a low-power adaptive edge decision feedback equalizer (DFE) for 10 giga-bits-per-second (Gbps) serial links with 4 PAM (pulse-amplitude-modulation) signaling. Optimal tap coefficients are obtained adaptively using a sign-sign least-mean-square (SS-LMS) algorithm that minimizes the jitter of equalized data. Low-voltage-differential-signaling (LVDS) tap generators that double DFE strength without increasing power consumption are used. Power reduction is also achieved by only activating the tap generator corresponding to the incoming data and sharing slicers for determining data state, the sign of data jitter, and bang-bang phase detection. A frequency locked-loop locked to an external frequency reference and a bang-bang phase-locked loop locked to the edge of equalized data, both sharing the same active inductor ring oscillator with separate frequency and phase tunings, are employed for clock recovery. The effectiveness of the proposed edge DFE is validated using a 10 Gbps 4PAM serial link designed in a 65 nm CMOS technology over a wire channel with 12 dB loss at baud-rate frequency. Simulation results demonstrated that the proposed adaptive edge DFE is capable of achieving 46% vertical opening and 60% horizontal eye-opening while consuming 26.24 mW.
{"title":"Low-power adaptive edge decision feedback equalizer for serial links with 4PAM signaling","authors":"Matthew Dolan, F. Yuan","doi":"10.1109/ICAM.2017.8242150","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242150","url":null,"abstract":"This paper presents a low-power adaptive edge decision feedback equalizer (DFE) for 10 giga-bits-per-second (Gbps) serial links with 4 PAM (pulse-amplitude-modulation) signaling. Optimal tap coefficients are obtained adaptively using a sign-sign least-mean-square (SS-LMS) algorithm that minimizes the jitter of equalized data. Low-voltage-differential-signaling (LVDS) tap generators that double DFE strength without increasing power consumption are used. Power reduction is also achieved by only activating the tap generator corresponding to the incoming data and sharing slicers for determining data state, the sign of data jitter, and bang-bang phase detection. A frequency locked-loop locked to an external frequency reference and a bang-bang phase-locked loop locked to the edge of equalized data, both sharing the same active inductor ring oscillator with separate frequency and phase tunings, are employed for clock recovery. The effectiveness of the proposed edge DFE is validated using a 10 Gbps 4PAM serial link designed in a 65 nm CMOS technology over a wire channel with 12 dB loss at baud-rate frequency. Simulation results demonstrated that the proposed adaptive edge DFE is capable of achieving 46% vertical opening and 60% horizontal eye-opening while consuming 26.24 mW.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242145
Xin Chuan, Yingjian Yan, Yi-lun Zhang
The cryptographic chip is widely used in government, military, finance, business and other fields, so the requirement of security is very high. The globalization of the integrated circuit supply chains has promoted the rapid development of the industry, but the chip is also vulnerable to malicious modified by the attacker, namely hardware Trojan implanted. The paper proposed a hardware Trojan efficient triggering method in AES cryptographic circuit. The method generated the test vector set by using the proposed optimal expand algorithm, which was used for detecting the AES cryptographic circuit to judge whether AES circuit exist hardware Trojans. Experiment results indicate that the method proposed in this paper can effectively trigger the hardware Trojan, increase the number of hardware Trojans triggered, and improve the trigger efficiency of the hardware Trojan. Thus, it is an efficient triggering method for detecting combinational hardware Trojans in AES Cryptographic circuit.
{"title":"An efficient triggering method of hardware Trojan in AES cryptographic circuit","authors":"Xin Chuan, Yingjian Yan, Yi-lun Zhang","doi":"10.1109/ICAM.2017.8242145","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242145","url":null,"abstract":"The cryptographic chip is widely used in government, military, finance, business and other fields, so the requirement of security is very high. The globalization of the integrated circuit supply chains has promoted the rapid development of the industry, but the chip is also vulnerable to malicious modified by the attacker, namely hardware Trojan implanted. The paper proposed a hardware Trojan efficient triggering method in AES cryptographic circuit. The method generated the test vector set by using the proposed optimal expand algorithm, which was used for detecting the AES cryptographic circuit to judge whether AES circuit exist hardware Trojans. Experiment results indicate that the method proposed in this paper can effectively trigger the hardware Trojan, increase the number of hardware Trojans triggered, and improve the trigger efficiency of the hardware Trojan. Thus, it is an efficient triggering method for detecting combinational hardware Trojans in AES Cryptographic circuit.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123429852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242158
Dongrong Zhang, Xiaoxiao Wang
Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the worst-case timing slack in the DUT. Then the chip can be binned to the corresponding speed bin according to the test frequency and slack information. The proposed sensor has been implemented on various ITC benchmarks and the FGU of OpenSPARCT2 core on 28nm technology node. Experiment result shows that the proposed sensor can accurately monitor the slack of the DUT with low test time. At the same time, the proposed sensor is all-digital, which requires low design effort, and less than 1% area overhead for large benchmarks.
{"title":"An on-chip binning sensor for low-cost and accurate speed binning","authors":"Dongrong Zhang, Xiaoxiao Wang","doi":"10.1109/ICAM.2017.8242158","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242158","url":null,"abstract":"Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the worst-case timing slack in the DUT. Then the chip can be binned to the corresponding speed bin according to the test frequency and slack information. The proposed sensor has been implemented on various ITC benchmarks and the FGU of OpenSPARCT2 core on 28nm technology node. Experiment result shows that the proposed sensor can accurately monitor the slack of the DUT with low test time. At the same time, the proposed sensor is all-digital, which requires low design effort, and less than 1% area overhead for large benchmarks.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122922380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242173
W. Wang, Lin Yan, N. Zhang, Hua Yu, Wen-biao Tao
Among power generation, transmission and use, distribution is an extremely important link. The distribution system includes a transformer and a variety of high and low voltage electrical equipment, the circuit breaker is a large amount of electrical appliances. The circuit breaker can be used to distribute electric energy, the asynchronous motor is not frequently started and the power line and motor is protected. The utility model can automatically cut off the circuit when the overload, short circuit and under voltage fault occur, and the utility model is equivalent to the combination of the fuse type switch and the over low thermal relay. In this paper, the problem of the failure of Qixian 220kV circuit breaker is analyzed. It is concluded that the gap of the switch electromagnet in the circuit breaker is changed and the hammer and trigger gap is too large. After the operation of the gate and non full phase protection, the top cannot trigger, thus unable to brake the conclusion.
{"title":"Reason analysis and countermeasure of opening failure of 220 kV circuit breaker","authors":"W. Wang, Lin Yan, N. Zhang, Hua Yu, Wen-biao Tao","doi":"10.1109/ICAM.2017.8242173","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242173","url":null,"abstract":"Among power generation, transmission and use, distribution is an extremely important link. The distribution system includes a transformer and a variety of high and low voltage electrical equipment, the circuit breaker is a large amount of electrical appliances. The circuit breaker can be used to distribute electric energy, the asynchronous motor is not frequently started and the power line and motor is protected. The utility model can automatically cut off the circuit when the overload, short circuit and under voltage fault occur, and the utility model is equivalent to the combination of the fuse type switch and the over low thermal relay. In this paper, the problem of the failure of Qixian 220kV circuit breaker is analyzed. It is concluded that the gap of the switch electromagnet in the circuit breaker is changed and the hammer and trigger gap is too large. After the operation of the gate and non full phase protection, the top cannot trigger, thus unable to brake the conclusion.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242172
Wei Wang, N. Zhang, Xing-Ting Liu, Yu Han, Wen-biao Tao
In order to solve the problems of power transformer such as the fault can be reflected by different characteristic signal from different side and complexity of fault reason and phenomenon, a synthetic diagnosis method using multi-neural network and evidence theory for transformer fault diagnosis is presented. Various kinds of data are dealt by using neural network's excellent abilities of learning, memory and recognition. Integrating data fusion methods, neural network's preliminary results are diagnosed by evidence theory. It has been shown by experiments that the accuracy rate of transformer fault diagnosis is up to 73%.
{"title":"Study on fault diagnosis method of transformer using multi-neural network and evidence theory","authors":"Wei Wang, N. Zhang, Xing-Ting Liu, Yu Han, Wen-biao Tao","doi":"10.1109/ICAM.2017.8242172","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242172","url":null,"abstract":"In order to solve the problems of power transformer such as the fault can be reflected by different characteristic signal from different side and complexity of fault reason and phenomenon, a synthetic diagnosis method using multi-neural network and evidence theory for transformer fault diagnosis is presented. Various kinds of data are dealt by using neural network's excellent abilities of learning, memory and recognition. Integrating data fusion methods, neural network's preliminary results are diagnosed by evidence theory. It has been shown by experiments that the accuracy rate of transformer fault diagnosis is up to 73%.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242165
Peng Zhang, Changchun Zhang, Jingjian Zhang, Yi Zhang, Ying Zhang, Xincun Ji
A 25–28Gb/s full-rate reference-less CDR is presented and designed in a standard 0.13μm SiGe BiCMOS process, which can be applicable to nearly all classical 100G communication protocols by multi-channel configuration. It consists mainly of a full-rate phase frequency detector, a quadrature voltage control oscillator and two voltage to current convertors with loop filters. A dual-loop topology is adopted in order for a wide frequency acquisition range and an excellent jitter performance. Simulation results show that the proposed CDR operates properly at a data rate of 25–28Gb/s. When a 25Gb/s PRBS data is applied, the jitters of the recovered clock and data are 0.34ps and 2.8ps, respectively, with 91 mA current consumption from a single power supply of 1.7V.
{"title":"A 25–28Gb/s PLL-based full-rate reference-less CDR in 0.13μm SiGe BiCMOS","authors":"Peng Zhang, Changchun Zhang, Jingjian Zhang, Yi Zhang, Ying Zhang, Xincun Ji","doi":"10.1109/ICAM.2017.8242165","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242165","url":null,"abstract":"A 25–28Gb/s full-rate reference-less CDR is presented and designed in a standard 0.13μm SiGe BiCMOS process, which can be applicable to nearly all classical 100G communication protocols by multi-channel configuration. It consists mainly of a full-rate phase frequency detector, a quadrature voltage control oscillator and two voltage to current convertors with loop filters. A dual-loop topology is adopted in order for a wide frequency acquisition range and an excellent jitter performance. Simulation results show that the proposed CDR operates properly at a data rate of 25–28Gb/s. When a 25Gb/s PRBS data is applied, the jitters of the recovered clock and data are 0.34ps and 2.8ps, respectively, with 91 mA current consumption from a single power supply of 1.7V.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242195
Y. Lyu, Wei Zou, Shuang Chen
This paper presents a dual-channel GNSS receiver covering GPS and Beidou on a single chip in 0.13μm CMOS process. The receiver incorporates one reconfigurable RF front-end and two separate IF signal channels with one single fractional-N frequency synthesizer by using a ring voltage-controlled oscillator. This architecture supports an external active or passive antenna and provides the benefits of low cost and power consumption. An optional SAW filter can be inserted between the low-noise amplifier and mixer, providing out-of-band interference rejection in high performance applications. The receiver exhibits maximum gain of 95 dB and noise figures of 3.5 and 3.7 dB for L1 and B1 bands, respectively. The total power consumption of the receiver is 30 mW with a 1.2-V supply while occupying a 1.7mm2 die area including the ESD I/O pads. The one presented here is the smallest dual-channel GNSS receiver reported so far.
{"title":"A dual-channel GNSS receiver for GPS and Beidou applications","authors":"Y. Lyu, Wei Zou, Shuang Chen","doi":"10.1109/ICAM.2017.8242195","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242195","url":null,"abstract":"This paper presents a dual-channel GNSS receiver covering GPS and Beidou on a single chip in 0.13μm CMOS process. The receiver incorporates one reconfigurable RF front-end and two separate IF signal channels with one single fractional-N frequency synthesizer by using a ring voltage-controlled oscillator. This architecture supports an external active or passive antenna and provides the benefits of low cost and power consumption. An optional SAW filter can be inserted between the low-noise amplifier and mixer, providing out-of-band interference rejection in high performance applications. The receiver exhibits maximum gain of 95 dB and noise figures of 3.5 and 3.7 dB for L1 and B1 bands, respectively. The total power consumption of the receiver is 30 mW with a 1.2-V supply while occupying a 1.7mm2 die area including the ESD I/O pads. The one presented here is the smallest dual-channel GNSS receiver reported so far.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130697150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242146
Hu Jianfei, Guo Jinjin
Microsystem technology based on micro machining technology and integrated circuit technology has the advantages of miniaturization, integration, intelligence, low cost, high performance, mass production and so on. An overview of the composition and working principle of the microsystem, it introduces the development history of micro system technology, current situation and industrial distribution pattern, focuses on several important micro machining technology, analyses surface processing technology, bonding, LIGA technology, nano imprint technology and high aspect ratio manufacturing technology principle, characteristics and manufacturing process, explains the study of microsystem CAD, and combines with the current application of micro devices of the advantages of technology, which has a certain value for the study of microsystem technology.
{"title":"The development of microsystem technology","authors":"Hu Jianfei, Guo Jinjin","doi":"10.1109/ICAM.2017.8242146","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242146","url":null,"abstract":"Microsystem technology based on micro machining technology and integrated circuit technology has the advantages of miniaturization, integration, intelligence, low cost, high performance, mass production and so on. An overview of the composition and working principle of the microsystem, it introduces the development history of micro system technology, current situation and industrial distribution pattern, focuses on several important micro machining technology, analyses surface processing technology, bonding, LIGA technology, nano imprint technology and high aspect ratio manufacturing technology principle, characteristics and manufacturing process, explains the study of microsystem CAD, and combines with the current application of micro devices of the advantages of technology, which has a certain value for the study of microsystem technology.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126785234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242154
Shulin Liu, Chaoying Wang, Qianqian Wang, Shitong Tao
A kind of LLC resonant converter with voltage-doubling rectifier technology is studied in this paper. The converter has not only a general LLC half-bridge resonant converter being easy to obtain ZVS for primary side switches and ZCS for secondary side diodes, a high efficiency of this topology, but also advantages that the transformer structure is simple in which one winding is involved on its secondary side, voltage stress of two output capacitors are half of output voltage and extra voltage balance circuit is excluded. Voltage and current stress of two output rectifier diodes are equal to output voltage and current, respectively. The working principle of the converter and the soft switching process are analyzed in detail in this paper. Simulation and experiment results are in positive to the analysis showing the feasibility of the proposed method.
{"title":"Analysis and simulation of LLC resonant converter with voltage-doubling rectifier","authors":"Shulin Liu, Chaoying Wang, Qianqian Wang, Shitong Tao","doi":"10.1109/ICAM.2017.8242154","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242154","url":null,"abstract":"A kind of LLC resonant converter with voltage-doubling rectifier technology is studied in this paper. The converter has not only a general LLC half-bridge resonant converter being easy to obtain ZVS for primary side switches and ZCS for secondary side diodes, a high efficiency of this topology, but also advantages that the transformer structure is simple in which one winding is involved on its secondary side, voltage stress of two output capacitors are half of output voltage and extra voltage balance circuit is excluded. Voltage and current stress of two output rectifier diodes are equal to output voltage and current, respectively. The working principle of the converter and the soft switching process are analyzed in detail in this paper. Simulation and experiment results are in positive to the analysis showing the feasibility of the proposed method.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130244550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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