Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242176
A. Jurenoks, L. Novickis
Energy efficiency is at the heart of the EU's Europe 2020 Strategy for smart, sustainable and inclusive growth and of the transition to a resource efficient economy. Energy efficiency is one of the most cost effective ways to enhance security of energy supply, and to reduce emissions of greenhouse gases and other pollutants. Nowadays intelligent home energy management is an approach to build centralized systems that deliver application functionality as services to end-consumer applications. The objective of this work is to develop a stable, robust, and optimal switching supervisory controller for the smart house that will minimize the use of heating energy reducing the impact on the heating system while satisfying the temperature rules for the user. This paper describes a central heating system control method implemented by using the fuzzy control system designed. Author concentrates on the basic operation of such systems and present findings from the design process and initial tests.
{"title":"Fuzzy logic control method for autonomous heating system in energy efficient homes","authors":"A. Jurenoks, L. Novickis","doi":"10.1109/ICAM.2017.8242176","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242176","url":null,"abstract":"Energy efficiency is at the heart of the EU's Europe 2020 Strategy for smart, sustainable and inclusive growth and of the transition to a resource efficient economy. Energy efficiency is one of the most cost effective ways to enhance security of energy supply, and to reduce emissions of greenhouse gases and other pollutants. Nowadays intelligent home energy management is an approach to build centralized systems that deliver application functionality as services to end-consumer applications. The objective of this work is to develop a stable, robust, and optimal switching supervisory controller for the smart house that will minimize the use of heating energy reducing the impact on the heating system while satisfying the temperature rules for the user. This paper describes a central heating system control method implemented by using the fuzzy control system designed. Author concentrates on the basic operation of such systems and present findings from the design process and initial tests.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129989203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242137
Yang Cao, Wei Zhang, Jun Fu, Nianhong Liu, Quan Wang, Linlin Liu
In this paper, on-wafer de-embedding methods for passive components are evaluated for millimeter wave integrated circuit (MMW IC) design support. An electromagnetic simulation aided de-embedding (EMSAD) technique is proposed. The electromagnetic model is calibrated by matching the open-short de-embedded measurement at relatively lower frequencies. A set of Ground Coplanar Waveguide (GCPW) test structures fabricated on HLMC 40nm RF CMOS process are used for the investigation. The results of the proposed technique are used as reference for de-embedding of passive components at millimeter wave frequencies. As a result, the open-short de-embedding method is found to lose its accuracy above 60GHz in this work.
{"title":"De-embedding and electromagnetic simulation calibration of on-wafer passive devices for millimeter wave integrated circuit design support","authors":"Yang Cao, Wei Zhang, Jun Fu, Nianhong Liu, Quan Wang, Linlin Liu","doi":"10.1109/ICAM.2017.8242137","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242137","url":null,"abstract":"In this paper, on-wafer de-embedding methods for passive components are evaluated for millimeter wave integrated circuit (MMW IC) design support. An electromagnetic simulation aided de-embedding (EMSAD) technique is proposed. The electromagnetic model is calibrated by matching the open-short de-embedded measurement at relatively lower frequencies. A set of Ground Coplanar Waveguide (GCPW) test structures fabricated on HLMC 40nm RF CMOS process are used for the investigation. The results of the proposed technique are used as reference for de-embedding of passive components at millimeter wave frequencies. As a result, the open-short de-embedding method is found to lose its accuracy above 60GHz in this work.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242188
Najam Muhammad Amin, Farrukh Shahid, Lianfeng Shen, Zhigong Wang, H. Rasheed, Burhan Ahmed
An active quasi-circulator (AQC) operating at a frequency band ranging from 1.2–3.8 GHz is designed in a 0.18-μm CMOS process. To improve the isolation between AQC's ports common-gate (CG), common-source (CS) and common-drain (CD) configurations have been employed. To particularly improve the transmitter-to-receiver port isolation, out-of-phase cancellation is employed by making the transmit signal traverse from two different out-of-phase paths. A figure-of-merit (FOM) has also been proposed to enable a fair comparison of different published works. For the proposed design, simulation results indicate >11 dB return losses (RL) for all three AQC ports. The AQC has maximum insertion losses (IL) of −10 dB and −7.8 dB between transmitter-to-antenna and antenna-to-receiver ports respectively. With a power dissipation of 40 mW, the proposed AQC displays a transmit-receive isolation of >30 dB and a high FOM of 1.948 GHz × mW.
{"title":"1.2–3.8 GHz active quasi-circulator with >30 dB transmit-receive isolation","authors":"Najam Muhammad Amin, Farrukh Shahid, Lianfeng Shen, Zhigong Wang, H. Rasheed, Burhan Ahmed","doi":"10.1109/ICAM.2017.8242188","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242188","url":null,"abstract":"An active quasi-circulator (AQC) operating at a frequency band ranging from 1.2–3.8 GHz is designed in a 0.18-μm CMOS process. To improve the isolation between AQC's ports common-gate (CG), common-source (CS) and common-drain (CD) configurations have been employed. To particularly improve the transmitter-to-receiver port isolation, out-of-phase cancellation is employed by making the transmit signal traverse from two different out-of-phase paths. A figure-of-merit (FOM) has also been proposed to enable a fair comparison of different published works. For the proposed design, simulation results indicate >11 dB return losses (RL) for all three AQC ports. The AQC has maximum insertion losses (IL) of −10 dB and −7.8 dB between transmitter-to-antenna and antenna-to-receiver ports respectively. With a power dissipation of 40 mW, the proposed AQC displays a transmit-receive isolation of >30 dB and a high FOM of 1.948 GHz × mW.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129899593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.
{"title":"A filterless digital audio class-D amplifier based on grow-left double-edge pulse width modulation","authors":"Xiaolei Chen, Haipeng Qu, Zeqi Yu, Chunyang Zhang, Enguang Zhang","doi":"10.1109/ICAM.2017.8242175","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242175","url":null,"abstract":"A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117055881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242141
Yinan Zhang, Xiaohong Peng
This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.
{"title":"A partition level floorplan method based on data flow analysis for physical design of digital IC","authors":"Yinan Zhang, Xiaohong Peng","doi":"10.1109/ICAM.2017.8242141","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242141","url":null,"abstract":"This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242153
Yao Lu, YanXu Zhu, Hui Song, Lailong Li, Dong Shi
In order to compensate for the effects of supply voltage, process and temperature on the oscillator frequency, we design a ring oscillator with digital calibration. By comparing the frequency deviation between the ring oscillator and the external reference clock source, adjusting the state of the control word, and then changing the number of resistors in the analog circuit to adjust the output frequency of the ring oscillator, so as to compensate the output frequency deviation. Firstly, we analyze the analog circuit and digital circuit, and then get the result of simulation, finally carry out the layout design. Simulation results show that by digital calibration, the output frequency can be adjusted up or down by 30%, so that the deviation can be compensated to a great extent.
{"title":"The design of a ring oscillator with digital calibration","authors":"Yao Lu, YanXu Zhu, Hui Song, Lailong Li, Dong Shi","doi":"10.1109/ICAM.2017.8242153","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242153","url":null,"abstract":"In order to compensate for the effects of supply voltage, process and temperature on the oscillator frequency, we design a ring oscillator with digital calibration. By comparing the frequency deviation between the ring oscillator and the external reference clock source, adjusting the state of the control word, and then changing the number of resistors in the analog circuit to adjust the output frequency of the ring oscillator, so as to compensate the output frequency deviation. Firstly, we analyze the analog circuit and digital circuit, and then get the result of simulation, finally carry out the layout design. Simulation results show that by digital calibration, the output frequency can be adjusted up or down by 30%, so that the deviation can be compensated to a great extent.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126325679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242167
Yi Liu, Jianmin Cao
A simulation method of non-uniform interface charges in pMOSFETs was presented in this paper. By using the 2D device simulation software, it increases the non-uniform interface charges array and calculation module. Bonded with the device negative bias temperature instability NBTI (Negative Bias Temperature Instability) degeneration model, the pure bias NBTI (Pure Drain Bias NBTI) degradation impact on pMOS device threshold voltage was calculated and analyzed. The results show that the pure bias NBTI degradation is smaller than typical NBTI degradation in the beginning of a period of time of the stress, but after prolonged stress, the degradation of both is the same. In the test window, the pure bias NBTI degradation exponent changes along with the gate voltage. These methods and conclusions are helpful for the further analysis of the mechanism of pure bias NBTI degradation and related reliability issues.
本文提出了一种模拟pmosfet非均匀界面电荷的方法。利用二维器件仿真软件，增加了非均匀界面电荷阵列和计算模块。结合器件负偏置温度不稳定性NBTI (negative bias temperature instability)退化模型，计算分析了纯偏置NBTI (pure Drain bias NBTI)退化对pMOS器件阈值电压的影响。结果表明:纯偏置NBTI在一段时间内的降解比典型NBTI的降解要小，但在长时间的应力作用后，两者的降解基本一致;在测试窗口内，纯偏置NBTI降解指数随栅极电压变化。这些方法和结论有助于进一步分析纯偏置NBTI退化的机理和相关的可靠性问题。
{"title":"Numerical simulation of non-uniform interface charge caused by pure bias NBTI degradation in pMOSFETs","authors":"Yi Liu, Jianmin Cao","doi":"10.1109/ICAM.2017.8242167","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242167","url":null,"abstract":"A simulation method of non-uniform interface charges in pMOSFETs was presented in this paper. By using the 2D device simulation software, it increases the non-uniform interface charges array and calculation module. Bonded with the device negative bias temperature instability NBTI (Negative Bias Temperature Instability) degeneration model, the pure bias NBTI (Pure Drain Bias NBTI) degradation impact on pMOS device threshold voltage was calculated and analyzed. The results show that the pure bias NBTI degradation is smaller than typical NBTI degradation in the beginning of a period of time of the stress, but after prolonged stress, the degradation of both is the same. In the test window, the pure bias NBTI degradation exponent changes along with the gate voltage. These methods and conclusions are helpful for the further analysis of the mechanism of pure bias NBTI degradation and related reliability issues.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129125709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242135
Hengzhen Li, Z. Ming, Bangfa Chen, Zhang Sihan, Dong Di
In order to solve the safety problem about person and equipment caused by the dispersed current during the transmission tower being lightning struck, it is necessary to study the characteristics of the dispersed current. In this paper, the dispersed current model of the tower grounding device is established in COMSOL. The distribution of the dispersed current around the tower is discussed, and the location of the test points is determined according to the simulation. Then the field experiment platform based on the lightning current generator and the dispersed current measurement system is established to measure the dispersed current. The influence of the grounding device structure on the dispersed current characteristics is discussed with the experimental data and simulation analysis. The results show that the field experiment platform can accurately measure the current density in the ground and the simulation results are consistent with the measured data. Therefore, the simulation model can be used in further study of the dispersed current situation around the grounding device. Far from the grounding electrode 4–5m, the current density decreased about 50%, 7–8m decreased by about 75%. The current density near the ground device decreases with the extension of the horizontal ground electrode, and the closer the distance to the grounding device is, the more obvious the trend is.
{"title":"Study on the distribution characteristics of the scattered current during the transmission tower being lightning struck","authors":"Hengzhen Li, Z. Ming, Bangfa Chen, Zhang Sihan, Dong Di","doi":"10.1109/ICAM.2017.8242135","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242135","url":null,"abstract":"In order to solve the safety problem about person and equipment caused by the dispersed current during the transmission tower being lightning struck, it is necessary to study the characteristics of the dispersed current. In this paper, the dispersed current model of the tower grounding device is established in COMSOL. The distribution of the dispersed current around the tower is discussed, and the location of the test points is determined according to the simulation. Then the field experiment platform based on the lightning current generator and the dispersed current measurement system is established to measure the dispersed current. The influence of the grounding device structure on the dispersed current characteristics is discussed with the experimental data and simulation analysis. The results show that the field experiment platform can accurately measure the current density in the ground and the simulation results are consistent with the measured data. Therefore, the simulation model can be used in further study of the dispersed current situation around the grounding device. Far from the grounding electrode 4–5m, the current density decreased about 50%, 7–8m decreased by about 75%. The current density near the ground device decreases with the extension of the horizontal ground electrode, and the closer the distance to the grounding device is, the more obvious the trend is.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134452969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242128
Qi-Cheng Ye, Youtao Zhang, Xiaopeng Li, Yi Zhang
In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.
本文介绍了一种采用280GHz fT 0.7um InP HBT技术的12bit 10GSps电流转向数模转换器(DAC)。DAC核心以双采样方式工作，从而将最大时钟频率降低一半。双采样开关被分离，以减少符号间的干扰。采用改进的电流转向开关结构，提高了高频动态性能。仿真结果表明，该芯片的DNL/INL分别为0.7/0.8 LSB。低频时的SFDR在71dBc以上，奈奎斯特频率以下的最低SFDR在46.96dBc以上。
{"title":"A 12-bit 10GSps ultra high speed DAC in InP HBT technology","authors":"Qi-Cheng Ye, Youtao Zhang, Xiaopeng Li, Yi Zhang","doi":"10.1109/ICAM.2017.8242128","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242128","url":null,"abstract":"In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123692081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242151
S. A. Imam, Aijaz M. Zaidi, A. Choudhary, B. Kanaujia, M. Singh
A new quad band quadrature branch line coupler (BLC) has been presented in this paper. The proposed BLC has been designed with the help of the T shaped coupled line sections, quad band impedance inverter. The BLC has been designed using Advanced Design System (ADS) software for f1 = 0.66 GHz, f2 = 1.52 GHz, f3 = 2.57 GHz and f4 = 3.44 GHz operating frequencies. The Rogers 5870 substrate has been selected for the BLC design. The BLC's S-parameters characteristics including insertion loss, isolation loss, quadrature phase and equal power division have been achieved with 0.58 dB maximum amplitude imbalance and 4.33° maximum phase deviation while preserved the <-10dB return loss and isolation loss at four frequency bands. The simulated results of the BLC verified the theoretical results of the BLC at four frequency bands.
{"title":"A quad band quadrature branch line coupler using coupled line sections","authors":"S. A. Imam, Aijaz M. Zaidi, A. Choudhary, B. Kanaujia, M. Singh","doi":"10.1109/ICAM.2017.8242151","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242151","url":null,"abstract":"A new quad band quadrature branch line coupler (BLC) has been presented in this paper. The proposed BLC has been designed with the help of the T shaped coupled line sections, quad band impedance inverter. The BLC has been designed using Advanced Design System (ADS) software for f1 = 0.66 GHz, f2 = 1.52 GHz, f3 = 2.57 GHz and f4 = 3.44 GHz operating frequencies. The Rogers 5870 substrate has been selected for the BLC design. The BLC's S-parameters characteristics including insertion loss, isolation loss, quadrature phase and equal power division have been achieved with 0.58 dB maximum amplitude imbalance and 4.33° maximum phase deviation while preserved the <-10dB return loss and isolation loss at four frequency bands. The simulated results of the BLC verified the theoretical results of the BLC at four frequency bands.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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