Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242182
Yan Siyi, Zong Zhulin
Objective: The stepped-frequency chirp signal is a wide band radar signal which can obtain high resolution range profiles. But when it come across phase discordance, the energy of target cannot be accumulated and the corresponding radar system cannot detect any targets. In order to resolve the effect of phase uncertainties, an novel phase error compensation method is proposed in this paper. Method: Research into the phase characteristic of a group of stepped-frequency chirp signals using the FFT algorithm, the phase difference between each received stepped-frequency chirp signal and the transmitted signal can be calculated and the phase compensation is carried out by using a compensator and a look-up table. Result & Conclusion: The sampled stepped-frequency is used to simulate the proposed algorithm, the phase error is compensated and the high resolution range profiles can be easily obtained. The validity and the feasible of the algorithm are verified through the simulations.
{"title":"An implementation of phase error compensation algorithm","authors":"Yan Siyi, Zong Zhulin","doi":"10.1109/ICAM.2017.8242182","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242182","url":null,"abstract":"Objective: The stepped-frequency chirp signal is a wide band radar signal which can obtain high resolution range profiles. But when it come across phase discordance, the energy of target cannot be accumulated and the corresponding radar system cannot detect any targets. In order to resolve the effect of phase uncertainties, an novel phase error compensation method is proposed in this paper. Method: Research into the phase characteristic of a group of stepped-frequency chirp signals using the FFT algorithm, the phase difference between each received stepped-frequency chirp signal and the transmitted signal can be calculated and the phase compensation is carried out by using a compensator and a look-up table. Result & Conclusion: The sampled stepped-frequency is used to simulate the proposed algorithm, the phase error is compensated and the high resolution range profiles can be easily obtained. The validity and the feasible of the algorithm are verified through the simulations.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125650413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242128
Qi-Cheng Ye, Youtao Zhang, Xiaopeng Li, Yi Zhang
In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.
本文介绍了一种采用280GHz fT 0.7um InP HBT技术的12bit 10GSps电流转向数模转换器(DAC)。DAC核心以双采样方式工作，从而将最大时钟频率降低一半。双采样开关被分离，以减少符号间的干扰。采用改进的电流转向开关结构，提高了高频动态性能。仿真结果表明，该芯片的DNL/INL分别为0.7/0.8 LSB。低频时的SFDR在71dBc以上，奈奎斯特频率以下的最低SFDR在46.96dBc以上。
{"title":"A 12-bit 10GSps ultra high speed DAC in InP HBT technology","authors":"Qi-Cheng Ye, Youtao Zhang, Xiaopeng Li, Yi Zhang","doi":"10.1109/ICAM.2017.8242128","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242128","url":null,"abstract":"In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123692081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242151
S. A. Imam, Aijaz M. Zaidi, A. Choudhary, B. Kanaujia, M. Singh
A new quad band quadrature branch line coupler (BLC) has been presented in this paper. The proposed BLC has been designed with the help of the T shaped coupled line sections, quad band impedance inverter. The BLC has been designed using Advanced Design System (ADS) software for f1 = 0.66 GHz, f2 = 1.52 GHz, f3 = 2.57 GHz and f4 = 3.44 GHz operating frequencies. The Rogers 5870 substrate has been selected for the BLC design. The BLC's S-parameters characteristics including insertion loss, isolation loss, quadrature phase and equal power division have been achieved with 0.58 dB maximum amplitude imbalance and 4.33° maximum phase deviation while preserved the <-10dB return loss and isolation loss at four frequency bands. The simulated results of the BLC verified the theoretical results of the BLC at four frequency bands.
{"title":"A quad band quadrature branch line coupler using coupled line sections","authors":"S. A. Imam, Aijaz M. Zaidi, A. Choudhary, B. Kanaujia, M. Singh","doi":"10.1109/ICAM.2017.8242151","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242151","url":null,"abstract":"A new quad band quadrature branch line coupler (BLC) has been presented in this paper. The proposed BLC has been designed with the help of the T shaped coupled line sections, quad band impedance inverter. The BLC has been designed using Advanced Design System (ADS) software for f1 = 0.66 GHz, f2 = 1.52 GHz, f3 = 2.57 GHz and f4 = 3.44 GHz operating frequencies. The Rogers 5870 substrate has been selected for the BLC design. The BLC's S-parameters characteristics including insertion loss, isolation loss, quadrature phase and equal power division have been achieved with 0.58 dB maximum amplitude imbalance and 4.33° maximum phase deviation while preserved the <-10dB return loss and isolation loss at four frequency bands. The simulated results of the BLC verified the theoretical results of the BLC at four frequency bands.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242147
Q. Duan, T. Guo, S. Huang, Min Ding
An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated. The incremental delta-sigma modulator adopting a second-order CIFB structure is implemented in a 0.25-μm 5 V CMOS process with drain extended MOS high-voltage devices. The modulator consuming a current of approximately 400 μA and with a sampling frequency of 500 kHz completes converting one cell voltage in 790 μs. The schematic and layout simulation results show the modulator with a digital filter achieves a resolution of 12 bits and good linearity.
{"title":"An incremental delta-sigma modulator with self-making capacitors for multi-cell battery packs","authors":"Q. Duan, T. Guo, S. Huang, Min Ding","doi":"10.1109/ICAM.2017.8242147","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242147","url":null,"abstract":"An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated. The incremental delta-sigma modulator adopting a second-order CIFB structure is implemented in a 0.25-μm 5 V CMOS process with drain extended MOS high-voltage devices. The modulator consuming a current of approximately 400 μA and with a sampling frequency of 500 kHz completes converting one cell voltage in 790 μs. The schematic and layout simulation results show the modulator with a digital filter achieves a resolution of 12 bits and good linearity.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132932919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242163
Xun Wang, Shiwei Feng, Jingwei Li, Bangbing Shi
This paper proposes a novel method to derive the junction temperature of a Silicon Carbide Schottky Barrier Diode (SiC SBD) when it is in operation. There is a correlation between the switching waveforms and the temperature, due to the material parameters and the carrier vary with the temperature. Estimating the Turn-on-delay time as a temperature sensitive electrical parameter (TSEP), the chip temperature in operation can be evaluated. The experiment is based on signal loop — dealing with the output signal of the chip by the peripheral circuits, then putting it as the switching signal to the chip. Thus, each minimal turn-on-delay time — at nanosecond level — can be accumulated to be a time span at microsecond or second level and the value is averaged to evaluate the turn-on-delay time.
{"title":"Study on junction temperature measurement of SiC Schottky Barrier diode based on turn-on-delay time estimation","authors":"Xun Wang, Shiwei Feng, Jingwei Li, Bangbing Shi","doi":"10.1109/ICAM.2017.8242163","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242163","url":null,"abstract":"This paper proposes a novel method to derive the junction temperature of a Silicon Carbide Schottky Barrier Diode (SiC SBD) when it is in operation. There is a correlation between the switching waveforms and the temperature, due to the material parameters and the carrier vary with the temperature. Estimating the Turn-on-delay time as a temperature sensitive electrical parameter (TSEP), the chip temperature in operation can be evaluated. The experiment is based on signal loop — dealing with the output signal of the chip by the peripheral circuits, then putting it as the switching signal to the chip. Thus, each minimal turn-on-delay time — at nanosecond level — can be accumulated to be a time span at microsecond or second level and the value is averaged to evaluate the turn-on-delay time.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242180
Zhao Lv, Shuming Chen, Yaohua Wang
We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The synthesize result shows the area can be reduced by 37% compared with the multiply without the reuse architecture.
{"title":"A novel high performance SIMD 54-bit multiply array","authors":"Zhao Lv, Shuming Chen, Yaohua Wang","doi":"10.1109/ICAM.2017.8242180","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242180","url":null,"abstract":"We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The synthesize result shows the area can be reduced by 37% compared with the multiply without the reuse architecture.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115356302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242133
Chen Daopin, Chen Zhucheng, Wang Junbo, Ou Xiaomei, Song Anqi
In order to work out the accident caused by the impact or frequent current into the ground on person or equipment near the substation when transmission line tower is short-circuited, the technology of multi-point monitoring to scattered current in the ground were studied in this paper. And then the method is verified by simulation and experiment. At the same time, the scattered current of not monitored points can be calculated by the data obtained. The key technology of monitoring is to use the Rogowski coil to capture the current and eliminate the interference of external environment. A large number of experiments show that the scattered current monitoring system is effective and reliable for the on-line monitoring; it can real-time record and monitor multi-point current waveform and use host computer to handle and analyze; the risk assessment software is designed to protect the safety of people and prevent in advance. The research on the monitoring method is helpful to the development of the current measurement and monitoring technology of the transmission line tower, which can effectively control the safety accidents of person and equipment in the power grid.
{"title":"Monitoring technology of scattered current in transmission line tower","authors":"Chen Daopin, Chen Zhucheng, Wang Junbo, Ou Xiaomei, Song Anqi","doi":"10.1109/ICAM.2017.8242133","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242133","url":null,"abstract":"In order to work out the accident caused by the impact or frequent current into the ground on person or equipment near the substation when transmission line tower is short-circuited, the technology of multi-point monitoring to scattered current in the ground were studied in this paper. And then the method is verified by simulation and experiment. At the same time, the scattered current of not monitored points can be calculated by the data obtained. The key technology of monitoring is to use the Rogowski coil to capture the current and eliminate the interference of external environment. A large number of experiments show that the scattered current monitoring system is effective and reliable for the on-line monitoring; it can real-time record and monitor multi-point current waveform and use host computer to handle and analyze; the risk assessment software is designed to protect the safety of people and prevent in advance. The research on the monitoring method is helpful to the development of the current measurement and monitoring technology of the transmission line tower, which can effectively control the safety accidents of person and equipment in the power grid.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127228148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICAM.2017.8242144
Hong-Yan Su, Po-Ting Chiang, Radhamanjari Samanta, Yih-Lang Li
Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).
{"title":"Clock tree aware post-global placement optimization","authors":"Hong-Yan Su, Po-Ting Chiang, Radhamanjari Samanta, Yih-Lang Li","doi":"10.1109/ICAM.2017.8242144","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242144","url":null,"abstract":"Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122084995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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