When an over-the-cell routing layer is available for a VLSI standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. Three physical models are presented to utilize the area over the cells for routing in standard cell designs. Also presented are efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, it is shown how to arrange inter-cell routing, over-the-cell routing and power/ground buses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. The saving in routing area achieved by these algorithms is up to 21 %.<>
{"title":"General models and algorithms for over-the-cell routing in standard cell design","authors":"J. Cong, B. Preas, C. Liu","doi":"10.1109/DAC.1990.114945","DOIUrl":"https://doi.org/10.1109/DAC.1990.114945","url":null,"abstract":"When an over-the-cell routing layer is available for a VLSI standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. Three physical models are presented to utilize the area over the cells for routing in standard cell designs. Also presented are efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, it is shown how to arrange inter-cell routing, over-the-cell routing and power/ground buses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. The saving in routing area achieved by these algorithms is up to 21 %.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new VLSI min-cut placement algorithm is presented for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays, called GALOP. The application results are described for the case of clock skew control of an ECL 12K-gate array.<>
{"title":"A new min-cut placement algorithm for timing assurance layout design meeting net length constraint","authors":"M. Terai, Kazuhiro Takahashi, Koji Sato","doi":"10.1145/123186.123234","DOIUrl":"https://doi.org/10.1145/123186.123234","url":null,"abstract":"A new VLSI min-cut placement algorithm is presented for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays, called GALOP. The application results are described for the case of clock skew control of an ECL 12K-gate array.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. A. Malik, R. Brayton, A. Newton, A. Sangiovanni-Vincentelli
The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset Tautology-based schemes are generally slower and often give somewhat inferior results, because of a limited global picture of the way in which the cube can be expanded. If the offset is used, usually the expansion can be done quickly and in a more global way because it is easier to see effective directions of expansion. The problem with this approach is that there are many functions that have a reasonably sized onset and don't care set, but the offset is unreasonably large. It was recently shown that for the minimization of such Boolean functions, a new approach using reduced offsets provides the same global picture and can be computed much faster. The authors extend reduced offsets to logic functions with multivalued inputs.<>
{"title":"Reduced offsets for two-level multi-valued logic minimization","authors":"A. A. Malik, R. Brayton, A. Newton, A. Sangiovanni-Vincentelli","doi":"10.1145/123186.123279","DOIUrl":"https://doi.org/10.1145/123186.123279","url":null,"abstract":"The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset Tautology-based schemes are generally slower and often give somewhat inferior results, because of a limited global picture of the way in which the cube can be expanded. If the offset is used, usually the expansion can be done quickly and in a more global way because it is easier to see effective directions of expansion. The problem with this approach is that there are many functions that have a reasonably sized onset and don't care set, but the offset is unreasonably large. It was recently shown that for the minimization of such Boolean functions, a new approach using reduced offsets provides the same global picture and can be computed much faster. The authors extend reduced offsets to logic functions with multivalued inputs.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130418518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem of verifying the equivalence of interacting finite state machines (FSMs) described at the logic level is addressed. The problem is formulated as that of checking for the equivalence of the reset/starting states of the two FSMs. Separate sum-of-product representations of the on-sets and off-sets of each of the flip-flop inputs and primary outputs of the sequential circuit are extracted using the PODEM algorithm. A fast algorithm for state differentiation based on this representation is described. The input and the state space are implicitly enumerated through a process of repeated cube intersections to generate the state transition graph. Unlike previous approaches, this algorithm can be efficiently generalized for verifying distributed-style specifications of interacting sequential circuits, exploiting the nature of the interconnection topology. Pipeline latches in a distributed-style specification typically do not add complexity to the sequential behavior of a circuit, but greatly add to the complexity of traditional approaches to verifying sequential circuits. Pipeline latches are easily incorporated into this generalized, hierarchical verification strategy whereby the states of pipeline latches can be implicitly enumerated.<>
{"title":"Verification of interacting sequential circuits","authors":"Abhijit Ghosh, S. Devadas, A. Newton","doi":"10.1109/DAC.1990.114856","DOIUrl":"https://doi.org/10.1109/DAC.1990.114856","url":null,"abstract":"The problem of verifying the equivalence of interacting finite state machines (FSMs) described at the logic level is addressed. The problem is formulated as that of checking for the equivalence of the reset/starting states of the two FSMs. Separate sum-of-product representations of the on-sets and off-sets of each of the flip-flop inputs and primary outputs of the sequential circuit are extracted using the PODEM algorithm. A fast algorithm for state differentiation based on this representation is described. The input and the state space are implicitly enumerated through a process of repeated cube intersections to generate the state transition graph. Unlike previous approaches, this algorithm can be efficiently generalized for verifying distributed-style specifications of interacting sequential circuits, exploiting the nature of the interconnection topology. Pipeline latches in a distributed-style specification typically do not add complexity to the sequential behavior of a circuit, but greatly add to the complexity of traditional approaches to verifying sequential circuits. Pipeline latches are easily incorporated into this generalized, hierarchical verification strategy whereby the states of pipeline latches can be implicitly enumerated.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131087382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Examined is a problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. It is shown that, if the Boolean network has a tree topology, there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated.<>
{"title":"Algorithms for library-specific sizing of combinational logic","authors":"P. K. Chan","doi":"10.1145/123186.123302","DOIUrl":"https://doi.org/10.1145/123186.123302","url":null,"abstract":"Examined is a problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. It is shown that, if the Boolean network has a tree topology, there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123995415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A super-fast fault simulator for synchronous sequential circuits, called PROOFS, is described. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.<>
{"title":"PROOFS: a fast, memory efficient sequential circuit fault simulator","authors":"T.M. Niermann, W.-T. Cheng, J. Patel","doi":"10.1109/DAC.1990.114913","DOIUrl":"https://doi.org/10.1109/DAC.1990.114913","url":null,"abstract":"A super-fast fault simulator for synchronous sequential circuits, called PROOFS, is described. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124145126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. A segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice with reasonable CPU time by heuristics. The experiments show that a segmented channel can generally accommodate connections using only a few more tracks than a conventional channel would.<>
{"title":"Segmented channel routing","authors":"V. Roychowdhury, J. Greene, A. Gamal","doi":"10.1145/123186.123405","DOIUrl":"https://doi.org/10.1145/123186.123405","url":null,"abstract":"Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. A segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice with reasonable CPU time by heuristics. The experiments show that a segmented channel can generally accommodate connections using only a few more tracks than a conventional channel would.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115949240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Donath, R. J. Norman, B. K. Agrawal, S. E. Bello, Sang-Yong Han, J. M. Kurtzberg, P. Lowy, R. McMillan
A methodology for standard cell or gate array designs is described. A new approach is introduced whereby the placement process is divided into a global step and a detailed step. The timing drive placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.<>
{"title":"Timing driven placement using complete path delays","authors":"W. Donath, R. J. Norman, B. K. Agrawal, S. E. Bello, Sang-Yong Han, J. M. Kurtzberg, P. Lowy, R. McMillan","doi":"10.1109/DAC.1990.114834","DOIUrl":"https://doi.org/10.1109/DAC.1990.114834","url":null,"abstract":"A methodology for standard cell or gate array designs is described. A new approach is introduced whereby the placement process is divided into a global step and a detailed step. The timing drive placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently developed necessary and sufficient conditions for robust path-delay-fault testability are applied to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, a covering procedure is given which optimizes for robust path delay fault testability. These two-level circuits can then be algebraically factored to produce robustly path-delay-fault testable multilevel circuits. For regular structures which cannot be flattened to two levels, a composition procedure is given which allows for the construction of robustly path-delay-fault testable regular structures. Finally, it is shown how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. These techniques are demonstrated on a variety of examples. It is possible to produce entire clips that are fully path delay testable using these techniques.<>
{"title":"Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits","authors":"S. Devadas, K. Keutzer","doi":"10.1109/DAC.1990.114858","DOIUrl":"https://doi.org/10.1109/DAC.1990.114858","url":null,"abstract":"Recently developed necessary and sufficient conditions for robust path-delay-fault testability are applied to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, a covering procedure is given which optimizes for robust path delay fault testability. These two-level circuits can then be algebraically factored to produce robustly path-delay-fault testable multilevel circuits. For regular structures which cannot be flattened to two levels, a composition procedure is given which allows for the construction of robustly path-delay-fault testable regular structures. Finally, it is shown how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. These techniques are demonstrated on a variety of examples. It is possible to produce entire clips that are fully path delay testable using these techniques.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128323450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays. i.e., delays unknown at compile time, must also be considered. A relative scheduling technique that supports operations with fixed and unbounded delays is presented. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. A novel property called well-posedness of timing constraints is analyzed that is used to identify consistency of constraints in the presence of unbounded delay operations, and an approach to relative scheduling is presented that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.<>
{"title":"Relative scheduling under timing constraints","authors":"D. Ku, G. Micheli","doi":"10.1109/DAC.1990.114830","DOIUrl":"https://doi.org/10.1109/DAC.1990.114830","url":null,"abstract":"Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays. i.e., delays unknown at compile time, must also be considered. A relative scheduling technique that supports operations with fixed and unbounded delays is presented. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. A novel property called well-posedness of timing constraints is analyzed that is used to identify consistency of constraints in the presence of unbounded delay operations, and an approach to relative scheduling is presented that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124727277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：