A new approach called percolation-based synthesis for the scheduling phase of high-level synthesis (HLS) is presented. Some new techniques are discussed for compaction of flow graphs beyond basic block limits, which can produce order-of-magnitude speedups versus serial execution. The presented algorithm applies to programs with conditional jumps, loops, and multicycle pipelined operations. In order to schedule under resource constraints, one starts by first finding the optimal schedule (without constraints) and then adds heuristics to map the optimal schedule onto the given system. It is argued that starting from an optimal schedule is one of the most important factors in scheduling because it offers the user flexibility to tune the heuristics and gives a good bound for the resource-constrained schedule. This scheduling algorithm is integrated with a synthesis tool which uses VHDL as input description and produces a structural netlist of generic register-transfer components and a unit-based control table as output.<>
{"title":"Percolation based synthesis","authors":"R. Potasman, Joseph Lis, A. Nicolau, D. Gajski","doi":"10.1109/DAC.1990.114897","DOIUrl":"https://doi.org/10.1109/DAC.1990.114897","url":null,"abstract":"A new approach called percolation-based synthesis for the scheduling phase of high-level synthesis (HLS) is presented. Some new techniques are discussed for compaction of flow graphs beyond basic block limits, which can produce order-of-magnitude speedups versus serial execution. The presented algorithm applies to programs with conditional jumps, loops, and multicycle pipelined operations. In order to schedule under resource constraints, one starts by first finding the optimal schedule (without constraints) and then adds heuristics to map the optimal schedule onto the given system. It is argued that starting from an optimal schedule is one of the most important factors in scheduling because it offers the user flexibility to tune the heuristics and gives a good bound for the resource-constrained schedule. This scheduling algorithm is integrated with a synthesis tool which uses VHDL as input description and produces a structural netlist of generic register-transfer components and a unit-based control table as output.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133002290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed.<>
{"title":"Clock routing for high-performance ICs","authors":"M. Jackson, A. Srinivasan, E. Kuh","doi":"10.1109/DAC.1990.114920","DOIUrl":"https://doi.org/10.1109/DAC.1990.114920","url":null,"abstract":"Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new logic design timing verification technique named coded time-symbolic simulation (CTSS) is presented. Novel techniques of analyzing the results of CTSS are proposed. Simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values is considered. The cases of possible delay values of each gate are encoded by binary values, and all the possible combinations of the delay values are simulated by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. An efficient simulator was implemented by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions.<>
{"title":"Coded time-symbolic simulation using shared binary decision diagram","authors":"N. Ishiura, Y. Deguchi, S. Yajima","doi":"10.1109/DAC.1990.114842","DOIUrl":"https://doi.org/10.1109/DAC.1990.114842","url":null,"abstract":"A new logic design timing verification technique named coded time-symbolic simulation (CTSS) is presented. Novel techniques of analyzing the results of CTSS are proposed. Simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values is considered. The cases of possible delay values of each gate are encoded by binary values, and all the possible combinations of the delay values are simulated by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. An efficient simulator was implemented by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114381764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MACLOG is a family of layout generators for the AT&T Cell Library. The MACLOG layout generator set is built on an object-oriented framework. Most frameworks are built around the hierarchy of module types. It is found that service hierarchy-the types of information provided to the user by the generator-makes the framework and generators easier to design and modify. The MACLOG framework and the experience with framework structure are described.<>
{"title":"A framework for industrial layout generators","authors":"W. Bower, C. Seaquist, W. Wolf","doi":"10.1109/DAC.1990.114893","DOIUrl":"https://doi.org/10.1109/DAC.1990.114893","url":null,"abstract":"MACLOG is a family of layout generators for the AT&T Cell Library. The MACLOG layout generator set is built on an object-oriented framework. Most frameworks are built around the hierarchy of module types. It is found that service hierarchy-the types of information provided to the user by the generator-makes the framework and generators easier to design and modify. The MACLOG framework and the experience with framework structure are described.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121426663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The false path problem on precharge/unate networks, more commonly known as dynamic CMOS networks, is considered. It is demonstrated that the tight criterion of dynamic sensitization is robust on such networks, though it has been shown to be nonrobust on general networks. Tighter bounds may be obtained on the length of the critical path in precharge/unate networks than in general static networks. A dynamic programming procedure to find the longest dynamically sensitizable path in a precharge/unate network is derived.<>
{"title":"Timing analysis in precharge/unate networks","authors":"P. McGeer, R. Brayton","doi":"10.1109/DAC.1990.114841","DOIUrl":"https://doi.org/10.1109/DAC.1990.114841","url":null,"abstract":"The false path problem on precharge/unate networks, more commonly known as dynamic CMOS networks, is considered. It is demonstrated that the tight criterion of dynamic sensitization is robust on such networks, though it has been shown to be nonrobust on general networks. Tighter bounds may be obtained on the length of the critical path in precharge/unate networks than in general static networks. A dynamic programming procedure to find the longest dynamically sensitizable path in a precharge/unate network is derived.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125314806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A point-to-point routing algorithm with three new features is presented. First, the router makes optimal use of oversized, rectangular contacts. Second, it allows different wire width on different layers, with the layers having complete freedom as to routing direction. These two features make the algorithm attractive for MOS layout applications. Finally, it is able to realize an all-angle routing and to accept all-angle obstacles, a feature interesting for hybrid and PCB routing. The router is gridless and guarantees a solution if one exists. Since it is based on computational geometry algorithms, it offers a low run-time complexity. The ideas have been implemented in a prototype version for 45 degrees routing. The results indicate that the router performs well, even on large designs.<>
{"title":"A gridless router for industrial design rules","authors":"W. Schiele, Thomas Krüger, K. M. Just, F. Kirsch","doi":"10.1109/DAC.1990.114929","DOIUrl":"https://doi.org/10.1109/DAC.1990.114929","url":null,"abstract":"A point-to-point routing algorithm with three new features is presented. First, the router makes optimal use of oversized, rectangular contacts. Second, it allows different wire width on different layers, with the layers having complete freedom as to routing direction. These two features make the algorithm attractive for MOS layout applications. Finally, it is able to realize an all-angle routing and to accept all-angle obstacles, a feature interesting for hybrid and PCB routing. The router is gridless and guarantees a solution if one exists. Since it is based on computational geometry algorithms, it offers a low run-time complexity. The ideas have been implemented in a prototype version for 45 degrees routing. The results indicate that the router performs well, even on large designs.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126176455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong canonical form in the ROBDD and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory function for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for recycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described is significantly faster and more memory-efficient than other ROBDD implementations described in the literature.<>
{"title":"Efficient implementation of a BDD package","authors":"K. Brace, R. Rudell, R. Bryant","doi":"10.1109/DAC.1990.114826","DOIUrl":"https://doi.org/10.1109/DAC.1990.114826","url":null,"abstract":"Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong canonical form in the ROBDD and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory function for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for recycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described is significantly faster and more memory-efficient than other ROBDD implementations described in the literature.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cell synthesis is the process of transforming detailed, transistor level specifications and technology information into layout. While cell synthesis has been investigated for several years, only recently has it become practical and pervasive. To accelerate this process and to encourage further refinement, a set of benchmarks was developed for cell synthesis tools. The benchmarks try to balance the objective of universal participation against that of comprehensive testing. They cover the areas of arithmetic, finite state machines (FSM), RAM, and analog design and include detailed descriptions of technology rules. Discussed are the benchmarks, and how they may be used as a guide to future work in this field.<>
{"title":"Benchmarks for cell synthesis","authors":"D. Hill, B. Preas","doi":"10.1109/DAC.1990.114873","DOIUrl":"https://doi.org/10.1109/DAC.1990.114873","url":null,"abstract":"Cell synthesis is the process of transforming detailed, transistor level specifications and technology information into layout. While cell synthesis has been investigated for several years, only recently has it become practical and pervasive. To accelerate this process and to encourage further refinement, a set of benchmarks was developed for cell synthesis tools. The benchmarks try to balance the objective of universal participation against that of comprehensive testing. They cover the areas of arithmetic, finite state machines (FSM), RAM, and analog design and include detailed descriptions of technology rules. Discussed are the benchmarks, and how they may be used as a guide to future work in this field.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132608030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An electron beam exposure system used for LSI mask making or direct writing for ASICs is considered. In CAD data/electron beam exposure-data conversion, a new algorithm for treating overlapping cells hierarchically is proposed. Geometric transformations, such as resizing, for overlapping cells are performed without referring to other cells by introducing a data marking structure. The conversion time of a 16M DRAM and 70 K-gate LSI circuits becomes as short as 23 and 62 CPU minutes, respectively, using a 12-MIPS computer.<>
{"title":"New algorithm for overlapping cell treatment in hierarchical CAD data/electron beam exposure data conversion","authors":"T. Okubo, Takashi Watanabe, K. Wada","doi":"10.1109/DAC.1990.114874","DOIUrl":"https://doi.org/10.1109/DAC.1990.114874","url":null,"abstract":"An electron beam exposure system used for LSI mask making or direct writing for ASICs is considered. In CAD data/electron beam exposure-data conversion, a new algorithm for treating overlapping cells hierarchically is proposed. Geometric transformations, such as resizing, for overlapping cells are performed without referring to other cells by introducing a data marking structure. The conversion time of a 16M DRAM and 70 K-gate LSI circuits becomes as short as 23 and 62 CPU minutes, respectively, using a 12-MIPS computer.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133773551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multilevel logic synthesis method based on standard cells and aiming at reducing both gate and wiring areas is presented. The goal is to decrease the routing factor which is defined as a ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on a lexicographical expression of a Boolean function controlling the input dependency and on a kernel filtering controlling the excessive factorizations responsible for wiring complexity increase.<>
{"title":"Multilevel synthesis minimizing the routing factor","authors":"P. Abouzeid, K. Sakouti, G. Saucier, F. Poirot","doi":"10.1109/DAC.1990.114884","DOIUrl":"https://doi.org/10.1109/DAC.1990.114884","url":null,"abstract":"A multilevel logic synthesis method based on standard cells and aiming at reducing both gate and wiring areas is presented. The goal is to decrease the routing factor which is defined as a ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on a lexicographical expression of a Boolean function controlling the input dependency and on a kernel filtering controlling the excessive factorizations responsible for wiring complexity increase.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131015638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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