MICON is a knowledge-based system that designs small computer systems. The synthesis of a digital system may be viewed as successive design and redesign of individual subsystems. Redesign is necessary when the design of one subsystem imposes conflicting requirements on the design of another, and when a design cannot meet specifications. Described is a technique to correct failures during the synthesis process based on dependency-directed backtracking. The dependency network is built dynamically during the design process. The failure recovery scheme implemented is more sophisticated than most existing schemes because of the unstructured problem domain on which it is applied.<>
{"title":"Failure recovery in the MICON system","authors":"A. J. Daga, W. Birmingham","doi":"10.1145/123186.123440","DOIUrl":"https://doi.org/10.1145/123186.123440","url":null,"abstract":"MICON is a knowledge-based system that designs small computer systems. The synthesis of a digital system may be viewed as successive design and redesign of individual subsystems. Redesign is necessary when the design of one subsystem imposes conflicting requirements on the design of another, and when a design cannot meet specifications. Described is a technique to correct failures during the synthesis process based on dependency-directed backtracking. The dependency network is built dynamically during the design process. The failure recovery scheme implemented is more sophisticated than most existing schemes because of the unstructured problem domain on which it is applied.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.<>
{"title":"Constraint generation for routing analog circuits","authors":"U. Choudhury, A. Sangiovanni-Vincentelli","doi":"10.1109/DAC.1990.114918","DOIUrl":"https://doi.org/10.1109/DAC.1990.114918","url":null,"abstract":"An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123689844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm is presented to optimally distribute a signal to its required destinations. The choice of the buffers and the topology of the distribution tree depends on the availability of different strength gates and on the load and the required times at the destination. Since the area-constrained fanout problem is NP-complete and area is not a major consideration in present high-density designs, attention is restricted to the simpler problem of designing fast fanout circuits without any area constraint. The proposed algorithm builds the fanout tree by partitioning the fanout signals into subsets and then recursively solving each subproblem. At each stage the algorithm generates a fanout tree that is an improvement over the previous stage. This feature allows the user to specify the improvement desired by the fanout correction process. The performance of the algorithm, when run on randomly generated distributions of required times and on real design examples, is very promising.<>
{"title":"A heuristic algorithm for the fanout problem","authors":"K. J. Singh, A. Sangiovanni-Vincentelli","doi":"10.1145/123186.123303","DOIUrl":"https://doi.org/10.1145/123186.123303","url":null,"abstract":"An algorithm is presented to optimally distribute a signal to its required destinations. The choice of the buffers and the topology of the distribution tree depends on the availability of different strength gates and on the load and the required times at the destination. Since the area-constrained fanout problem is NP-complete and area is not a major consideration in present high-density designs, attention is restricted to the simpler problem of designing fast fanout circuits without any area constraint. The proposed algorithm builds the fanout tree by partitioning the fanout signals into subsets and then recursively solving each subproblem. At each stage the algorithm generates a fanout tree that is an improvement over the previous stage. This feature allows the user to specify the improvement desired by the fanout correction process. The performance of the algorithm, when run on randomly generated distributions of required times and on real design examples, is very promising.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An intermediate representation for behavioral and structural designs that is based on annotated state tables is described. It facilitates user control of the synthesis process by allowing specification of partially designed structures, and a mixture of behavior, structure, and user specified bindings between the abstract behavior and the structure. The format's general model allows the capture of synchronous and asynchronous behavior, and permits hierarchical descriptions with concurrency. The format is easily translated to VHDL for simulation at each stage of the design process. It therefore complements a good simulation language (VHDL) by providing an excellent input path for behavioral and register-transfer synthesis. The format's simple and uniform syntax allows it to be used both as an intermediate exchange format for various behavioral synthesis tools, and as a graphical tabular interface for the user, thereby allowing a natural medium for automatic or manual refinement of the design.<>
{"title":"An intermediate representation for behavioral synthesis","authors":"N. Dutt, T. Hadley, D. Gajski","doi":"10.1109/DAC.1990.114821","DOIUrl":"https://doi.org/10.1109/DAC.1990.114821","url":null,"abstract":"An intermediate representation for behavioral and structural designs that is based on annotated state tables is described. It facilitates user control of the synthesis process by allowing specification of partially designed structures, and a mixture of behavior, structure, and user specified bindings between the abstract behavior and the structure. The format's general model allows the capture of synchronous and asynchronous behavior, and permits hierarchical descriptions with concurrency. The format is easily translated to VHDL for simulation at each stage of the design process. It therefore complements a good simulation language (VHDL) by providing an excellent input path for behavioral and register-transfer synthesis. The format's simple and uniform syntax allows it to be used both as an intermediate exchange format for various behavioral synthesis tools, and as a graphical tabular interface for the user, thereby allowing a natural medium for automatic or manual refinement of the design.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124791894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since many ASICs are dominated by control functions, control-dominated architectures form an important domain for behavioral synthesis. It is proposed to model control-dominated architectures during behavioral synthesis as networks of communicating finite state machines (FSMs). The model more directly reflects behavior and allows more accurate cost estimation, especially for control, than do traditional data-directed representations for control-dominated machines. It is shown how to implement a number of important compiler optimizations on the FSM network model.<>
{"title":"The FSM network model for behavioral synthesis of control-dominated machines","authors":"W. Wolf","doi":"10.1109/DAC.1990.114942","DOIUrl":"https://doi.org/10.1109/DAC.1990.114942","url":null,"abstract":"Since many ASICs are dominated by control functions, control-dominated architectures form an important domain for behavioral synthesis. It is proposed to model control-dominated architectures during behavioral synthesis as networks of communicating finite state machines (FSMs). The model more directly reflects behavior and allows more accurate cost estimation, especially for control, than do traditional data-directed representations for control-dominated machines. It is shown how to implement a number of important compiler optimizations on the FSM network model.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123555365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A data management package, called Organized C, is described. The main features of this package are simple and compact declarations which translate organizations into the definitions of classes, pointers, and access functions. This method adds a new dimension to the inheritance mechanism, works with both C and C++, and is specifically useful for CAD software which often deals with large and complex data. It also leads to a unified coding style for algorithms and memory resident databases. Practical experience indicates that organized C improves software quality and productivity in both C and C++: coding and debugging three times faster is common, while the run-time performance and memory remain as good as those of hand-coded C. Resulting programs are strongly typed, protected against dangling pointers and, because of their clear organization, are much easier to maintain.<>
{"title":"Organized C: a unified method of handling data in CAD algorithms and databases","authors":"J. Soukup","doi":"10.1109/DAC.1990.114894","DOIUrl":"https://doi.org/10.1109/DAC.1990.114894","url":null,"abstract":"A data management package, called Organized C, is described. The main features of this package are simple and compact declarations which translate organizations into the definitions of classes, pointers, and access functions. This method adds a new dimension to the inheritance mechanism, works with both C and C++, and is specifically useful for CAD software which often deals with large and complex data. It also leads to a unified coding style for algorithms and memory resident databases. Practical experience indicates that organized C improves software quality and productivity in both C and C++: coding and debugging three times faster is common, while the run-time performance and memory remain as good as those of hand-coded C. Resulting programs are strongly typed, protected against dangling pointers and, because of their clear organization, are much easier to maintain.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128332752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new and practical approach to several layout optimization problems is introduced. A novel two-dimensional pattern generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from wire crossing minimization and topological via minimization to minimum Steiner tree optimization and IO alignment. The expected running time is O(n log n) and the space requirement is O(n), where n is the number of layout objects. The system was fully coded and tested, and excellent results in both laboratory and real-life examples were achieved.<>
{"title":"Layout optimization by pattern modification","authors":"R. Hojati","doi":"10.1145/123186.123424","DOIUrl":"https://doi.org/10.1145/123186.123424","url":null,"abstract":"A new and practical approach to several layout optimization problems is introduced. A novel two-dimensional pattern generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from wire crossing minimization and topological via minimization to minimum Steiner tree optimization and IO alignment. The expected running time is O(n log n) and the space requirement is O(n), where n is the number of layout objects. The system was fully coded and tested, and excellent results in both laboratory and real-life examples were achieved.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121147061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design platform is a central user interface to a CAD framework. It enables information retrieval, object selection, and tool activation in a uniform and integrated fashion. A description is given of such a design platform with emphasis on the graphical metadesign data-browsing facilities. The design platform informs designers about the latest developments of their designs and simplifies interaction with the design system. It enables designers to concentrate more on their main task of electronics design, resulting in better designs and increased productivity. Although the design platform presented has been implemented on top of the NELSIS CAD framework, the ideas and concepts can be used in a variety of applications where data of interest to end users are maintained by a framework.<>
{"title":"A design platform for the NELSIS CAD framework","authors":"P. Bingley, P. van der Wolf","doi":"10.1109/DAC.1990.114845","DOIUrl":"https://doi.org/10.1109/DAC.1990.114845","url":null,"abstract":"A design platform is a central user interface to a CAD framework. It enables information retrieval, object selection, and tool activation in a uniform and integrated fashion. A description is given of such a design platform with emphasis on the graphical metadesign data-browsing facilities. The design platform informs designers about the latest developments of their designs and simplifies interaction with the design system. It enables designers to concentrate more on their main task of electronics design, resulting in better designs and increased productivity. Although the design platform presented has been implemented on top of the NELSIS CAD framework, the ideas and concepts can be used in a variety of applications where data of interest to end users are maintained by a framework.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116709913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression circuit for delay fault testing, and (3) a pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer.<>
{"title":"Automatic incorporation of on-chip testability circuits","authors":"N. Ito","doi":"10.1109/DAC.1990.114912","DOIUrl":"https://doi.org/10.1109/DAC.1990.114912","url":null,"abstract":"A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression circuit for delay fault testing, and (3) a pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB.<>
{"title":"LiB: a cell layout generator","authors":"Yung-Ching Hsieh, Chi-Yi Hwang, Y. Lin, Y. Hsu","doi":"10.1109/DAC.1990.114902","DOIUrl":"https://doi.org/10.1109/DAC.1990.114902","url":null,"abstract":"An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125647523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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