K. Adamiak, R. Allen, J. Poltz, C. Rebizant, A. Wexler
An efficient method for analog simulation of printed circuit board systems is proposed. It is based on the transmission line model circuit derived from the analysis of the electromagnetic field in a two-dimensional cross section of devices. Simulation results from two circuits with IC package, cable, and connector models are presented. The results confirm the effectiveness of this method.<>
{"title":"System simulation of printed circuit boards including packages and connectors","authors":"K. Adamiak, R. Allen, J. Poltz, C. Rebizant, A. Wexler","doi":"10.1109/DAC.1990.114892","DOIUrl":"https://doi.org/10.1109/DAC.1990.114892","url":null,"abstract":"An efficient method for analog simulation of printed circuit board systems is proposed. It is based on the transmission line model circuit derived from the analysis of the electromagnetic field in a two-dimensional cross section of devices. Simulation results from two circuits with IC package, cable, and connector models are presented. The results confirm the effectiveness of this method.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122258037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis they stress optimization across conditional branches. Several path-based algorithms are presented. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions are also implemented. Extensive application of these algorithms to the benchmarks of the high-level synthesis workshop shows the practical feasibility of such methods.<>
{"title":"Synthesis using path-based scheduling: algorithms and exercises","authors":"Raul Compasano, R. Bergamaschi","doi":"10.1109/DAC.1990.114898","DOIUrl":"https://doi.org/10.1109/DAC.1990.114898","url":null,"abstract":"Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis they stress optimization across conditional branches. Several path-based algorithms are presented. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions are also implemented. Extensive application of these algorithms to the benchmarks of the high-level synthesis workshop shows the practical feasibility of such methods.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127814066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm is presented for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g., area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches and then to choose optimally configurations within each stage. The new algorithm allows the designer to specify the number of stages in the pipeline as well as the clocking frequency of each stage. It also permits the use of totally arbitrary timing functions-that is, an implementation may produce different output times if the ready times of its various inputs are rearranged.<>
{"title":"Automatic operator configuration in the synthesis of pipelined architectures","authors":"K. N. McNall, A. Casavant","doi":"10.1109/DAC.1990.114850","DOIUrl":"https://doi.org/10.1109/DAC.1990.114850","url":null,"abstract":"An algorithm is presented for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g., area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches and then to choose optimally configurations within each stage. The new algorithm allows the designer to specify the number of stages in the pipeline as well as the clocking frequency of each stage. It also permits the use of totally arbitrary timing functions-that is, an implementation may produce different output times if the ready times of its various inputs are rearranged.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121033076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The use of a general-purpose, message-based multiprocessor to speed up the task of VLSI circuit extraction is discussed. The parallel algorithm incorporates the use of secondary storage to allow complete VLSI circuits to be extracted with small-scale multiprocessors. Experimental results for the detection and labeling of transistor regions are presented.<>
{"title":"Circuit extraction on a message-based multiprocessor","authors":"B. A. Tonkin","doi":"10.1109/DAC.1990.114864","DOIUrl":"https://doi.org/10.1109/DAC.1990.114864","url":null,"abstract":"The use of a general-purpose, message-based multiprocessor to speed up the task of VLSI circuit extraction is discussed. The parallel algorithm incorporates the use of secondary storage to allow complete VLSI circuits to be extracted with small-scale multiprocessors. Experimental results for the detection and labeling of transistor regions are presented.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123372205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm is given for computing subsets of the observability don't cares at the nodes of a multilevel Boolean network. These subsets are based on an extension of the methods introduced by S. Muroga et al. (IEEE Trans. on Computers, Oct. 1989) for computing compatible sets of permissible functions (CSPFs) at the nodes of networks composed of NOR gates. The extensions presented are in four directions: an arbitrary logic function is allowed at any node, the don't cares are expressed in terms of both primary inputs and intermediate variables, a new ordering scheme is used. and maximal CSPFs are computed. These ideas are incorporated in an algorithm designed to take full advantage of the power of two-level minimization in multilevel logic synthesis systems. This has been implemented in MIS-II, and results are presented that demonstrate the effectiveness of these techniques.<>
{"title":"The use of observability and external don't cares for the simplification of multi-level networks","authors":"H. Savoj, R. Brayton","doi":"10.1109/DAC.1990.114954","DOIUrl":"https://doi.org/10.1109/DAC.1990.114954","url":null,"abstract":"An algorithm is given for computing subsets of the observability don't cares at the nodes of a multilevel Boolean network. These subsets are based on an extension of the methods introduced by S. Muroga et al. (IEEE Trans. on Computers, Oct. 1989) for computing compatible sets of permissible functions (CSPFs) at the nodes of networks composed of NOR gates. The extensions presented are in four directions: an arbitrary logic function is allowed at any node, the don't cares are expressed in terms of both primary inputs and intermediate variables, a new ordering scheme is used. and maximal CSPFs are computed. These ideas are incorporated in an algorithm designed to take full advantage of the power of two-level minimization in multilevel logic synthesis systems. This has been implemented in MIS-II, and results are presented that demonstrate the effectiveness of these techniques.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123380823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new synthesis-for-testability method is presented in which a test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as a FSM with the same number of state variables as the given object machine. The state graph of the test machine is so defined that each state is uniquely set and observed by an input sequence no longer than log/sub k/ n, where n is the number of states and the integer k is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are then carried out for the combined graph. By this design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements. the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.<>
{"title":"Test function specification in synthesis","authors":"V. Agrawal, K. Cheng","doi":"10.1109/DAC.1990.114860","DOIUrl":"https://doi.org/10.1109/DAC.1990.114860","url":null,"abstract":"A new synthesis-for-testability method is presented in which a test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as a FSM with the same number of state variables as the given object machine. The state graph of the test machine is so defined that each state is uniquely set and observed by an input sequence no longer than log/sub k/ n, where n is the number of states and the integer k is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are then carried out for the combined graph. By this design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements. the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117161991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Scheichenzuber, W. Grass, U. Lauther, Sabine März
A new bottom-up logic synthesis technique for general behavioral descriptions is reported. The technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account, and both high-level synthesis and design-space exploration are addressed.<>
{"title":"Global hardware synthesis from behavioral dataflow descriptions","authors":"J. Scheichenzuber, W. Grass, U. Lauther, Sabine März","doi":"10.1109/DAC.1990.114899","DOIUrl":"https://doi.org/10.1109/DAC.1990.114899","url":null,"abstract":"A new bottom-up logic synthesis technique for general behavioral descriptions is reported. The technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account, and both high-level synthesis and design-space exploration are addressed.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115567298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient delay test generation system for combinational logic circuits is presented. Delay testing problems are divided into gross-delay fault testing and small-delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross-delay and small-delay faults. A novel timing analysis method via functionality check is presented for delay test generation. Complete test results are demonstrated for both gross-delay and small-delay faults on several benchmark circuits.<>
{"title":"An efficient delay test generation system for combinational logic circuits","authors":"E. Park, M. R. Mercer","doi":"10.1109/DAC.1990.114911","DOIUrl":"https://doi.org/10.1109/DAC.1990.114911","url":null,"abstract":"An efficient delay test generation system for combinational logic circuits is presented. Delay testing problems are divided into gross-delay fault testing and small-delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross-delay and small-delay faults. A novel timing analysis method via functionality check is presented for delay test generation. Complete test results are demonstrated for both gross-delay and small-delay faults on several benchmark circuits.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115837661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A heuristic approach to the optimal selection of standard cells in VLSI circuit design is presented. A cell library is composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, one selects the best templates from the cell library to minimize the total area of the cells under delay constraints. The algorithm is capable of handling efficiently relatively large designs taking into account the entire circuit, not iterating on a path basis. Carefully chosen weights reflect the significance of particular cells in the circuit and guide the template selection process. Because the algorithm is capable of increasing and decreasing the templates, very good experimental results are achieved.<>
{"title":"Delay and area optimization in standard-cell design","authors":"Shen Lin, M. Marek-Sadowska, E. Kuh","doi":"10.1109/DAC.1990.114880","DOIUrl":"https://doi.org/10.1109/DAC.1990.114880","url":null,"abstract":"A heuristic approach to the optimal selection of standard cells in VLSI circuit design is presented. A cell library is composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, one selects the best templates from the cell library to minimize the total area of the cells under delay constraints. The algorithm is capable of handling efficiently relatively large designs taking into account the entire circuit, not iterating on a path basis. Carefully chosen weights reflect the significance of particular cells in the circuit and guide the template selection process. Because the algorithm is capable of increasing and decreasing the templates, very good experimental results are achieved.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This multilevel interconnect model for VLSI data path synthesis is designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. The algorithms help implement the generalized interconnect model in the ELF hardware compiler.<>
{"title":"A generalized interconnect model for data path synthesis","authors":"T. Ly, Lloyd Elwood, E. F. Girczyc","doi":"10.1109/DAC.1990.114849","DOIUrl":"https://doi.org/10.1109/DAC.1990.114849","url":null,"abstract":"This multilevel interconnect model for VLSI data path synthesis is designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. The algorithms help implement the generalized interconnect model in the ELF hardware compiler.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131101532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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