A system designed for verifying the consistency of timing specifications for digital circuits is presented. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. To perform this interface verification, two operators are defined which allow one to perform useful reasoning concerning the interface. One operator deals with causality and another with timing constraints. The system can also be used in the case of verifying specifications of unimplemented components. The system is implemented as a hardware design timing verification (HDTV) program.<>
{"title":"Timing verification using HDTV","authors":"A. R. Martello, S. Levitan, D. Chiarulli","doi":"10.1109/DAC.1990.114840","DOIUrl":"https://doi.org/10.1109/DAC.1990.114840","url":null,"abstract":"A system designed for verifying the consistency of timing specifications for digital circuits is presented. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. To perform this interface verification, two operators are defined which allow one to perform useful reasoning concerning the interface. One operator deals with causality and another with timing constraints. The system can also be used in the case of verifying specifications of unimplemented components. The system is implemented as a hardware design timing verification (HDTV) program.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The placement algorithm, called the hierarchical clustering with min-cut exchange (HCME), is effective at avoiding being trapped in local optimum solutions. The global routing algorithm does not route the nets one by one and therefore the results are independent of the net order and channel order. In this algorithm, channel width is minimized under a cost function, in which the trade-off between the minimization of net-lengths and the minimization of the number of tracks is considered. These algorithms are simple and highly efficient. This is confirmed by computational experiments.<>
{"title":"New placement and global routing algorithms for standard cell layouts","authors":"M. Edahiro, T. Yoshimura","doi":"10.1145/123186.123427","DOIUrl":"https://doi.org/10.1145/123186.123427","url":null,"abstract":"The placement algorithm, called the hierarchical clustering with min-cut exchange (HCME), is effective at avoiding being trapped in local optimum solutions. The global routing algorithm does not route the nets one by one and therefore the results are independent of the net order and channel order. In this algorithm, channel width is minimized under a cost function, in which the trade-off between the minimization of net-lengths and the minimization of the number of tracks is considered. These algorithms are simple and highly efficient. This is confirmed by computational experiments.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K-input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 LOGIC Synthesis benchmarks Chortle achieves superior results in significantly less time.<>
{"title":"Chortle: a technology mapping program for lookup table-based field programmable gate arrays","authors":"R. Francis, Jonathan Rose, K. Chung","doi":"10.1145/123186.123418","DOIUrl":"https://doi.org/10.1145/123186.123418","url":null,"abstract":"An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K-input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 LOGIC Synthesis benchmarks Chortle achieves superior results in significantly less time.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parallel pattern mixed-level fault simulator is described and demonstrated. The switch level allows the simulator to treat transistor faults such as stuck-open and stuck-short faults, the gate level allows the simulator to conserve the speed advantage of the gate level simulation, and the parallel pattern single-fault propagation (PPSFP) strategy enhances the simulation speed at least one order of magnitude, depending on the word length to implement the simulator. The simulator is built on the basis of a set of operators that translate the switch-level signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. These make parallel pattern evaluation for switch level simulation possible. The implemented simulator exhibits an O(G/sup 1.88/) performance for the logic-level simulation. This can be further improved if a longer word length is adopted.<>
{"title":"A parallel pattern mixed-level fault simulator","authors":"Tyh-Song Hwang, Chung-Len Lee, W. Shen, C. Wu","doi":"10.1145/123186.123449","DOIUrl":"https://doi.org/10.1145/123186.123449","url":null,"abstract":"A parallel pattern mixed-level fault simulator is described and demonstrated. The switch level allows the simulator to treat transistor faults such as stuck-open and stuck-short faults, the gate level allows the simulator to conserve the speed advantage of the gate level simulation, and the parallel pattern single-fault propagation (PPSFP) strategy enhances the simulation speed at least one order of magnitude, depending on the word length to implement the simulator. The simulator is built on the basis of a set of operators that translate the switch-level signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. These make parallel pattern evaluation for switch level simulation possible. The implemented simulator exhibits an O(G/sup 1.88/) performance for the logic-level simulation. This can be further improved if a longer word length is adopted.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fault-tolerant design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired without reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and leads to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.<>
{"title":"Design of repairable and fully diagnosable folded PLAs for yield enhancement","authors":"C. Wey, Jyhyeung Ding, Tsin-Yuan Chang","doi":"10.1145/123186.123295","DOIUrl":"https://doi.org/10.1145/123186.123295","url":null,"abstract":"A fault-tolerant design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired without reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and leads to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133777968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Murgai, Y. Nishizaki, Narendra V. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli
The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures.<>
{"title":"Logic synthesis for programmable gate arrays","authors":"R. Murgai, Y. Nishizaki, Narendra V. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1145/123186.123421","DOIUrl":"https://doi.org/10.1145/123186.123421","url":null,"abstract":"The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An object-oriented kernel that integrates design and process planning in the domain of mechanical parts is presented. The kernel identifies and separates the integral elements of its domain from the elements that are associated with a particular design/manufacturing environment. Consequently, it can be customized to a wide range of environments and be used as a rapid prototyping tool. A prototype is developed and implemented in Smalltalk-80.<>
{"title":"An object-oriented kernel for an integrated design and process planning system","authors":"S. J. Feghhi, M. Marefat, R. Kashyap","doi":"10.1109/DAC.1990.114896","DOIUrl":"https://doi.org/10.1109/DAC.1990.114896","url":null,"abstract":"An object-oriented kernel that integrates design and process planning in the domain of mechanical parts is presented. The kernel identifies and separates the integral elements of its domain from the elements that are associated with a particular design/manufacturing environment. Consequently, it can be customized to a wide range of environments and be used as a rapid prototyping tool. A prototype is developed and implemented in Smalltalk-80.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117196748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A practical online design rule checking system is proposed. which can provide the following features: an ability to cope with a complicated and wide variety of design rules with high accuracy, easy use, high-speed incremental DRC (simultaneous checking with pattern editing) and total DRC (nonsimultaneous checking), high-speed pattern editing, and a small memory space. For the last three items, a field block data structure is developed. Experimental results show that this system is effective for VLSI cell layout design.<>
{"title":"A practical online design rule checking system","authors":"G. Suzuki, Y. Okamura","doi":"10.1109/DAC.1990.114862","DOIUrl":"https://doi.org/10.1109/DAC.1990.114862","url":null,"abstract":"A practical online design rule checking system is proposed. which can provide the following features: an ability to cope with a complicated and wide variety of design rules with high accuracy, easy use, high-speed incremental DRC (simultaneous checking with pattern editing) and total DRC (nonsimultaneous checking), high-speed pattern editing, and a small memory space. For the last three items, a field block data structure is developed. Experimental results show that this system is effective for VLSI cell layout design.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127456438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A component database for behavioral synthesis of digital circuits should generate components that fit specific design requirements and provide information about a component's electrical and layout characteristics for possible architectural tradeoffs. A component server, called the intelligent component database (ICDB), is described. ICDB can dynamically generate components for a given set of constraints and attributes. Further, it provides delay, area, and shape estimates that support design tradeoffs on the microarchitecture-level. The ICDB is designed to be used with tools for behavioral, logic, and layout synthesis. Experiments demonstrate that such a component server can replace component catalogs with hundreds of pages.<>
{"title":"An intelligent component database for behavioral synthesis","authors":"Gwo-Dong Chen, D. Gajski","doi":"10.1109/DAC.1990.114846","DOIUrl":"https://doi.org/10.1109/DAC.1990.114846","url":null,"abstract":"A component database for behavioral synthesis of digital circuits should generate components that fit specific design requirements and provide information about a component's electrical and layout characteristics for possible architectural tradeoffs. A component server, called the intelligent component database (ICDB), is described. ICDB can dynamically generate components for a given set of constraints and attributes. Further, it provides delay, area, and shape estimates that support design tradeoffs on the microarchitecture-level. The ICDB is designed to be used with tools for behavioral, logic, and layout synthesis. Experiments demonstrate that such a component server can replace component catalogs with hundreds of pages.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"42 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The temporal logic model algorithm of E.M. Clarke et al. (ACM Trans. Prog. Lang. Syst., vol.8, no.2, p.244-63, 1986) is modified to represent a state graph using binary decision diagrams (BDDs). Because this representation captures some of the regularity in the state space of sequential circuits with data path logic, one is able to verify circuits with an extremely large number of states. This new technique is demonstrated on a synchronous pipelined design with approximately 5*10/sup 20/ states. The logic that is used to specify circuits is a propositional temporal logic of branching time, called CTL or Computation Tree Logic. The model checking algorithm handles full CTL with fairness constraints. Consequently. it is possible to handle a number of important liveness and fairness properties. which would otherwise not be expressible in CTL. The method presented is not necessarily a replacement for brute-force state-enumeration methods but an alternative that may work efficiently when the brute force methods fail.<>
{"title":"Sequential circuit verification using symbolic model checking","authors":"J. Burch, E. Clarke, K. McMillan, D. Dill","doi":"10.1109/DAC.1990.114827","DOIUrl":"https://doi.org/10.1109/DAC.1990.114827","url":null,"abstract":"The temporal logic model algorithm of E.M. Clarke et al. (ACM Trans. Prog. Lang. Syst., vol.8, no.2, p.244-63, 1986) is modified to represent a state graph using binary decision diagrams (BDDs). Because this representation captures some of the regularity in the state space of sequential circuits with data path logic, one is able to verify circuits with an extremely large number of states. This new technique is demonstrated on a synchronous pipelined design with approximately 5*10/sup 20/ states. The logic that is used to specify circuits is a propositional temporal logic of branching time, called CTL or Computation Tree Logic. The model checking algorithm handles full CTL with fairness constraints. Consequently. it is possible to handle a number of important liveness and fairness properties. which would otherwise not be expressible in CTL. The method presented is not necessarily a replacement for brute-force state-enumeration methods but an alternative that may work efficiently when the brute force methods fail.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127479717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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